A New High Step-Up SC-Based Grid-Tied Inverter With Limited Charging Spike for RES Applications

Switched capacitor multilevel inverter topologies are attractive among industrial power electronics researchers due to their applicability in sustainable energy systems such as renewable energy source (RES) applications. In this paper, a new switched capacitor (SC)-based grid-tied seven-level inverter is proposed for renewable energy sources (RES) applications. The proposed inverter can generate a seven-level output voltage waveform with voltage boosting ability and a gain factor of 3. Also, the proposed topology can provide the self voltage balancing for capacitors. The most important challenge of the SC-based topologies, i.e., the capacitor charging spike current, is solved by applying a soft charging circuit in the charging loop of the capacitors. The soft charging circuit consists of an inductor and a power diode in the capacitor charging path. Using a small size inductor in the soft charging circuit, the proposed inverter can limit the input current spikes. Comprehensive experiment results and comparisons are presented to verify the accurate performance of the proposed inverter.


I. INTRODUCTION
Nowadays, the clean energy transition is a key to overcoming the CO2 emission of fossil fuels.The use of RES is increasing to provide a green future.Power electronic converters are needed to exploit the energy produced by PV systems and use them in industry and residential sectors [1], [2], [3].Multi-level inverters are promising solutions to enhance the performance of electric vehicles (EVs), PV systems, and other power electronic devices in medium-and high-power applications due to many advantages like requiring small size filter, low total harmonic distortion (THD), high efficiency, etc. [4], [5].
They can be categorized into three main basic structures, including flying capacitor (FC), neutral point clamped (NPC), and cascaded H-bridge (CHB) topologies [6], [7], [8].Meanwhile, the mentioned inverters suffer from the high number of circuit elements and require complex control systems, especially to provide a higher number of output levels.To generate higher output voltage levels, both NPC and FC topologies have to use more capacitors, power switches, and diodes.Balancing the capacitors' voltages in these structures is also a serious challenge.The reduced component-based topologies can solve the necessity of the higher number of switches and diodes of conventional structures [9].However, these topologies cannot provide the voltage boosting feature at the output.Some topologies have been proposed with additional circuits or using complex control strategies to overcome the capacitors' voltage balancing [10].
In these topologies, using additional circuits or complex control systems leads to increasing the cost, volume, and structural complexity.In order to solve the disadvantages of the conventional and reduced element structures, switched capacitor-based multilevel inverters have been proposed [11].In the switched capacitor topologies, by series-paralleling of capacitors with input dc power supply, the voltage boosting feature and capacitor voltage balancing can be obtained.[12], [13].Note that, in the switched capacitor topologies, the voltage boosting capability can be provided without using an extra boost stage.In the proposed topology of [14], to generate the negative half cycle of the output voltage waveform, an H-bridge circuit at the back end is used.
The recently-introduced switched capacitor-based MLIs, without using H-bridge units, require a large number of components, such as power switches and diodes to produce the output voltage waveform.Although a lower number of components are used in switched capacitor MLIs with H-bridge units, the total standing voltage (TSV) is very high.
Based on the voltage gain of switched capacitor-based inverters, the seven-level topologies can generally be classified into two groups.The seven-level SC-based multilevel inverters with a voltage gain of 1.5 have been presented in [15], [16], [17], [18], [19], [20].Also, the seven-level SC-based inverters with a voltage gain factor of 3 are proposed in [21], [22], [23], [24], [25].The presented SC-based inverters in [21] and [15] need more than one input DC power supply, which makes them improper for certain applications.In addition, the need for multiple input power supplies leads to increasing the cost and size of the power converter.In [19], a new cascaded seven-level topology is suggested.Meanwhile, the proposed topology needs auxiliary and complex control systems to balance the capacitor voltage.
The major challenge of the SC-based multilevel inverters is the charging current spike passage through the capacitors in the charging loop.This current spike can cause harmful current stress on the power electronic switches and diodes [26].In [27], the used capacitors are in charging mode during every switching cycle, and they are not discharged completely.So, without using an inductor, the amplitude of the inrush current can be limited.Meanwhile, these unwanted inrush currents cannot be eliminated completely.The presented topology in [5] can overcome the instant inrush currents in the series-connected capacitors using the quasi-resonant inductor.
Regarding the above-mentioned challenges, a new switched capacitor-based seven-level inverter using a single DC power supply is proposed in this paper.The proposed topology can generate a seven-level output voltage waveform with voltageboosting capability.Moreover, the proposed inverter provides voltage-boosting capability with a gain factor of 3 without using any extra DC-DC boost converter.As discussed, the major drawback of the switched capacitor-based inverters is the current spike during the capacitor charging modes.The proposed inverter also mitigates the capacitor charging spike current and provide soft charging employing a soft charging circuit that consists of an inductor and one diode.The rest of the paper is organized as follows: First, the proposed inverter is briefly introduced, and its operational modes are explained.Then, the duty cycle calculations will be carried out for three operating zones of the introduced converter.In addition, the inductance value of the output filter and the capacitance values of the implemented capacitors are computed.Also, soft-charging circuit design consideration is provided.Furthermore, the applied closedloop control system is presented, which adjusts injected active and reactive power to the grid and generates switching gate pulses for the proposed seven-level inverter.Moreover, the reliability of this converter is assessed using the Markov approach, to guarantee the proposed inverter's durability and solidity.Furthermore, power losses and efficiency analysis is performed.In order to highlight the advantages of the proposed inverter, a comparison of this structure with some resembling topologies is conducted and presented in detail.Finally, a laboratory prototype of the proposed inverter is assembled at 620 W output power, and the captured waveforms are illustrated in the experimental result section.

II. PROPOSED SEVEN-LEVEL SC-BASED INVERTER
The proposed seven-level SC-based grid-tied inverter is illustrated in Fig. 1.It uses a single DC-source, nine switches (S 1 ∼S 9 ), one diode (D 1 ), and two switched capacitors (C 1 & C 2 ) to generate seven-level output voltage waveform.Note that all the used power switches are unidirectional.In order to limit the capacitor charging spike during charging modes of the capacitors, a soft charging circuit is used in the proposed inverter.The soft charging circuit consists of a diode (D r ) and an inductor (L r ) connected in parallel.
In the switched capacitor-based topologies, the basic idea involves redistributing charges among the capacitors in a way that ensures their voltages are balanced [11], [12], [13].In the proposed grid-tied inverter, controlled switches connect and disconnect capacitors, allowing charges to flow between them.The switching sequence is carefully controlled to maintain balance.Switches are operated in a specific order to transfer charge between capacitors, adjusting their voltages.Self-balancing of capacitors in switched-capacitor-based inverters is an inherent feature and can be accessed without the need for an external controller system.
In the proposed topology, the utilized capacitors can be charged to V IN = V dc by connecting to input dc source, individually.Therefore, the voltage boosting capability with voltage gain of 3 can be achieved.Here's how the proposed SC-based inverter facilitates triple voltage gain: r This series connection allows for voltage tripling, leading to an increase in the overall output voltage.In the proposed configuration, the maximum blocked voltage (MBV) of the switches S 1 ∼S 5 is V IN and the MBV value of switches S 6 ∼S 9 is 3V IN .

III. OPERATION MODES OF SEVEN-LEVEL SC-BASED INVERTER
The operation modes of the proposed inverter during both positive and negative half cycles are shown in Figs. 2 and 3.In the mentioned figures, the red-dash line, blue-dash line, and green-dash line denote to the injected current to the grid path, charging current path of capacitors, and reactive power path, respectively.

A. FIRST OPERATION MODE
The First operation mode is illustrated in Fig. 2(a).It can be seen that in order to generate the zero level of output voltage waveform during the positive half cycle, the switches S 6 , and S 8 should be in on-state.Regarding Fig. 2(a), during the first

B. SECOND OPERATION MODE
The equivalent electrical circuit of the proposed inverter in the second operation mode during positive half cycle is illustrated in Fig. 2

C. THIRD OPERATION MODE
The third operation mode of the proposed inverter in the positive half cycle is shown in Fig. 2(c).Regarding Fig. 2 So, the second level of output voltage waveform can be generated.
In addition, the second path is generated by turning on the switches S 1 , S 3 , S 7 , and S 8 .By using this current path, the capacitor C 2 , and input DC source are connected in series to the output of the inverter.Therefore, the amplitude of output voltage will be equal to sum of capacitor C 2 voltage and input voltage (V out = V C2 + V IN = 2V IN ).As a result, the second level of output voltage waveform can be generated.Note that in this mode, the switches S 2 , S 4 , S 6 , and S 9 are in off-state.Also, the diode D 1 is in disconnected state.Considering Fig. 2(d), both switched capacitors are in discharging mode in this mode.In order to generate the third level of output voltage waveform during positive half cycle, the switches S 1 , S 4 , S 7 , and S 8 should be in on-state.Under this switching pattern, the capacitor C 1 , and C 2 , and input power supply are connected in series to the output of the inverter.

D. FOURTH OPERATION MODE
So, the amplitude of output voltage is equal to the sum of the voltages of capacitors C 1 , and C 2 , and input voltage Therefore, the third level of output voltage waveform in the positive half cycle can be generated.Based on this operation mode, it can be verified that the proposed inverter can provide the voltage boosting capability with the gain factor of 3. Note that in this mode, the soft charging circuit along with diode D 1 are in disconnected mode.In addition, the switches S 2 , S 3 , S 5 , S 6 , and S 9 are in off-state.
Negative half cycle:

E. FIRST OPERATION MODE
Fig. 3(a) indicates the first operation mode in the negative half cycle.During this operation mode, the zero level of output voltage waveform in the negative half cycle is generated.Considering Fig. 3(a), in this mode, similar to first mode in the positive half cycle, both switched capacitors C 1 , and C 2 are in charging mode.In this mode, in order to generate the zero level of output voltage waveform in the negative half cycle, the switches S 6 and S 8 should be in on-state.Based on Fig. 3(a), in this mode, the switches S 1 , S 4 , S 7 , and S 9 are in off-state.

F. SECOND OPERATION MODE
The equivalent electrical circuit of the second operation mode in the negative half cycle is illustrated in Fig. 3(b).Like the first operation mode in the negative half cycle, in this mode, the capacitors are still in charging mode.Regrading Fig. 3(b), to generate the first level of output voltage waveform in the negative half cycle, the switches S 6 , S 9 and diode D 1 should be in on-state.By using this switching pattern, the Input DC source is connected to the output of inverter in parallel.So, the amplitude of output voltage is equal to -V IN .Therefore, the first level in the negative half cycle can be generated.With respect to Fig. 3(b), in this mode, the switches S 1 , S 4 , S 7 , and S 8 are in off-state.Also, diode D r of soft charging circuit diode is in off-state.

G. THIRD OPERATION MODE
The third operation mode is shown in Fig. 3(c).In this mode, the aim is generating the second level of output voltage waveform during the negative half cycle.Regarding Fig. 3(c), there are two current paths to obtain the mentioned aim.The first current path can be provided by turning on the switches S 1 , S 5 , S 6 , and S 9 .By using this current path, the capacitor C 1 and input DC source are connected to output in series.So, the amplitude of output voltage is the sum of input DC voltage and voltage of capacitor The second current path is generating by turning on the switches S 1 , S 3 .S 6 , and S 9 .By using this path, the stored energy of capacitor C 2 along with input DC voltage are discharged to output.So, the amplitude of output voltage is the sum of input DC voltage and voltage of capacitor C 2 .As a result, the second level of output voltage in the negative half cycle can be generated.Regarding Fig. 3(c), in this mode, the switches S 2 , S 4 , S 7 , and S 8 are in off-state.Also, the diode D 1 and soft charging circuit (D r & L r ) are disconnected.

H. FOURTH OPERATION MODE
The fourth operation mode in the negative half cycle is shown in Fig. 3(d).This mode aims to generate the upper level of output voltage level during negative half cycle.To obtain this target, the switches S 1 , S 4 , S 6 , and S 9 should be in on-state.Under this switching pattern, the stored energies of capacitor C 1 and C 2 along with input DC voltage are injected to the output.So, the output voltage amplitude is the sum of capacitors C 1 and C 2 voltages, and input voltage ( Therefore, the third level of output voltage waveform in the negative half cycle can be generated.Considering Fig. 3(d), in this mode, both capacitors C 1 , and C 2 are in discharging state.Also, the switches S 2 , S 3 , S 5 , S 7 , and S 8 are in off-state.In addition, the diode D 1 and soft charging circuit (D r & L r ) are disconnected in this mode.

IV. DUTY CYCLE CALCULATIONS IN THREE OPERATION ZONES OF THE PROPOSED INVERTER
Fig. 4 shows the output voltage waveform during positive half cycle along with grid current waveform.Based on Fig. 4, the seven-level output waveform of inverter has three operation zones (Zone I ∼ Zone III) in the positive half cycle.
Considering Fig. 4, it can provide the control system of the proposed grid-connected inverter.The sampling frequency and maximum switching frequency can be denoted by f smp , and f m respectively.Furthermore, the sampling frequency is two times of maximum switching frequency.
The equations of grid voltage and injected current to the grid can be written as: Where, V g,max , and I g,max are maximum values of grid voltage and injected current to the grid, respectively.Regarding Fig. 4, V out and v g denote the output voltages of inverter and grid, respectively.

A. OPERATION ZONE I
Considering Fig. 4, in the zone I, the output voltage waveform of the inverter is between zero and V IN .The switching duty cycle (d 1 ) of the inverter during zone I can be obtained as follows, applying the inductor volt-second balanced (IVSB) law.
Replacing ( 1) in ( 4), the duty cycle of zone I can be obtained as follows: (5)

B. OPERATION ZONE II
As seen from Fig. 4, the output voltage waveform of the inverter is located between V IN and 2V IN .The switching duty cycle of the inverter (d 2 ) during zone II can be obtained by applying IVSB law for the voltage across the inductor and can be written as follows: With respect to (5), the (7) can be rewritten as:

C. OPERATION ZONE III
It can be seen from Fig. 4, that the output voltage waveform is between 2V IN and 3V IN during operation zone III.The switching duty cycle (d 3 ) of the proposed inverter in the zone III can be calculated by applying the IVSB law for the voltage across the output filter inductor and can be expressed as: Considering (7), the (10) could be rewritten as: Finally, the equations of t 1 and t 2 can be expressed as:

V. CALCULATION OF THE INDUCTANCE VALUE OF OUTPUT FILTER AND CAPACITANCE VALUES OF UTILIZED CAPACITORS
Here, the inductance value of the output filter and the capacitance values of the implemented capacitors are computed.
In order to calculate the inductance value of L f , the passing current through it can be expressed as: (14) Regarding (14), the current ripple of the inductor can be calculated as: Therefore, using ( 1) and ( 10), the current ripple of the inductor can be rewritten as follows By solving (16), the final value of current ripple of inductor L f can be obtained as: Therefore, considering (17), the final value of L f can be calculated as: ) Also, the desired values of capacitors in the proposed inverter are computed.In order to calculate the capacitance of the capacitors C 1 , and C 2 , the longest discharging period (LDP) of each capacitor during an output cycle is considered.Fig. 5. Shows the LDP cycles of capacitors C 1 , and C 2 in a full switching period (T).Regarding LDP of each capacitor C 1 , and C 2 , the optimal capacitance values of C 1 , and C 2 by considering the permissible maximum value of the voltage ripple can be calculated as follows: Where, ω = 2πf .Also, f, and V max denote grid frequency, and the maximum voltage ripple, respectively.Also, ωt is the discharging period of the capacitor and can be calculated as follows: Regarding Fig. 5, the sinewave with a peak of 3.5 V IN cuts the seven-level output voltage waveform at points (ωt a , 1.5V IN ), (ωt a , 2.5V IN ) and (ωt a , 2.5V IN ).So, the ωt a , ωt b , and ωt c can be calculated as:

VI. SOFT-CHARGING CIRCUIT DESIGN AND VERIFICATION
As mentioned in the manuscript file, a soft charging circuit is used in the charging loop of used capacitors of the proposed topology to limit the capacitor charging current spike.This soft charging circuit includes an inductor (L r ) and a power electronics diode (D r ).To answer your comments, the following revisions have been performed: In the following, the detailed equations and analysis are provided.
The equivalent circuit of the charging loop of capacitor C 1 is shown in Fig. 6.Regarding Fig. 6, R eq , denotes the equivalent resistance of the charging loop.
Based on Fig. 6, by applying the KVL law in the charging loop of capacitor C 1 , the following equations can be obtained: By solving (22), the resonance frequency (ω r ) and damping factor (α) are obtained as follows: To design the optimal size of the inductor L r which is applied to limit the capacitor charging current spike, the value of the damping index should be smaller than the resonance frequency, so it can be expressed as: By squaring both sides of (24) and simplifying it, the desired inductance of inductor L r can be obtained as: Where R eq is the equivalent resistance of the charging loop of capacitor C 1 and can be expressed as: Where, R D1 , R DS , r ESR,C , r Lr denote the forward-voltage drop of power diode D 1 , on-state resistance of the switches S 2 , S 5 , the equivalent series resistance of the capacitor, and the internal resistance of the inductor L r in the charging loop, respectively.
Further, the capacitor charging current can be calculated as follows: During the time interval of t P , this current reach to its maximum value obtained by the below equation: Now, the maximum value (peak) of the charging current during t P can be obtained as: The maximum value of the charging current of the capacitors without using the inductor L r in the charging loop can be calculated as: So, the percentage of reduction in inrush current magnitude of capacitors can be calculated as: In order to verify the soft charging feature of the proposed inverter, the simulation has been performed by MAT-LAB/Simulink software in the presence and absence of the L r inductor and investigates the effect of L r on the capacitor current spike.In the simulation, L r has been assumed a very small inductor with the inductance value of 0.1 mH as the same as it's experimental description (see Table 3).The capacitor charging current waveforms of capacitor C 1 in the presence and absence of the inductor L r are shown in Fig. 7(a) and (b), respectively.Also, the capacitor charging current waveforms of capacitor C 2 in the presence and absence of the inductor L r are illustrated in Fig. 7(c) and (d), respectively.According to these figures, the capacitor current spike of each capacitor is limited to 25 A in the presence of the L r .While, in the absence of the L r , the current spike of each capacitor has reached to 300 A. So, regarding (31), the percentage of reduction in inrush current magnitude of capacitor C 1 and C 2 are equal to 8.33 %.

VII. APPLIED CLOSED LOOP CONTROL SYSTEM FOR GRID-TIED INVERTER
The block diagram of the applied control system in the proposed grid-connected seven-level inverter is illustrated in Fig. 8(a).The control system is designed to regulate the operation of a seven-level grid-tied inverter.This control system adjusts both injected active and reactive power flows to the grid and generate switching gate pulses of the switches (S 1 ∼S 9 ) of the introduced inverter.By using this control strategy, a sinusoidal current waveform can be injected to the grid.The conversion unit is a crucial component responsible for transforming quantities between different coordinate systems.Utilizes transformation techniques (dq transformation) to generate the d-axis (active power) and q-axis (reactive power) components of the grid current.Similar transformation is applied to generate the d-axis and q-axis components of the grid voltage.
Regarding Fig. 8(a), in this control system, the (aβ0/dq0) conversion unit is used to generate the d-axis and q-axis of grid current which are denoted by (I d ), and (I q ), respectively.Also, the d-axis of grid voltage (V d ) and q-axis of grid voltage (V q ) are generated by using the (aβ0/dq0) conversion unit.Note that here, I d and I q denote active and reactive power flows, respectively.Regarding control system, the reference values d-axis (I * d ) and q-axis (I * q ) of the injected grid current are obtained as: Using above-mentioned reference values, both active and reactive power can be controlled.Considering closed loop control system, it is obvious that the AC components are delivered to d-q axis.Also, the desired value of the injected grid current can be obtained by using a proportional-integral (PI)-based current controller in the control system of the inverter.
At last, the V * a is delivered to the pulse width modulation (PWM) unit so, the switching gate pulses of the switches (S 1 ∼S 6 ) can be generated and applied to gate drivers.
The control logic of the system can be summarized as follows: r Compares the actual d-axis (I d ) and q-axis (I q ) compo- nents of the grid current with the reference values (I * d and I * q ).r Generates error signals based on the differences between the actual and desired values.
r Utilizes a control algorithm (a PI controller) to process these error signals.
r The controller generates control signals that drive the inverter to adjust the switching gate pulses (S 1 ∼S 9 ).A typical PWM method is shown in Fig. 8(b).Based on this figure, V r1 , V r2 , V r3 , and V r4 are the shifted level carrier waveforms.
In summary, the control system involves a conversion unit for transforming quantities, a control system for regulating active and reactive power flows, and a feedback mechanism to adjust the inverter's switching gate pulses.

VIII. POWER LOSSES AND EFFICIENCY ANALYSIS
In order to derive the loss break-down and efficiency of the proposed seven-level inverter, the power losses of the components are derived in this section.There are two types of losses in this inverter: switching losses, and conduction losses.Switch loss includes the turn-on and turn-off switching losses and conduction losses.Furthermore, diode loss consists of conduction losses.Finally, capacitors and inductors only have conduction losses.Also, the utilized inductor's Ferrite core has a 2.2 W core losses.

A. CONDUCTION LOSS
Conduction losses arise due to various factors during the operation of power switches, power diodes, and passive components in the circuit.These factors include the on-state resistance of the switches (R DS ), the forward-voltage drop of power diodes (V Fw-D ), the equivalent series resistance of the capacitor (R C ), and the internal resistance of the inductor (R L ).Taking into account the aforementioned factors: Where q(t) and p(t) refer to the number of power switches and power diodes in the current trajectory.The overall conduction losses of the proposed inverter can be derived as follows:

B. SWITCHING LOSS
The switching losses of the circuit includes the on-state and off-state losses of the switches.In order to ease the analysis, the across voltage and passing current of the switches are linearized.As a result, the on-state and off-state switching loss for each power switch will be attained as follows: I SW and I' SW are the passing currents of each power switch after turning on and just before turning off, respectively.N ON , and N OFF denote the number of turning on and turning off of the switches during a full switching period, respectively.Also, t ON is the sum of Turn-On Delay Time and Turn-On Rise Time.t OFF is sum of Turn-Off Delay Time and Turn-Off Fall Time.It should be mentioned that the values t ON and t OFF can be accessed in the data sheet of the utilized power switches in the proposed inverter.Moreover, T S and f S are the switching period and the switching frequency of the inverter, respectively.The overall switching losses of the proposed inverter will be achieved as follows: 5) and ( 8), the overall losses of the proposed inverter will be obtained: Fig. 9 visualizes the proportion of losses for each power component of the introduced inverter.In Fig. 9(a), the pie chart of the percentage of losses of the power switches, power diodes, inductor, and capacitors are shown.It is evident that the conduction losses hold a higher share of overall losses in comparison with the switching losses.Furthermore, the power switches hold 4.55% of the overall losses of the proposed inverter.What's more, in Fig. 9(b), the detailed share percentage of switches' losses (sum of switching and conduction losses of the power switches) for each power switch is derived and displayed.
The overall power losses of the proposed inverter using the above equations is 28.42 W. Therefore, the theoretical efficiency of the proposed inverter for 620 W output power is obtained 95.6%.It is worth mentioning that the experimental efficiency for the mentioned output power is 94.8%, which is lower than the calculated analytical efficiency, due to the assumptions of components to be ideal in theory.

IX. RELIABILITY ASSESSMENT
The reliability analysis of converters provides a systematic approach for assessing the reliability of these complicated systems, which is important for assuring their safe and efficient operation in different applications.The reliability assessment of the proposed inverter in this article is performed using Markov Approach [4], which is a mathematical tool used to assess the probabilities of transitions between different states in a system over time.In case of multi-level inverters, the Markov chain refers to the possible states of the system, such as normal operation, partial failure, and complete failure, and the probabilities of transitions among these states as a result of component failures.
The reliability analysis using the Markov approach involves calculating the reliability function, which is the probability that the system will remain in a specified state.Using MIL-HDBK-217F handbook and the equations in [28], the failure rates of the proposed inverter is derived, which is mentioned in Table 1.According to the mentioned rates, the failure rates of active semiconductor devices in the proposed structure hold a 304 VOLUME 5, 2024 Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.higher total share in comparison with the passive components like inductors and capacitors.
In addition, based on the current path throughout the inverter, the rate at which the current passes through each component have a close relation with the reliability of the whole inverter, as well as many other factors like power dissipation, the ambient temperature, and basic failure rates of each component.The reliability equation of the proposed inverter after computing the failure rates is attained using the following equation: Considering the failure rates and (21), the reliability curve of the proposed inverter versus time will be achieved.Fig. 10 portrays the exponential reliability curve versus time.Actually, as time passes, the reliability of the proposed inverter is reduced.Based on this figure, in order to ensure the reliability, it is important to take into consideration of several aspects during the design, assembly, and applying the proposed inverter.
Therefore, a thorough reliability study like this assessment, is helpful in projecting the durability of the inverter.

X. COMPARISON
In this section, in order to highlight the advantages of the proposed inverter, a comparison of this structure with some resembling topologies is conducted and presented in detail.The comparison is conducted based on some items such as the number of components, voltage boosting feature, voltage gain factor, spike current limitation, per unit value of maximum blocked voltage (MBV pu ), per unit value of total standing voltage (TSV pu ), output power (P out ), total volume (mm 3 ), power density (W/mm 3 ), and CF/N level .The comparison results are presented in Table 2.
Note that in order to calculate the total volume of each topology, the volume of utilized switches, diodes, and capacitors in each inverter are considered.Also, in order to obtain the implementation cost for each inverter, the CF/N L (cost function/number of levels) is calculated as follows: (44) Note that the power density of the modified topology and other compared topologies are calculated as (23).
Power density (W/mm 3 ) = P out (W ) Total volume (mm 3 ) (45) where P out and total volume denote the output power and total volume of each topology.
Regarding Table 2, it can be seen that among other compared topologies, only the proposed inverter can limit the capacitor charging current spike of capacitors during charging mode.Compared with topologies of [16], [17], [18], [20], [22], [23], [25], and [29], the proposed inverter has the maximum value of power density.Considering Table 2, from the point of CF/N level , the proposed inverter has the minimum vale of this cost factor compared with all of topologies.Therefore, it can be said that the proposed structure is cost-effective, compared to other compared topologies.
Considering Table 2, compared with topologies of [15], [16], [21], [24], [25], [29], the proposed inverter has the minimum value of TSV pu .Also, the proposed inverter can provide the voltage boosting feature with a gain factor of 3, unlike the topologies of [16], [17], [18], [19], [20].They have a larger value of CF/N level than the proposed inverter.Therefore, these structures are not economically viable compared to the proposed structure.Based on Table 2, it can be concluded that the proposed inverter provides an overall enhancement on the number of components, boosting factor, reduced TSV pu , reduced CF/N level , spike current limitation, and power density.

XI. EXPERIMENTAL RESULTS
In this section, a laboratory prototype of the proposed inverter is assembled at 620 W output power, and the captured waveforms are illustrated.The specifications of the used components in the experimental laboratory prototype are summarized in Table 3.In addition, the photograph of the experimental laboratory prototype of the proposed inverter is illustrated in Fig. 11.
Fig. 12(a) shows the seven-level output voltage and injected current to the grid at the unity power factor (PF). Regarding Fig. 12(a), it can be seen that the maximum value of output voltage of the inverter and the injected current to the local grid are about 400 V and 4 A, respectively.So, by using the applied control strategy the proposed inverter can inject a 620 W active power to the grid.Regarding Fig. 9(a), the proposed grid-connected inverter has good tracking capability of the reference current through the output inductor-based filter.Regarding Figs. 12, and 14, the inverter, by applying the closed-loop control system, can inject the sinusoidal current into the grid under different conditions of power factor.
In order to study and investigate the dynamic response of the proposed grid-connected inverter, a step change of the reference current (I * ) is applied and the obtained results are shown in Fig. 15.The step change of the injected grid current is a change from 4 A to 6 A. Therefore, the injected active power increases from 620 W to 920 W.
Regarding Fig. 15, it can be concluded that the proposed inverter has a good response under the applied step change in the amplitude of the reference current from 4 A to 6 A.
The voltage stress of the switches S 1 ∼S 9 are shown in Fig. 16   In addition, THD (%) of the grid current in the experiment results, for unity, leading, and lagging power factor (PF) are determined according to Table 4. Considering Table 4, it can

TABLE 4. THD (%) of the Grid Current in the Experiment Results
be observed that the THD of injected current to the grid under different conditions of PF such as unity PF, leading PF, and lagging PF are 3.56%, 3.45%, and 3.73%, respectively.Based on IEC 61000-3-2 and IEEE 1547.2-2008standards the limit of THD of injected current to the grid is less than 5%.Therefore, the proposed grid-tied inverter can pass these mentioned standards.
Considering the experimental results presented above, it can be concluded that the proposed grid-tied switched capacitor-based inverter has a good performance and all the mentioned features can be confirmed for it.

XII. CONCLUSION
In this paper, a new high step-up switched-capacitor-based seven-level grid-connected inverter is presented.The proposed inverter uses only a single input power supply to generate a seven-level output voltage waveform with high step-up gain factor of 3. In order to control both active and reactive power, and generate the switching gate pulses of the switches, a closed loop control system has been applied.
In order to provide the soft charging feature and limit the spike current of the capacitors during the capacitor charging mode, a soft charging circuit is used in the proposed inverter.In the proposed inverter, to provide the voltage boosting feature, the series-parallel switching pattern of the capacitors has been applied.Regarding the applied closed-loop control system, by using a small filter inductor, the injected current can be completely controlled at any desired power factor.
In this research study, to show the advantages of the proposed inverter, a comprehensive comparison with some other recently-presented seven-level inverters has been performed and the comparison results proved the benefits of the suggested grid-tied inverter over other topologies.Also, the design consideration of passive components such as capacitors and filter inductor has been done.In addition, the reliability analysis of the proposed switched capacitor-based inverter has been considered in the paper.
Finally, in order to verify the accurate performance of the proposed inverter and its advantages and features, an experimental laboratory prototype for the proposed inverter at 620 W output power has been built and the obtained results have been presented.

FIGURE 2 .
FIGURE 2. Operation modes during the positive half cycle: (a) first operation mode, (b) second operation mode, (c) third operation mode, and (d) fourth operation mode.

FIGURE 3 .
FIGURE 3. Operation modes during the negative half cycle: (a) first operation mode, (b) second operation mode, (c) third operation mode, and (d) fourth operation mode.

Fig. 2 (
Fig. 2(d) illustrates the fourth operation mode of the proposed SC-based inverter.Considering Fig.2(d), both switched capacitors are in discharging mode in this mode.In order to generate the third level of output voltage waveform during positive half cycle, the switches S 1 , S 4 , S 7 , and S 8 should be in on-state.Under this switching pattern, the capacitor C 1 , and C 2 , and input power supply are connected in series to the output of the inverter.So, the amplitude of output voltage is equal to the sum of the voltages of capacitors C 1 , and C 2 , and input voltage(V out = V C1 + V C2 + V IN = 3V IN ).Therefore, the third level of output voltage waveform in the positive half cycle can be generated.Based on this operation mode, it can be verified that the proposed inverter can provide the voltage boosting capability with the gain factor of 3. Note that in this mode, the soft charging circuit along with diode D 1 are in disconnected mode.In addition, the switches S 2 , S 3 , S 5 , S 6 , and S 9 are in off-state.Negative half cycle:

FIGURE 4 .
FIGURE 4. Positive half cycle output voltage waveform, grid voltage, and three operation zone.

FIGURE 5 .
FIGURE 5. Seven-level output voltage waveform with charging and discharging modes of the capacitors.

FIGURE 6 .
FIGURE 6. Equivalent circuit of charging loop of capacitor C 1 .

FIGURE 7 .
FIGURE 7. Simulation results: (a) chagrin current of capacitor C 1 in the presence of L r , (b) charging current of C 2 in the absence of L r , (c) chagrin current of capacitor C 2 in the presence of L r , and (d) charging current of C 2 in the absence of L r .

FIGURE 8 .
FIGURE 8. (a) Closed loop control block diagram (b) carrier waveforms and V * a waveform.

FIGURE 9 :
FIGURE 9: Pie charts of the percentage of losses in circuit components, (a) share of losses percentage for the all components of the inverter, (b) share of losses percentage for the power switches.

FIGURE 11 .
FIGURE 11.Photograph of the experimental prototype of the proposed grid-tied inverter.
(a)-(c).The voltage stress waveforms of switches S 1 , S 2 , and S 3 are illustrated in channel 1, 2, and 3 (CH1-CH3) of Fig. 16(a), respectively.Regarding this figure, the MBV of switches S 1 , S 2 , and S 3 are about 120 V or V IN .

FIGURE 15 .
FIGURE 15.Experimental results under a step change in the amplitude of reference current: CH1: output voltage, CH2: voltage across capacitor C 2 , CH3: voltage across capacitor C 1 , CH4: grid current.