Comprehensive Analysis and Stabilization of a B2B HVDC System Connecting Two Extremely Weak Grids Considering the Impact of Power Feedforward Compensation

Back-to-Back (B2B) HVDC systems can enhance cross-regional transmission capacity and overall power system stability. However, their use in interconnecting two extremely weak grids can compromise system stability. This paper presents a comprehensive stability analysis of a B2B HVDC system to distinguish the root causes of instability mechanisms and identify the critical short circuit ratio (CSCR) of each converter station under inverter and rectifier operations considering the impact of power feedforward compensation of the dc-bus voltage controller. The study also investigates the stability implications and CSCR changes when a dc transmission line connects the converter stations, creating a point-to-point (P2P) HVDC system. Eigenvalue analysis, based on detailed small-signal modeling, showed that three distinct instability mechanisms, high-, low-, and medium-frequency instabilities, can compromise the operation of VSC stations under extremely weak grid conditions. Notably, the medium-frequency instability observed in the P2P HVDC system during inverter operation is predominantly caused by the power feedforward compensation of the dc-bus voltage controller. Furthermore, the analysis reveals that the CSCRs for dc-bus voltage-controlled VSC stations are higher in comparison to power-controlled ones. This suggests that a dc-bus voltage-controlled VSC is more susceptible to instability in weak grid scenarios than its power-controlled counterpart. Active compensators are designed based on participation factor analysis to mitigate the identified instabilities. The findings are validated with extensive simulations and real-time hardware-in-the-loop tests, demonstrating the analysis's accuracy and the proposed compensators' efficacy.


A. Variables v tdq
VSC terminal voltage d-q components.v sdq PCC voltage d-q components.v gdq AC grid voltage d-q components.i sdq , i gdq VSC and ac grid currents d-q components.V dc DC-link voltage.P t VSC terminal power.
δ PCC voltage angle.SC MVA PCC short-circuit power.P V SC VSC rated power.
B. Parameters R f , L f , C f AC filter resistance, inductance, and capacitance.

R g , L g
Grid resistance and inductance.C dc DC-bus capacitance.

G c
Current loop PI controller.

I. INTRODUCTION
Voltage-source converter (VSC) technology has emerged as a prominent solution in high voltage direct current (HVDC) systems, offering numerous advantages such as independent control of active and reactive power, the ability to operate under weak grid conditions and a compact footprint.In particular, B2B HVDC systems, designed to offer seamless asynchronous interconnection between different ac systems, have become increasingly prevalent in the power grid over recent years.For instance, in the U.S., seven B2B HVDC facilities enable a 1320 MW power flow between its eastern and western interconnections [1].A B2B HVDC system in China is designed to improve the cross-region transmission capacity between the southwest and central China power grid [2].The B2B HVDC facilities can improve the power system reliability and security by minimizing the impact of faults and improving system damping [3].However, a B2B system interconnecting two very weak ac systems is challenging and can lead to system instability.Connecting a VSC to a very long transmission line frequently establishes an interface with a weak grid.The strength of the ac system is gauged using the short circuit ratio (SCR) metric: an SCR value below 3 signifies a weak system, dropping below 2 indicates a very weak grid, and the most critical state is when SCR equals 1.While employing linecommutated converters (LLCs) in grids with an SCR<2 is inadvisable due to stability challenges, VSCs, with their inherent self-commutation capabilities, are theoretically capable of supplying power even to an extremely weak grid [4], [5].Yet, in practice, introducing VSCs to these grids can lead to instability issues [6], [7], [8].Investigating the root causes of these instabilities and devising effective stabilization methods has captivated researchers for the last decade.
The phase-locked loop (PLL) is a crucial element in a gridconnected VSC, ensuring synchronization with the power grid.A body of research mainly attributes the instability problems of VSCs under weak grids to the dynamics of PLL [9], [10], [11], [12], [13].Using frequency domain modeling, the analysis in [12], [13] uncovered that the PLL dynamics significantly influence the VSC output impedance under weak grid conditions.Notably, the VSC instability is caused by the negative incremental resistance of the q-q channel impedance, and a larger PLL bandwidth extends the frequency range of this instability.Studies [14], [15] highlight the profound impact of PLL parameters on the system stability margin, leading to the recommendation of meticulous tuning of PLL parameters as a measure to alleviate system instability.It is advised to reduce the PLL bandwidth to enhance overall system stability.However, limiting the PLL bandwidth degrades the system's transient response and robustness [16].
Recognizing these challenges, advanced PLLs are proposed in the literature to mitigate the negative influence of the PLL under a weak grid, thereby offering a balance between system stability, transient response, and robustness [17], [18], [19], [20], [21].Reference [17] introduces a modified PLL to ensure decoupling from grid impedance by adjusting its input to the PCC voltage and grid admittance product.However, this method's dependency on online grid impedance measurement questions its reliability.Similarly, [18] proposes a PLL with constant and low coupling independent of grid strength or bandwidth, though at the cost of increased PLL structure complexity.Also, the PLL performance under an extremely weak grid (SCR = 1) was not verified.Another solution is proposed in [20], wherein a modified PLL based on a bandpass filter is introduced to reshape the VSC output impedance.Reference [21] details the incorporation of an active damping controller into the PLL, enhancing its performance under weak grid conditions, though this necessitates modification of the PLL's internal structure.Other studies proposed artificial bus-based synchronization methods [16], [22], allowing VSC synchronization to a virtual but more robust node by changing the PLL input.Despite their innovation, these methods depend on grid impedance measurement.Alternatively, the power synchronization control (PSC) emerges as a promising solution, ensuring weak grid interconnection stability without PLL synchronization by emulating synchronous machine behavior [23], [24].Nevertheless, its capability is limited in handling ac-side faults, necessitating a switch to conventional vector current control to prevent converter current limit violation.
While the studies cited previously focus on the significant impact of the PLL as a primary cause of VSC instability under weak grid conditions, alternative perspectives in the literature present a different facet of the issue.These sources suggest that VSC weak grid instability is primarily influenced by either the outer or inner control loops of the classical vector control [25], [26], [27], [28], [29].In [25] and [26], the ac voltage controller emerges as a primary factor affecting instability under weak grid conditions.As the PCC voltage is sensitive to the variation of active and reactive power, the authors suggested accelerating the ac voltage controller to enhance reactive power support.The work in [27] showed that the conventional power/dc-bus voltage controller is unstable under high-power demands at a weak grid.To mitigate the instability, the authors propose modifying the outer control loops by including decoupling gains, a solution to address the interactions between the ac-bus voltage and active power control.Despite the enhancement, the need for a gain scheduling controller to ensure stability at different operating points is challenging.Studies [28], [29] identify the current control loop as the dominant factor for VSC instability under a weak grid.Hence, in [28], it is suggested to restructure the PI current controller as an IP controller to diminish instability.
Alternatively, the research outlined in [30], [31], [32] contends that the instability of VSC under a weak grid stems from the adverse interactions among various VSC control loops and not the effect of a single controller.The work in [32] illustrates that a larger PLL bandwidth intensifies the coupling between the outer control loops (active/reactive power control), potentially leading to system instability under a weak grid.The study in [31] utilizes modal resonance analysis to delve into the roots of instability under a weak grid, revealing that intensified interactions between the PLL and dc-bus voltage controller under such conditions destabilize the low-frequency mode.The research in [30] attributes system instability primarily to PLL and current controller interactions.The authors introduced a multi-variable controller based on optimal linear quadratic theory to mitigate the instability and enhance the VSC performance.
The VSC weak grid instability can occur under both rectifier and inverter modes of operation [33], [34], [35].The work in [33] demonstrated that the causes of VSC weak-grid instability differ depending on its operation mode.Under inverter operation, the instability is primarily caused by the interactions between the current controller and PLL.In contrast, rectifier instability is due to the interactions between the outer controllers and PLL.However, this study only investigated the low-frequency instability mechanism and the CSCR for inverter or rectifier operation was not identified.In [34], it was shown that VSC stability under a weak grid is more critical under rectifier operation.A VSC is stable for a wider range of SCR under inverter operation than rectifier operation.The study in [36] investigated the impact of power flow variation on the stability of a P2P HVDC system.It was shown that the HVDC system exhibits instability when the dc-voltagecontrolled VSC operates as a rectifier.However, the study did not consider the impact of ac grid strength on the stability of the HVDC system.The transient stability of a B2B system interconnecting two weak autonomous ac microgrids (IMGs) was presented in [37], [38].The finding in [37] showed that the PLL parameters, dc voltage controller parameter and the initial dc capacitor voltage considerably impact the critical modes and may destabilize the IMGs.However, the analysis was performed at SCR of 2, which may not reveal all instability mechanisms, and the study only focused on the initial dc voltage transient stability.
While the current research offers valuable insights into the instability mechanisms of VSC under a weak grid, it falls short in presenting a comprehensive stability analysis that distinguishes these instabilities and identifies the CSCR, considering the various VSC operation modes (rectifier/ inverter) and control modes (dc-bus voltage control/active power control).Furthermore, the literature has yet to discuss the impact of the dc-bus voltage controller power feedforward compensation loop on VSC stability under weak grid conditions.To bridge these gaps, this paper delivers a thorough stability analysis of both B2B and P2P HVDC systems.The primary contributions of this work are as follows: 1) An in-depth stability analysis of B2B and P2P HVDC systems connected to extremely weak grids is presented.This paper uncovers the root causes of low-, medium-, and high-frequency instabilities based on comprehensive small-signal models.2) A thorough comparison of stability implications and CSCR values between B2B and P2P HVDC systems is presented, focusing on the impact of the dc-bus voltage controller power feedforward compensation.3) This paper proposes effective compensation methods to mitigate various instabilities and enhance system performance under an extremely weak grid.4) The proposed active compensators are rigorously evaluated against existing methods using detailed nonlinear time-domain simulations and real-time simulations tests.The paper's structure is as follows: Section II outlines system control and modeling.Section III delves into the eigenvalue analysis of B2B and P2P HVDC systems connected to extremely weak grids.Section IV discusses the proposed active compensation methods.Section IV details the simulation and real-time simulation studies, respectively.Lastly, Section V summarizes the conclusions.

II. SYSTEM CONTROL AND MODELING
The configuration of a B2B HVDC system, employed to provide an asynchronous link between Grid 1 and Grid 2, is depicted in Fig. 1(a).The system consists of two converter stations: VSC1 and VSC2.VSC1 is designated as the power-controlled VSC station, while VSC2 is responsible for regulating the DC-bus voltage.The dc sides of the two converters are directly connected to the dc-link capacitor (C dc ).On the ac side, each converter is connected to the ac system through an LC filter designed to mitigate high-frequency switching harmonics, as portrayed in Fig. 1(b).The ac system is represented by a Thevenin impedance (Z g ) and a stiff voltage (V g ).The following subsections delve into the comprehensive modeling of the entire system and the derivation of the small-signal model.

A. VSC AC-SIDE MODELING
Referring to Fig. 1(b), the ac-side dynamics of each VSC station can be represented by ( 1)-( 3) in the gird d-q reference frame as follows: A crucial metric used to define the strength of a grid is the short circuit ratio (SCR), defined as

B. VSC VECTOR CONTROL MODELING
Vector control is a predominant technique employed for regulating grid-connected VSCs.As illustrated in Fig. 2, the architecture of the VSC control system is bifurcated into outer and inner control loops.The primary functions of the outer loops are to manage the dc-bus voltage or active power injection and to regulate the PCC voltage.Conversely, the inner loops are dedicated to tracking the VSC's d-q currents.To ensure a fast current response, the bandwidth of the inner loops should be set notably large yet maintained substantially below the VSC switching frequency, typically around one-tenth of the switching frequency.Meanwhile, for cascade control stability and robustness, the bandwidth of the outer loops is typically designed to be between 10-20% of the inner loops [39].Modeling of the VSC control system will be elucidated in the succeeding subsections.

1) DC-BUS VOLTAGE AND ACTIVE POWER CONTROL
This control mechanism produces the reference d-axis current, denoted as i * sd .This is achieved by comparing either the desired dc-bus voltage V * dc , or the active power setpoint P * , to their respective actual values.The resultant error is then passed through a PI controller represented by G vdc,p (s).Typically, a feedforward component (P ext ) is incorporated, as depicted in Fig. 2, to enhance the transient response of the dc-bus voltage.Consequently, the reference current i * sd can be mathematically described by This control mechanism addresses the discrepancy between the desired and actual voltage at the PCC using a PI compensator G ac (s).As an outcome, the reference q-axis current, i * sq , is formulated as

3) INNER CURRENT CONTROL LOOP
This control loop regulates the d-q axis currents of the VSC utilizing a PI compensator, denoted as G c (s).To ensure the independent control of active and reactive currents, the decoupling term ( jωL f i c sdq ) is employed.Moreover, PCC voltage feedforward is incorporated to mitigate potential voltage disturbances, ensuring robust current control.The d-q axis terminal voltage of a VSC can be formulated as

C. PLL DYNAMICS
The PLL is responsible for synchronizing the VSC to the grid by estimating the phase angle of the PCC voltage [40].Under weak grid conditions, the dynamics of the PLL can significantly influence the performance and stability of VSC.Therefore, accurate modeling of the PLL is vital when analyzing the stability of a VSC connected to a weak grid.The structure of the classical PLL is shown in Fig. 3(a).It uses a PI compensator, G pll (s), to regulate the q-axis PCC voltage at zero and generate the angular frequency ω.The angular frequency is then integrated to produce the synchronization angle δ.
It is important to highlight that a grid-connected VSC system encompasses two distinct d-q frames: the grid's d-q frame and that of the converter [41].Under steady-state conditions, these frames are synchronized.However, when the system undergoes transient disturbances, a phase discrepancy emerges between the two frames, as illustrated in Fig. 3(b).This misalignment can be attributed to the PLL's response time.For a comprehensive state-space representation of the system, it is imperative to consistently represent all variables in either the grid or the converter frame.The relationship between the d-q frames, as derived from Fig. 3(b), can be expressed as

D. DC-SIDE MODELING
As depicted in Fig. 1, the dc-sides of the VSCs are connected directly through the dc-bus capacitor.Applying the power balance, the dynamics of the dc-bus voltage can be described as 1 2 C dc sV 2 dc = P in − P e (11) Considering a lossless VSC, then )

E. SMAL-SIGNAL MODEL DEVELOPMENT AND VERIFICATION
Equations ( 1)-( 13) define the large-signal model of a VSC.Using the perturbation theory, the linearized small-signal model for VSC1 and VSC2 can be defined in ( 14) and ( 15), respectively.
Then, the augmented small-signal model of the B2B HVDC system can be described by where X = [ X1 X2 ] T and Ũ = [ Ũ1 Ũ2 ] T are the state and input vectors, respectively.
T are the characteristics and input matrices, respectively.The specifics of the matrices are excluded due to space constraints.To confirm the validity of the developed small-signal model, the B2B HVDC system in Fig. 1(a) is simulated in MAT-LAB/Simulink, with system and control parameters listed in the Appendix.The detailed Simulink and small-signal models in (15) have been tested under a 5% step change in the active power injection of VSC1.The responses of the variables I sd1 , V sd1 , V dc , I sd2 and V sd2 are shown in Fig. 4. The results verify the accuracy of the developed linear model of the system.

III. STABILITY ANALYSIS
Using the derived small-signal model in (14), it is possible to determine the system's eigenvalues to assess its stability and dynamic performance.Additionally, the model enables the application of linear system analysis techniques, such as determining the participation factors and assessing parameter sensitivity, to analyze the distinct oscillation modes inherent in the system.Based on these analyses, proper active damping techniques can be proposed to mitigate potential instabilities.In the following subsection, eigenvalue analysis is utilized to evaluate and compare the stability of both B2B and P2P HVDC systems under SCR variations.VSC1 is the power-controlled VSC station for both systems, while VSC2 regulates the dc-bus voltage.The analysis considers the rectifier and inverter mode of operation for each VSC station.Further, the critical SCR (CSCR), at which small-signal instability is exhibited, is identified for each VSC station.

A. B2B HVDC SYSTEM EIGENVALUE ANALYSIS
Fig. 5 illustrates the impact of varying the SCR of Grid 1 from 10 to 1 on the B2B HVDC system dominant eigenvalues under both the rectifier and inverter operation of VSC1.Overall, as the SCR decreases, the stability margin of the system decreases, gradually leading the system toward instability.However, the specific eigenmodes propelling the system to instability and the CSCR value differ with the VSC operational mode.Under rectifier operation, as depicted in Fig. 5(a), the analysis reveals three prominent eigenmodes affected by the SCR variation λ 1 , λ 2 and λ 3 .Notably, Notably, λ 1 and λ 2 are high-frequency modes (HFMs) directly contributing to high-frequency oscillations, whereas λ 3 is a low-frequency mode (LFM).As the SCR varies, it is observed that λ 1 and λ 2 reach an instability threshold at an SCR value of 2.2 and 1.4, respectively.On the other hand, λ 3 display instability at a notably lower SCR of 1.15.The participation factor analysis, shown in Fig. 7, reveals that the ac grid states are the main contributors to the HFMs (λ 1 and λ 2 ), with VSC controllers not affecting these modes.The high-frequency oscillations are primarily due to the resonance of the LC filter, which is prominent under weak grid conditions.On the other hand, Fig. 6 shows that the LFM is attributed to the PLL and outer loop controllers' states.This observation aligns with existing literature, underscoring the interaction between the PLL and outer loop controllers as a primary driver for low-frequency instability of VSC under weak grid conditions.Transitioning into the inverter operation of VSC1, as depicted in Fig. 5(b), it can be noted that neither high-nor low-frequency instability manifests in this scenario with the variation of SCR.The LFM (λ 3 ), while stable, it moves closer to the imaginary axis as the SCR decreases, indicating reduced damping and stability margin.Fig. 5(b) shows that instability under inverter operation emerges due to the medium-frequency mode, λ 4 , at SCR = 1.The analysis in Fig. 7 indicates that λ 4 is mainly influenced by the ac grid, PLL, and the PCC voltage controller.An analogous evaluation under low-power injection of VSC1 is represented in Fig. 5(c).This analysis reveals the possibility of high-frequency instability in inverter operation at SCR = 1.2 caused by λ 1 .Fig. 6 shows the movement of the dominant eigenvalues as the SCR of Grid 2 decreases under both the rectifier and inverter operation of VSC2.The findings exhibit parallel behavior with that observed with VSC1, especially with regard to high-and low-frequency modes inducing instability under rectifier operation, as evident in Fig. 6(a).The HFMs, represented by λ 5 and λ 6 , display instability thresholds at SCR values of 2.2 and 1.4, respectively.This agrees with the observations made in Fig. 5(a), a consequence of both VSCs being interfaced with an ac system characterized by identical parameters.The participation factor analysis from Fig. 7 demonstrates that the ac grid states predominantly dictate the behavior of these HFMs.Yet, a distinction emerges in the domain of the LFM, denoted as λ 7 .While VSC1 displays instability at an SCR of 1.15, VSC2 becomes unstable at a slightly higher SCR of 1.25.This divergence suggests that a dc-bus voltage-controlled VSC is more susceptible to instability in weak grid scenarios than its power-controlled counterpart.The participation factor analysis in Fig. 7 reveals the dc-bus voltage, outer controller states, and the PLL states as the prime contributors to λ 7 .
Exploring the inverter operation, the eigenvalue trajectories align closely with the results presented in Fig. 6(b) for VSC1.No high-frequency instability is observed, but an LFM and MFM move into instability at an SCR of 1 and 1.05, respectively.Furthermore, under light-power injection, as portrayed in Fig. 6(c), the emergence of high-frequency instability echoes the results observed for VSC1, reiterating the profound influence of the inherent ac system parameters

TABLE 1. CSCR Values of b2b and P2P HVDC Systems
on both VSCs.A comparison between the CSCR for both VSC1 and VSC2 under the rectifier and inverter operation is provided in Table 1.
The eigenvalue analysis presented in Fig. 5(b) and Fig. 6(b) indicated that both VSC converter stations of the B2B HVDC system may exhibit medium-frequency instability at extremely weak grid conditions.To further explore this instability, the frequency response of the transfer function V sd1 /V * sd1 at SCR = 1 under the variation of VSC1 LC filter capacitance is illustrated in Fig. 8(a).Two resonance peaks are observed at 40.7 Hz (medium frequency) and 10.1 Hz (low frequency), confirming the eigenvalue analysis.The amplitude of the low-frequency resonance is marginally influenced by changes in the filter capacitance (C f ), whereas the medium-frequency resonance (MFR) is significantly affected.As the capacitance (C f ) decreases, the amplitude of the MFR initially increases, peaking at C f = 4.15 μ f , before decreasing again with further reductions in C f .The findings suggest that the VSC LC filter capacitance considerably impacts the medium-frequency instability, and it can stem from the resonance between the filter capacitance and weak grid inductance.
The participation factor analysis in Fig. 7 illustrated that the PLL phase angle (δ) is the main state influencing both the low and medium unstable frequency modes.Fig. 8(b) illustrates the influence of varying the PLL bandwidth on the frequency response of the transfer function V sd1 /V * sd1 .It can be observed that decreasing the PLL bandwidth leads to lower resonance amplitude of both the low and high frequencies.
The findings indicate that a larger PLL bandwidth not only adversely impacts low-frequency resonance, as demonstrated in the literature, but also increases the amplitude of the mediumfrequency resonance reported in this study.

B. P2P HVDC SYSTEM EIGENVALUE ANALYSIS
The eigenvalue value analysis conducted for the B2B system is repeated for a P2P system to evaluate and compare the stability and CSCR of both systems under weak grid conditions.The analysis for VSC1 (power-controlled VSC station) is excluded for space limitation, given its close resemblance to the B2B system analysis.Such similarity is anticipated since the participation factor analysis (PFA) suggests that VSC1's dominant modes in weak grid scenarios are unaffected by the dc-side states.Fig. 9 shows the impact of decreasing the SCR of Grid 2 on the system stability under both the rectifier and inverter operation of VSC2.In Fig. 9(a), under rectifier operation, HFMs (λ 9 and λ 10 ) venture into instability as SCR decreases.While the HFMs display instability at close SCR values, as in the case of the B2B system, the LFM becomes unstable at a notably large SCR value of 1.4, signifying that dc transmission line dynamics challenge the stability of a dc-bus voltage-controlled VSC.
Under inverter operation, as shown in Fig. 9(b), the HFMs remain stable as the SCR decreases at the rated power injection of VSC2.However, the LFM displays instability at an SCR value of 1.1, slightly higher than the B2B system's value of 1. Fig. 9(b) also highlights a distinct medium-frequency eigenmode, λ 13 , which becomes unstable at a notably high SCR value of 2.8.The PFA, depicted in Fig. 10, reveals that λ 13 is mainly affected by the dc-side states (I 12 , V dc1 , and V dc2 ) and the PCC voltage controller state.With the current I 12 being a predominant state affecting λ 13 , it suggests that the instability might stem from the power feedforward compensation loop of the dc-bus voltage controller.This hypothesis is tested by evaluating the P2P system's stability without the power feedforward compensation loop, as illustrated in Fig. 11.It can be noted that as the gain of the power feedforward loop is reduced, λ 13 , shifts toward the LHP and eventually stabilizes upon deactivation of power feedforward (k f f = 0).This demonstrates that the power feedforward loop is the main influencer of λ 13 instability.A comparison between the CSCR for both VSC1 and VSC2 under the rectifier and inverter operation is provided in Table 1.

IV. PROPOSED COMPENSATORS
The stability analysis presented in the preceding section revealed that a B2B/P2P system is vulnerable to instabilities stemming from HFMs and LFMs, henceforth referred to as high-frequency instability (HFI) and low-frequency instability (LFI).Meanwhile, a P2P system may also encounter instability due to MFMs, termed medium-frequency instability (MFI).These challenges can be addressed using either passive or active compensating strategies.Passive compensation involves integrating a passive component into the system, enhancing the overall stability margin.However, this approach leads to increased costs and additional power losses.As a result, active compensation techniques, also known as virtual damping compensators, are increasingly favored for their effectiveness.These techniques replicate the damping effect of passive elements by altering the control loops of the VSC.The subsequent sections introduce these compensators and delve into the specifics of their parameter design.
Fig. 12 shows a flowchart outlining the design methodology of the proposed active compensators.First, using eigenvalue analysis, the unstable eigenmodes are identified.Then, participation factor analysis is applied to identify the main influencing states on these unstable modes, as detailed in Section II.Following a thorough examination, internal model-based active compensators are advised to inject modified versions of these influencing states into certain control loops to mitigate instability.The design of each compensator involves determining two critical parameters.The cut-off frequency (ω c ), which is determined based on the unstable mode frequency.Additionally, the compensator gain (k c ), which is adjusted to stabilize the system and ensure an acceptable stability margin.

A. HFI COMPENSATOR
The participation factor analysis, depicted in Fig. 7, reveals that the ac grid states, especially the PCC voltage d-q components, are the main influencing states on the HFMs.Therefore, an HFI compensator is advised to inject a modified version of the PCC voltage d-q components into the inner current loop of the VSC, as depicted in Fig 13 .The compensator uses a high-pass filter to extract the frequency modes of the PCC voltage oscillations, which are then embedded in the stable closed loop system; hence, it is possible to mitigate these oscillations.The transfer function of the HIF compensator can be described as: In (17), k c is a stabilizing gain to improve the highfrequency damping.k c is adjusted not only to stabilize the system but also to ensure acceptable stability margin.ω c is  the cut-off frequency of the high-pass filter which is selected to be half the frequency of the unstable mode, to avoid the filter's transition band area and effectively mitigate the HFI.
The system state-space model is modified to incorporate the HFI compensator dynamics (17) by adding one more state.Fig. 14 shows the impact of varying the compensator stabilizing gain from 0 to 0.3 on the unstable HFMs under three settings of ω c .The proposed compensator can stabilize the system by relocating the unstable modes to LHP.As the gain k c increases, the HFMs are shifted further into the LHP, implying improved damping.Fig. 15(a) provides a comparison between the frequency response of the transfer function V sd /V * sd with and without the proposed compensator.It can be noted that the HFI compensator is effective in mitigating the two resonant peaks in the system.Using the compensator parameters in Table 2, the frequency response of the transfer function V sd /V * sd under varying operating points is provided in Fig. 15(b).The result shows the proposed compensator's effectiveness in mitigating the high-frequency resonance under both the rectifier and inverter operation.

B. LFI COMPENSATOR
The analysis presented in Fig. 7 reveals that the primary factor influencing the LFI is the interaction between the PLL and the VSC outer loop controllers.These adverse interactions are caused by the large PLL bandwidth.While reducing the PLL bandwidth can mitigate the LFI and enhance the overall system stability, it would also degrade the system's transient response and robustness.Therefore, an LFI compensator is proposed in this paper to provide active compensation into the outer control loops of the VSC based on the perturbed angular frequency of the PLL ( ω) as depicted in Fig. 13.The transfer function of the LFI compensator can be described as: In (18), k l is a stabilizing gain to improve the low-frequency oscillation damping.ω l is the cut-off frequency of the compensator low-pass filter.It is important to highlight that the input to the compensator is the perturbed angular frequency ( ω); hence, it only encompasses variation in the angular frequency, not the steady-state value.The low-pass filter ensures that only the targeted low-frequency oscillations are being injected into the VSC outer control loops.The stability analysis in Section III demonstrates that the LFMs exhibit angular frequency in the 40-60 rad/s range depending on the VSC operation (rectifier/inverter). Therefore, ω c is selected to be 100 rad/s to ensure only the LFMs are compensated.
Based on (18), one more state is added to the system statespace model to incorporate the impact of the LFI compensator.Fig. 16(a) shows the impact of varying the LFI compensator stabilizing gain on the dominant eigenmodes under different SCR values.It is evident that the LFI compensator effectively stabilizes the system and significantly enhances the damping of unstable modes.Based on the findings presented in Fig. 16(a), a stabilizing gain of 1300 is sufficient to ensure system stability across various SCR values.Importantly, it should be noted that the damping signal converges to zero under steady-state conditions, thereby not affecting the steady-state operation of the VSC.Fig. 16(b) shows the impact of increasing the gain k l on the frequency response of the transfer function V sd /V * sd .As the gain increases, the resonance peak is significantly reduced, demonstrating the effectiveness of the LFI compensator.Fig. 16(c) further demonstrates the effectiveness and robustness of the proposed compensator under the variation of the active power operating point.It can be noted that the low-frequency resonance is effectively mitigated under both the rectifier and inverter operation.

C. MFI COMPENSATOR
It is demonstrated that dc-bus voltage-controlled VSC in a P2P HVDC system displays MFI primarily caused by the power feedforward compensation.The participation factor analysis in Fig. 10 showed that the current I 12 is the main influencing state on the unstable medium-frequency modes.Therefore, an active compensator is advised to inject a damping signal into the d-axis current control loop based on the current I 12 , as depicted in Fig. 13.The input of the compensator is the current I 12 and its transfer function can be described as: In (19), k d is a stabilizing gain to improve the mediumfrequency oscillation damping.ω d is the cut-off frequency of the compensator high-pass filter.ω d is determined to ensure that the targeted oscillations are only compensated.Since the medium-frequency unstable modes have a frequency of 250 rad/sec, ω d can be designed at half or lower than half of the medium-frequency modes to avoid filter transition's band area and effectively mitigate the MFI.
Based on (19), one more state is added to the state-space model of the system to incorporate the MFI compensator dynamics.The effectiveness of the compensator in mitigating the MFI is demonstrated in Fig. 17(a).Fig. 17(a) shows the unstable modes' movement as k d increases from 0 to 5 under different ω d values.It is evident the compensator is capable of shifting the unstable modes to the RHP under the three settings of ω d with a stabilizer gain higher than 3.8.The highest damping improvement can be achieved at lower ω d .The frequency response of V sd /V * sd , depicted in Fig. 17(b), further demonstrates the compensator's efficacy in eliminating medium-frequency resonance peaks.The effectiveness of the proposed compensator under the variation of the operating points is demonstrated in Fig. 17(c).It can be noted that the designed compensator successfully mitigates the mediumfrequency resonance.

V. VALIDATION RESULTS
Time-domain simulation and HIL real-time studies are conducted to verify the validity of the stability analysis and demonstrate the effectiveness of the proposed active compensators.Detailed nonlinear MATLAB/Simulink models of B2B and P2P HVDC systems are developed, with system and control parameters listed in the Appendix.

A. PERFORMANCE OF HFI COMPENSATOR
This study examines the efficacy and effectiveness of the proposed HFI compensator.In addition to system stabilization, the compensator should display robustness to variations in the operating point.The B2B HVDC system, depicted in Fig. 1, is simulated, wherein the SCR of Grid 1 is set to 1.3.The system's response to VSC1's power injection changes is captured in Fig. 18.Initially, the system maintains a steady state with VSC1 channeling −100 MW (rectifier operation) into the dc side.At t = 0.5 s, VSC1's power injection increased to −300 MW, leading to oscillatory instability in the system at 165 Hz, which agrees with the eigenvalue analysis in Fig. 5(a).By activating the proposed HFI compensator at t = 1 s, these in a steady state with VSC1 injecting 450 MW into the dc side.At t = 3.5 s, a line with the same impedance as Z g1 is added in parallel, altering the SCR from 1 to 2. Notably, both strategies maintain system stability during the significant change in SCR.Yet, as depicted in Fig. 21(a), the proposed method demonstrates better performance in terms of power deviation and settling time, achieving a settling time of 50 ms, in contrast to more than 200 ms observed with the method in [36].The slow response of the method in [36], is largely due to the negative feedback loop integrated with PLL controllers aimed at ensuring stability in weak grid, which inherently slows down the PLL.

E. ROBUSTNESS AGAINST GRID VOLTAGE ABNORMALITIES
Typically, VSCs must ride through voltage disturbances, including voltage sags and swells.As per European regulations, an HVDC converter station should remain connected and function at its power within a grid voltage span of 0.9-1.1 pu [43].In this study, a voltage sag of 10% is introduced at t = 3.5 s and the system response of the proposed method and one in [36] are compared in Fig. 22.Both approaches exhibit resilience against grid voltage disturbance.Yet, again, the proposed compensators demonstrate better transient performance with lower deviation and settling time, particularly when the grid voltage reverts to its standard value at t = 4 s.The dc-bus voltages remain largely stable during the sag, attesting to the efficacy of the proposed compensators.Fig. 23 shows the system response when subjected to a 10% grid voltage swell at t = 3.5 s.The results demonstrate the capability of the VSC station to continue stable operation during the voltage swell and also show the superior performance of the proposed compensators compared to the method in [36].

F. REAL-TIME HIL VALIDATION
The feasibility of the proposed compensators in real-time is validated using a real-time HIL setup based on the OPAL-RT OP5600 platform.The platform uses a Virtex-6 FPGA board  As the SCR changes from 1.9 to 1.7 at t = 1 s, the system is subjected to unstable oscillations at 35 Hz.With the activation of the MFI compensator, the oscillations are effectively damped, and the system stability is restored.At t = 2 s, the SCR is further decreased to 1.5.As can be seen, the system is maintained stable, except for a transient overshoot at the instant of SCR change.In the second test depicted in Fig. 25, the three compensators are evaluated under significant change in SCR.It is evident that as the SCR suddenly changes from 1 to 2, the system

FIGURE 1 .
FIGURE 1.(a) Schematic diagram of B2B HVDC system, (b) Representation of ac side of VSC.

FIGURE 2 .
FIGURE 2. Control system of a VSC station.

FIGURE 3 .
FIGURE 3. (a) Control structure of PLL.(b) Grid and converter d-q frames.

FIGURE 4 .
FIGURE 4. Small-signal model validation under step change of VSC1 power injection.

FIGURE 7 .
FIGURE 7. Participation factor analysis of dominant eigenmodes for B2B system under weak grid.

FIGURE 8 .
FIGURE 8. Frequency response of transfer function V sd1 /V * sd1 (a) under the variation of C f .(b) under the variation of PLL bandwidth.

FIGURE 12 .
FIGURE 12. Flowchart of the proposed compensators design methodology.

FIGURE 13 .
FIGURE 13.Schematic diagram of the proposed compensators.

FIGURE 14 .
FIGURE 14. Impact of HFI compensator on high-frequency eigenmodes as k c increases.

FIGURE 15 .
FIGURE 15.Impact of HFI compensator on high-frequency eigenmodes (a) Comparison with the uncompensated system.(b) Under varying operating points.

FIGURE 16 .
FIGURE 16.Impact of LFI compensator (a) LFM as k l increases.(b) frequency response of transfer function V sd /V * sd .(c) frequency response of V sd /V * sd under varying operating points.

FIGURE 17 .
FIGURE 17. Impact of MFI compensator (a) MFM as k d increases.(b) frequency response of transfer function V sd /V * sd .(c) frequency response of V sd /V * sd under varying operating points.