Steady-State and Transient Modeling of the Series Resonant Balancing Converter

The active voltage balancing device is a necessary part of some modern power electronics applications. Among numerous possible hardware solutions, the Series Resonant Balancing Converter shows advantages in terms of efficiency and low complexity, due to the soft-switching capability and stable operation in the open-loop. This paper models the steady-state operation of Series Resonant Balancing Converter, including the influence of parasitic components, such as parasitic resistances and semiconductors' forward voltages. Additionally, the dynamic modeling, describing the transient behaviour of the Series Resonant Balancing Converter, is presented, as well as the average model of the Series Resonant Balancing Converter with corresponding transfer functions. Frequency analysis and the low-pass nature of the Series Resonant Balancing Converter is presented and a case in which a large DC bus capacitor is connected externally is discussed. Lastly, the design example of a 7.6 kW, 700 V DC bus voltage, Series Resonant Balancing Converter is presented, and modeled steady-state and transient operations are experimentally verified.


I. INTRODUCTION
In order to improve the integration of renewable energy sources, and to better accommodate inherently DC loads or inverter-fed AC loads, the DC distribution systems are becoming increasingly popular topic in today's research [1], [2], [3], [4].While the DC grid can be unipolar or bipolar, the bipolar one is more resilient and provides more flexibility in terms of voltage levels for different loads [1], [5].However, since the loads are usually unbalanced, the bipolar DC grids require the Active Voltage Balancing Device (AVBD) to balance the bus voltages.Additionally, balancing of either split DC bus capacitor, supercapacitor banks or battery cells is increasingly more important in modern applications [6], [7], [8].Firstly, it can prolong lifetime of the supercapacitor or battery systems, secondly, some topologies, such as non-isolated Input-Series-Output-Series (ISOS) Partial Power Rated Converter (PPRC) are not stable without externally balanced DC bus [9], [10], [11].In addition, the authors in [8] and [12] discuss a possibility of active voltage balancing of more than two capacitors in series.
A wide spectrum of converters are used as AVBD.Buck/boost based topologies utilized as AVBD are presented in [6], [13], [14], [15].The dual-active bridge converter, used as an AVBD is shown in [16].The Series Resonant Balancing Converter (SRBC) can also be utilized as AVBD, and it can be realized with an AC inductor, as presented in [8] and [10], or with a DC inductor, as presented in the [11].
The optimal topology for AVBD is dependent on the system requirements, such as galvanic isolation, safety, etc.With soft-switching capabilities and simplicity of the control, the resonant converters are favorable to be utilized in applications where only balancing of the voltages is required, and not the regulation of the full DC bus voltage.These topologies have evolved from previously utilized switched capacitor balancing converters [6], in which, a small inductance is added so that the soft-switching operation is achieved [7], [17].Therefore, the scope of this paper is the analysis of the behaviour of the SRBC in steady-state, as well as during transients.
The SRBC, operating in Discontinuous Conduction Mode (DCM) achieves Zero Current Switching (ZCS), hence, it can operate with negligible switching losses (depending on the switch output capacitance), similarly to the converters presented in [18], [19], [20].While some authors proposed controlled SRBC [8], the simplicity of the SRBC lies in the fact that the open-loop gain of SRBC in DCM is constant and equal to 1 [21].Among various applications, the SRBC can be utilized within PPRC, to achieve highly efficient DC to DC conversion in PV or battery interface applications [9], [11].It can also be utilized in a single-phase active half-bridge rectifiers to eliminate the fundamental harmonic of the DC bus current, resulting in a immensely reduced size of the DC bus capacitor [22].
The SRBC topology is known and can be utilized in different applications, such as Uninterruptible Power Supplies (UPS) systems and data centers [8], [10].However, the voltage unbalance, caused by the parasitic resistances in the path of the resonant current have not yet been discussed in the literature.Hence, besides ideal, this paper also offers modeling of non-ideal steady-state operation of the SRBC.Additionally, while the general modeling of the dynamic behavior of the half-cycle DCM series resonant converters can be found in [23], [24], [25], the modeling of the dynamic behaviour in the specific case of the SRBC is not described in literature, and hence, it is presented in this paper.Namely, due to the interconnection between SRBC and other power converters in the system, e.g.ISOS PPRC, the understanding and properly modeling the dynamic behaviour of the SRBC is crucial.Moreover, the average model of the SRBC is presented, from which, the transfer functions describing the responses of the SRBC on disturbance in the DC bus voltages and on disturbance in the current injected in the midpoint of the DC bus are derived and discussed.Lastly, the transient behaviour of the SRBC in the specific case when a large DC bus capacitor is connected externally is discussed.Summarizing the main contributions and novelties of this manuscript are: 1) Modeling of the steady-state operation of the SRBC in case the parasitic components, such as parasitic resistances, semiconductors' forward voltages and the dead-time are not neglected, 2) Modeling of the dynamic behavior of the SRBC, 3) Derivation of the average model of the SRBC and the corresponding transfer functions.This paper is organized as follows: in Section II, the ideal and non-ideal steady-state operation of the SRBC is presented.The dynamic and average models of the SRBC are derived in Section III, and the transient behaviour of the SRBC, in a specific case when a large DC bus is connected externally, is discussed.In Section IV the design example is shown, and proposed steady-state and dynamic models are experimentally verified.

II. SERIES RESONANT BALANCING CONVERTER
The series resonant converter, shown in Fig. 1, operating in DCM, ideally exhibits a constant voltage gain of 1 [21].Therefore, the voltage balancing across the DC bus capacitors is achieved without a closed-loop control, provided that DCM is maintained.An additional advantage of DCM is operation with ZCS, which allows a highly efficient operation of the SRBC by minimizing the switching losses.Namely, in case the SRBC is operated at the switching frequency lower than the resonant frequency, i.e. f s < f r , the resonant current falls to zero before the next switching action, and hence, ensuring the switching transients with zero current.The analysis of the steady-state operation of the SRBC can be differentiated into ideal and non-ideal cases, depending on the omission or inclusion of the parasitic components, such as forward voltages of semiconductors and parasitic series resistances in the resonant circuit.

A. STEADY-STATE OPERATION: IDEAL CASE
The DC component of the current injected in the midpoint of the DC bus, I b , induces an unbalance between the voltages across the DC bus capacitors.In order to compensate this current, the series resonant converter can be utilized as an AVBD [8], [10].The switching states of the SRBC with the waveforms of the resonant current, i r , the current extracted from the midpoint of the DC bus, i 0 , and the voltage across the resonant capacitor, u C r , are shown in Fig. 2.
Having that the gain of the SRBC operating in DCM is 1, the voltages across upper and lower DC bus capacitors are forced to be equal, i.e.U 1 = U 2 .Also, assuming that the switching frequency of the SRBC is close to the resonant frequency, the current extracted from the midpoint of the DC bus by the SRBC is rectified resonant current.Hence, its DC value can be expressed as where I 0 m is the maximum value of the resonant current.Additionally, in steady-state, the DC values of the currents flowing through DC bus capacitors has to be zero, and consequently, the DC component of the current extracted from the midpoint of the DC bus, I 0 , exactly matches the DC value of the unbalance current, I b , i.e.I 0 = I b .Therefore, from (1), the resonant current can be expressed as where ω r is the resonant frequency and can be expressed as An important characteristic of the SRBC is the presence of a DC voltage bias across the resonant capacitor, U Cr DC .Namely, the voltages U 1 and U 2 are symmetrically applied across resonant tank, and having that the DC value of the voltage across inductor is zero, the DC voltage bias across resonant capacitor can be expressed as U Cr DC = (U 1 + U 2 )/2.This bias influences the design of a resonant capacitor, especially in a case of the ceramic capacitors, due to their strong dependence on the voltage applied across them.

B. STEADY-STATE OPERATION: NON-IDEAL CASE
In the previous section, the ideal steady-state operation of the SRBC is presented.However, the parasitic components, such as parasitic resistances and semiconductors' forward voltages, influence the operation of the SRBC.Independently of the switching state, the total resistance in the path of the resonant current is a sum of switch on-resistance r s,on , diode on-resistance r d,on , resonant inductor parasitic resistance r L and resonant capacitor equivalent series resistance ESR, i.e.
By assuming that voltages across DC bus capacitors are not equal (i.e.U 1 = U 2 ), the voltage applied across resonant tank is alternating between voltages U 1 and U 2 , and the equivalent circuit diagrams can be presented as in Fig. 3, where the U F s and U F d represent the switch and diode forward voltages, respectively.By solving the circuits shown in the Fig. 3(a) and (b), and by defining the quality factor Q as the resonant capacitor voltage u C r and resonant current i r can be expressed as Furthermore, from ( 5) and ( 6), and recognizing that the initial conditions of the resonant current are that it is equal to zero at the beginning and at the end of each half resonant period, i.e. i r (t = kT r /2) = 0 , k = 0, 1, 2, . .., the relations between unknown coefficients A 11 and A 21 , and A 12 and A 22 can be expressed as By defining the resonant capacitor voltage at the beginning of the first half of the resonant period, presented in Fig. 3(a) as U Cr 01 , and the resonant capacitor voltage at the beginning of the second half of the resonant period, presented in Fig. 3(b) as U Cr 02 , those voltages can be expressed from ( 5) and ( 6) as On the other hand, the average rectified resonant current, I 0 , extracted from the DC bus midpoint has to match the DC current injected in the DC bus midpoint, I b .Therefore, by calculating the average extracted current from DC bus midpoint by the SRBC, I 0 , and equalizing it with the DC current injected in the DC bus midpoint, I b , the following equation is obtained Having that the total voltage across upper and lower capacitors is the DC bus voltage, i.e.U 1 + U 2 = U DC , and with the ( 8) and (9), the system of six equations can be solved, and the voltages U 1 and U 2 can be obtained as Moreover, from (10), the difference between the voltages across upper and lower DC bus capacitors U 12 can be expressed as Considering the SRBC example given in Section IV, where the resonant circuit consists of L r = 1 μH, C r = 7.7 μF, and the forward voltages of switch and diode are U F s = U F d = 0.7 V, the relation ( 11) can be presented graphically, as shown in Fig. 4(a).Even though it shows exponential relation as described in (11), the more realistic case, when equivalent parasitic resistance is relatively small, is shown in Fig. 4(b).In this case, the voltage difference between DC bus capacitance voltages shows linear dependency on the equivalent parasitic resistance.Therefore, by considering that equivalent parasitic resistance is relatively small (i.e.R ep < 100 m ), and consequently, that the quality factor Q is high, the (11) can be simplified as Furthermore, similarly as given in [25], having that the switching and resonant frequencies are not equal, i.e. f s = f r , the equations describing the voltages U 1 and U 2 , as well as the voltage difference between DC bus capacitors, ( 10), (11), and (12), can be adjusted to account for this difference, i.e.
As it can be seen in ( 13c) and (13d), the expression describing the voltage difference between the DC bus capacitors is composed of two parts.The first is related to the semiconductors' forward voltages, U F s and U F d , and is constant, while the second part is related to the parasitic resistance, R ep , and is proportional to the current injected in the midpoint of the DC bus, I b .Moreover, considering the lower DC bus capacitor as the input of the SRBC, and the upper DC bus capacitor as the output of the SRBC, the voltage gain, G, of the SRBC can be calculated from (13a) and (13b) as In the Fig. 5 is shown the comparison between the calculated voltage difference, as shown in (11), and measured difference for different unbalance currents, I b .The experimental measurements are taken on the prototype described in Section IV, with the test circuit shown in Fig. 16.As it can be seen from the Fig. 5, the absolute error of the model increases with the injected current, I b .Namely, the model described in (11) and ( 12) is sensitive to the estimation of the forward voltage and series parasitic resistance.In low load conditions, i.e. for small I b , the error in estimating the voltage difference U 12 is mainly caused by the error in estimation of the switch and diode forward voltages U F s and U F d .On the other hand, for higher currents I b , the error in estimating the voltage difference U 12 is predominantly caused by the error in estimation of the series parasitic resistance R ep .Summarizing, the discrepancy between the voltages across DC bus capacitors is caused by the presence of the parasitic series resistances and semiconductors' forward voltages.The forward voltages impose constant offset between these two voltages, while additional discrepancy is dependent on the injected DC current (I b ) and the parasitic series resistances in the path of the resonant current.Additionally, from (4), (11), and (12), it is easily identifiable that in case U F s → 0, U F d → 0 and R ep → 0, the difference between voltages across DC bus capacitors diminishes.
Lastly, the DC bias voltage across resonant capacitor U Cr DC is the same as in case of ideal SRBC, which can be calculated from (10) as Therefore, in case the ceramic capacitors are used to design the resonant capacitor, the change in capacitance value with respect to the applied voltage should be taken into account.Additionally, from (2), the voltage ripple across resonant capacitor, U Cr pp , can be

calculated as
Therefore, the resonant capacitor should be designed according to its maximum voltage, U Cr max , which can be calculated as

III. DYNAMIC AND AVERAGE MODEL OF THE SRBC A. DYNAMIC MODEL OF THE SRBC
The dynamic model, describing the transient behaviour of the SRBC, caused by the disturbance in the unbalance current I b is of interest to ensure the stable operation.Therefore, similarly to the analysis shown in [24] regarding the series resonant converter, the equivalent circuit of the SRBC during transients can be derived.
Considering that the switching frequency is close to the resonant frequency (i.e T s ≈ T r ), the resonant circuit can be presented as shown in Fig. 6(a).To analyse the dynamic behaviour it is considered that the square waveform voltage, u r , is applied across the resonant tank, as shown in Fig. 7. Having that the DC bias voltage across the resonant capac- , and that the voltages U 1 and U 2 , described in (10), are alternately applied across the resonant tank, the voltage E represents half of the voltage difference between DC bus capacitors, i.e.
Together with the voltage u r , the waveform of the resonant current, i r , and of the voltage across the resonant capacitor, u Cr , are shown in Fig. 7.
By solving the circuit shown in Fig. 6(a), the absolute value of the resonant current in the first half of the k th period, i r1 , (i.e.t ∈ (kT r , kT r + T r 2 )) can be expressed as where |U Cr 01 (k)| is the voltage across resonant capacitor at the beginning of the k th period, and Z is the characteristic impedance of the resonant tank (i.e.Z = L r C r ).Additionally, the absolute value of the average resonant current over the half resonant period, I r , can be calculated as By combining ( 17) and ( 18), the absolute value of the average resonant current over first half of k th resonant period can be expressed as Additionally, the absolute value of the voltage across the resonant capacitor at the end of the first half of the k th period (i.e.t = kT r + T r 2 ), |U Cr 02 (k)|, can be calculated as (20) and by combining ( 17) and ( 20), it can be expressed as Having that the resonant capacitor voltage at the beginning of the second half of the k th period is the same as the resonant capacitor voltage at the end of the first half of the k th period, and from (19), the absolute values of the average resonant currents in first and second half of k th resonant period, I r1 (k) and I r2 (k), respectively, can be expressed as The waveforms of the applied voltage u r , resonant current i r , average rectified currents I r1 and I r2 , and voltage across resonant capacitor u Cr are shown in Fig. 7.
From (22), the first derivative of the absolute value of the resonant current, representing the rate of change of average rectified resonant current, can be expressed as Hence, by substituting ( 22) into (23b), it can be rewritten as (24) Similarly as presented in [25], the fact that switching and resonant frequencies are not equal, i.e. f s = f r , can be accounted for by adjusting the equivalent resistance with f r f s , and the equivalent resistance with ( f r f s ) 2 , i.e.
As analytically derived in ( 24) and ( 25), and considering the semiconductors' forward voltage, the resonant circuit can be presented by equivalent series RL circuit, with equivalent resistance R e and equivalent inductance L e as shown in Fig. 6(b), and the voltage applied across the equivalent resonant circuit is the voltage difference between upper and lower DC bus capacitors.
As it is shown in (25), all three passive components, i.e.R ep , L r and C r , influence the modeled equivalent resistance, R e , and inductance, L e .Considering that the SRBC is designed to operate at the specific switching frequency, which is close to the resonant frequency, i.e. f s ≈ f r , the relation between resonant inductance and capacitance, as well as the characteristic impedance Z can be expressed as Therefore, both equivalent resistance R e and equivalent inductance L e are directly proportional to the resonant inductance L r , and hence, the resonant inductance does not influence the dynamic behavior of the SRBC directly.On the other hand, the quality factor Q, expressed in (4), depends on the choice of resonant inductor/capacitor and on the parasitic resistance R ep .From (4), the increase of the quality factor asymptotically reduces the equivalent resistance to zero, and the equivalent inductance to π 2 4 L r .Therefore, considering that the time conof the equivalent RL circuit is τ = L e R e , the increase of the quality factor Q, also increases the time constant of the equivalent circuit, and consequently, it increases the response time of the SRBC.
Additionally, in case that R ep → 0, hence Q → ∞, the equivalent circuit becomes an ideal inductor, with the inductance L e = ( π 2 ) 2 L r , which corresponds to the results presented in [24] and [25].Furthermore, by assuming that the quality factor is high enough, i.e. that π Q is close to zero, the exponential functions in the equivalent resistance R e can be linearized around zero, i.e. e x = 1 + x.In this case the equivalent resistance can be expressed as R e = π 2 8 R ep , which corresponds to the result obtained in [25].
Lastly, considering that the source terminals of all four switches of the SRBC are on different potentials, their drivers have to be isolated.Depending on the power supply of the drivers, this can lead to the injection of common mode currents.However, since those currents are in MHz range, they are not influencing the dynamic behavior of the SRBC in the frequency bandwidth of interest for balancing.

B. AVERAGE MODEL OF THE SRBC
In the previous subsections, the steady-state operation and the transient behaviour of the SRBC are analysed.Based on these results, the average model of the SRBC is presented in Fig. 8.The voltages U 1 and U 2 are described in (10), while the resonant tank equivalent resistance and inductance are described in (24).Having that the SRBC is operating in open loop, from the average model shown in Fig. 8, the transfer function, H u (s), considering the response of the resonant current on the disturbance in voltage difference between upper and lower DC bus capacitor can be expressed as The above transfer function has one pole, real and negative, i.e. s = − R e L e , and hence, the current response will have exponential behavior of the form where A is a constant, and τ u is the time constant, which can be calculated as Additionally, the transfer function, H i (s), considering the response of the resonant current on the disturbance in current injected in the midpoint of the DC bus can be expressed as (29) and considering the following form of the second order transfer functions the natural frequency ω n , and damping factor ζ can be expressed from ( 29) and (30) as The poles of the transfer function given in (29) can be expressed as Hence, in case ζ ≥ 1, the poles are real and negative, the system is so-called overdamped and the current response has exponential behaviour, i.e.
where A 1 and A 2 are constants, and τ i 1 and τ i 2 are time constants, and can be expressed as In the case ζ < 1, the transfer function given in (29) has complex conjugate poles, and the current response will have oscillatory behaviour, which can be expressed as where A 1 and A 2 are constants, and τ i 3 is the time constant, which can be calculated as Furthermore, considering the SRBC example described in the Section IV, the Bode diagram of the transfer function H i (s) expressed in (29), together with the results obtained from the simulations in PLECS, are given in Fig. 10.As it can be seen from ( 29) and Fig. 10, the SRBC is a second order system, which has unity gain on low frequencies and high attenuation of high frequencies.Namely, any low-frequency component of the injected midpoint current I b is compensated by the SRBC with the current extracted from the midpoint I 0 , while the SRBC practically does not react to any high-frequency component of the current I b .Additionally, the cut-off frequency, f c , can be calculated from (29) as which for the example described in Section IV is f c ≈ 5965 Hz.Hence, the SRBC can be used in cases in which the DC [9], [11] or low-frequency [22] current is injected/extracted from the midpoint of the DC bus.Additionally, the influence of different components on the transient behavior of the SRBC is presented in Fig. 11.Considering that the resonant frequency is constant, for different resonant inductances, the resonant capacitances are changed accordingly, i.e. f r = . As it can be seen, the increase in DC bus capacitance reduces the bandwidth of the SRBC, yielding higher attenuation of the high-frequency components, while reducing the frequency span of currents that can be compensated by the SRBC.On the other hand, the change in resonant inductance does not provide significant changes in the transient response.
Hence, the resonant tank should be designed with respect to f r , in order to obtain required closed-loop dynamics, and to maximize efficiency, power density or other application dependent requirement.
Furthermore, the equivalent circuit in Fig. 8 can be used to investigate the response of the voltage difference on the injected current, i b .Any unbalance between currents i b and i 0 , causes the voltage difference between upper and lower DC bus capacitor.Namely, part of their difference is charging the lower DC bus capacitor, while the other part is discharging the upper DC bus capacitor.Consequently, the voltage difference between DC bus capacitors can be expressed as A block diagram that highlights the closed-loop structure of the voltage balancing system is shown in Fig. 9.
As it can be seen in Fig. 9, the SRBC inherently is a closedloop system.Additionally, the transfer function describing the  disturbance rejection, H d (s), can be expressed from ( 27) and (29) as The Bode diagram of this transfer function is given in Fig. 12, together with the simulation results.As it can be seen from this figure, the gain of the SRBC at zero frequency is around −16 dB, and from (38) it can be calculated as 20 log (2R e ).

C. TRANSIENT RESPONSE IN A CASE OF A LARGE EXTERNAL DC BUS CAPACITOR
In a case a large DC bus capacitance, C DC e >> C DC , is connected externally across positive and negative bus of the SRBC, as shown in Fig. 13(a), the transient behaviour of the SRBC can be modeled by adding the equivalent capacitance, C e , in parallel with the equivalent RL circuit, as shown in Fig. 13(b).
Considering the transient behavior, the large external DC bus capacitor is practically a short-circuit, and therefore, the transient behavior of the SRBC is decoupled from the rest of the circuit.In this case, the upper and lower DC bus capacitors of the SRBC are effectively connected in parallel, i.e. and in a case the system is overdamped (i.e.capacitances C DC are large enough), the equivalent circuit shown in Fig. 6(b) can be solved, and the equivalent current, i e , can be expressed as where coefficients λ 1 and λ 2 are and coefficients A 1 and A 2 are Therefore, from (41) and (42), the dominant time constant, τ e , of the current response can be expressed as The dominant time constant can also be derived from the transfer function H i (s), described in (29).Since the system is overdamped, i.e. ζ > 1, the transfer function has two real and negative Therefore, the dominant time constant can also be derived from (31) and (34).
Summarizing, the SRBC during transients can be modeled as a passive circuit, shown in 6(b), consisting of the equivalent inductor, L e , and equivalent series resistance R , both expressed in (24).The average model of the SRBC is presented in Fig. 8, and the transfer functions describing the resonant current response on the disturbance in voltage difof DC bus capacitors, U 12 , and on the disturbance in current injected in midpoint of the DC bus, I b , are presented in ( 27) and (29), respectively.Furthermore, in case of a large external DC bus capacitor, the equivalent circuit during transient is presented in Fig. 13(b), and the resonant current response on the disturbance in current injected in the midpoint of the DC bus, i b , has an exponential behaviour, as expressed in (41), with the dominant time-constant τ e , expressed in (44).

A. PROTOTYPE
The steady-state operation and the transient behaviour of the SRBC are verified on the prototype shown in Fig. 14, and the prototype specifications are presented in Table 1.The laboratory test setup is shown in Fig. 15.As it is designated in the Figs.14 and 15, the components of the SRBC as well as used for testing are given in the Table 2.The of the resonant inductor is RM7 from TDK (part number: B65819J0000R087), and the resonant inductor winding is made Litz wire (135 0.071 with turns and parallel windings.The resonant capacitor consists of 48 ceramic capacitors in parallel.The RT Box is used as a PWM generator, and the DC voltage source, designated with number 8 in Fig. 15, is used to manually adjust the switching frequency of the generated PWM.

B. STEADY-STATE OPERATION
To test the SRBC in steady-state operation, the circuit depicted in Fig. 16 is used.In this configuration the SRBC operates as a voltage doubler, i.e.U out = 2U S .Also, the sum of the source and load currents, i S and i L , make the unbalance current, i b , injected in the midpoint of the DC bus.Therefore, this configuration is preferable for demonstration than the one where the load is connected at the output, due to the fact that the same unbalance currents can be achieved with the two times lower power of the source.Moreover, on Fig. 16, the U S is the source voltage (U S = 350 V ), and R L is the load resistance (R L ≈ 31 ).The processed power by the SRBC in this test is 7.6 kW, and the obtained efficiency 98.82%, measured with KEYSIGHT IntegraVision Power Analyzer PA2203 A.
The measured steady-state waveforms are shown in Fig. 17, where the cyan and blue waveforms represent the voltages across full and lower DC bus capacitors, U DC and U 2 , respectively.The magenta waveform represents the resonant current i r .The SRBC is operated in DCM and therefore, short periods when the resonant current is equal to zero can be observed.The voltage difference between DC bus capacitors in steadystate, for different unbalance currents, I b , is shown in Fig. 5.

C. DYNAMIC RESPONSE
The transient behaviour of the SRBC is verified experimentally by step-change of the load resistance, as shown in Fig. 18.The same laboratory setup is reconfigured as shown in Fig. 15, where the mechanical switch is used to include additional load resistance, in order to force a transient, and the obtained waveforms are shown in the Fig. 19.Since the load current has a step change, the current injected in the midpoint of the DC bus has step change as well.Therefore, as it can be seen from the Fig. 19, the maximum, and hence the average  Finally, comparison between measured response of the voltage difference between upper and lower DC bus capacitors, U 12 , and modeled response, on a step change in current injected in midpoint of the DC bus, i b , is presented in Fig. 21.Since this voltage difference is relatively small compared to the DC value of these voltages, the transient response is measured with AC coupled voltage probes, and therefore, before the step change of a current injected in the midpoint of the DC bus, i.e. for t < 0, this difference is zero, and only the change in this difference is measured and presented.
As verified in this section, the influence of the parasitic components of the resonant circuit on the deviation from the gain 1 of the SRBC operating in steady-state can be modeled as presented in (11), or simplified as in (12).Additionally, the transient behaviour of the SRBC in case when a large DC bus is connected externally can be modeled as an RLC circuit, shown in Fig. 6(b).

V. CONCLUSION
In this paper, the Series Resonant Balancing Converter (SRBC) is analyzed.The steady-state operation and transient behaviour are modeled and experimentally verified on a 7.6 kW, 700 V prototype.
The SRBC is suitable for applications in which active voltage balancing is required, providing highly efficient operation and low complexity of implementation.By operating the SRBC in DCM, ZCS is ensured, and therefore, a high efficiency operation can be achieved.Additionally, the gain of the SRBC in DCM is constant and equal to 1, making it able to balance DC bus voltages without regulation, i.e. by operating in open-loop.The deviation from gain 1 is caused by forward voltages of the semiconductor devices and by parasitic series resistance in the path of the resonant current, which is described, modeled and experimentally verified.The transient behaviour of the SRBC is modeled, and the equivalent circuit of SRBC during transients is derived and experimentally verified.Furthermore, the average model of the SRBC is derived, together with transfer functions describing the SRBC responses on disturbance in DC bus voltages and on disturbance in current injected in midpoint of the DC bus.

FIGURE 1 .
FIGURE 1. Series Resonant Balancing Converter topology connected across split DC bus capacitors.

FIGURE 2 .
FIGURE 2. Four switching states of the Series Resonant BalancingConverter operating in DCM, and the waveforms of the currents i r and i 0 .

FIGURE 3 .
FIGURE 3. Equivalent resonant circuit including the non-ideal components during the interval: (a) i, and (b) iii, as shown in Fig. 2.

FIGURE 5 .
FIGURE 5. Measured versus calculated (11) voltage difference between upper and lower DC bus capacitors for different currents injected into the midpoint of the DC bus.

FIGURE 6 .
FIGURE 6.(a) Equivalent circuit diagram of the resonant circuit, (b) Equivalent circuit diagram of the SRBC during transients.

FIGURE 7 .
FIGURE 7. Waveforms of the voltage applied across resonant circuit, u r , resonant current, i r , and voltage across the resonant capacitance, u Cr .

FIGURE 8 .
FIGURE 8. Average model of the Series Resonant Balancing Converter.

FIGURE 11 .
FIGURE 11.Magnitude Bode diagrams for different values of DC bus capacitance and for different values of the resonant inductance.

FIGURE 12 .
FIGURE 12. Bode diagram of the transfer function describing the disturbance rejection, H d (s).

FIGURE 13 .
FIGURE 13.(a) SRBC externally interfaced with a large DC bus capacitor, C DCe , (b) Equivalent circuit diagram of the SRBC during transients, including a large DC bus capacitors, C DCe .
C e = C DC ||C DC = 2C DC (39)By applying the step change of the input current i b , i.e.

FIGURE 17 .FIGURE 18 .
FIGURE 17. Waveforms of the resonant current, i r , lower DC bus voltage, U 2 , and the total DC bus voltage U DC , during the steady-state operation.

FIGURE 19 .
FIGURE 19.Waveforms of the resonant current i r , upper DC bus voltage U 1 , full DC bus voltage U DC , and the current injected in the midpoint of the DC bus i b , during transient.

FIGURE 20 .
FIGURE 20.Comparison between modeled maximum value of the resonant current, i rme , and experimentally measured resonant current i r , during transient.

FIGURE 21 .
FIGURE 21.Comparison between measured and modeled transient response of the voltage difference between upper and lower DC bus capacitors, U 12 , on the step change of the current injected in the midpoint of the DC bus, i b .
r e − ωr t