EMI Mitigation for SiC MOSFET Power Modules Using Integrated Common-Mode Screen

Electromagnetic interference (EMI) remains a critical roadblock to fully benefitting from the various advantages provided by wide-bandgap devices. Of particular concern is the common-mode (CM) emissions generated during the device operation. This work aims to inform EMI mitigation strategies that can be implemented at the power module design stage and that can result in modules with lower noise emissions in the conducted EMI frequency range. Four 1.2 kV SiC MOSFET power modules are fabricated with different architectures found from literature to better understand their impact on EMI mitigation and to identify trade-offs. Module architectures with integrated CM screens connected to two different DC nodes are experimentally tested and an in-depth analysis on the EMI results is presented. Experimental results show that using a CM screen connected to the DC–link midpoint allows for up to 26 dB of CM current reduction at the baseplate of the module and the input of the converter. Furthermore, this integrated CM screen configuration enables a 0.5% increase in efficiency.


I. INTRODUCTION
The superior material properties of wide-bandgap (WBG) power semiconductors enable them to switch faster, block higher voltages, and have higher current densities compared to silicon devices.With these characteristics, WBG power semiconductors have the potential to improve the efficiency and power density of power electronic converters.However, one of the fundamental roadblocks to fully benefiting from WBG devices is the conducted electromagnetic interference (EMI) associated with high-speed switching of WBG devices [1].
To take advantage of the intrinsic benefits of WBG devices, designers are pursuing power converters with higher dv/dt, switching frequency, and DC-bus voltages.These three factors, enabled by WBG devices, improve power converter efficiency and density, but also exacerbate common-mode (CM) emissions in the conductive EMI frequency range (150 kHz to 30 MHz) [2].Of particular concern is the CM current propagating through the power module switching-node capacitance during switching transients.This CM current can flow into the cooling system and control circuitry, and cause erroneous signals and even catastrophic failure of the converter [3].
In this article, four different module architectures found in literature are comprehensively studied to understand the relationship between the package design and EMI mitigation.The effectiveness of the different module architectures in mitigating noise is investigated by packaging and testing 1.2 kV SiC MOSFET power modules.A module design that keeps key factors consistent between the four module variations and allows to test them under the same conditions is proposed.The experimental results of the two integrated CM screen module architectures are then looked into in more detail.An in-depth analysis comparing the EMI performance of the two architectures is presented using substitution and superposition principle, and noise transfer functions.Doing so gives insight into the effectiveness of the CM screen architectures and the impact of connecting a screen to different DC nodes.This work aims to offer module designers guidance in EMI mitigation at the packaging level.The article shows that by modifying the module architectures, lower CM noise emission can be obtained, which can help reduce the size of filters and converter level EMI solutions.
This article is divided into five major parts: Section II provides a survey of module architectures that have been used in literature for EMI mitigation, Section III covers the design of the modules and the variations that will be tested, and Section IV covers the test setup and experimental results.Additionally, Section V covers simulation analysis to understand the mitigation results seen between the two integrated CM screen module architectures studied in more detail, Section VI covers a discussion of the results, thermal testing, key tradeoffs, and Section VII provides the conclusion of the study.

II. BACKGROUND
For the past decade, research has focused on addressing issues relating to CM current for WBG devices at different levels of the converter.Many researchers have focused on minimizing the impact of CM current on the auxiliary circuitry through proper layout and improved gate driver architecture [4].Such architectures have enabled gate drivers to achieve high CM noise immunity and function under high dv/dt conditions without false turn-on [5].Other solutions, such as CM chokes and EMI filters, are often implemented at the input of the converter to minimize the amount of CM current flowing into the system [6].However, this solution increases the weight and volume of the system and limits the efficiency and power density of the converters [4].For example, the addition of an EMI filter can occupy nearly one-third of the volume of the converter [7], hence lowering the power density of the system.Other CM current solutions involve switching control schemes, parasitic capacitance balancing, and the use of active gate drivers to minimize issues related to CM current [4], [8].Some authors have proposed separated heatsinks for modules to prevent CM current from flowing to the ground in a three-phase, SiC-based inverter [9].Most of the EMI mitigation techniques available in literature require a trade-off to be made in the system level.Often times, bulky EMI filters are added directly to the power path of the converter and must be adequately designed to reduce power losses [6], [10].Slowing down the slew rates can reduce noise generated but also increases switching losses [11].Active gate drivers employ slew rate control to help achieve a balance between switching losses and EMI noise but can increase the complexity of the circuitry and controls of the converters [8], [12].
Less work has been dedicated to studying and mitigating CM current at the power module level.Reducing the EMI generated at the packaging level will not eliminate the need for a filter, but it can minimize the amount of noise at the converter level that will need to be filtered.With the rise of WBG devices, the layout and design of power modules have garnered attention due to the higher sensitivity of WBG devices to parasitic inductances and capacitances [13].Since CM current is worsened by these parasitics, which are related to the power module design, EMI mitigation and containment solutions at the package level are being investigated [2].
When it comes to reducing CM noise inside the package, a large portion of the literature is focused on minimizing the power-loop and gate-loop inductances that lead to ringing during switching events.A popular way to reduce the impact of stray inductances is to integrate decoupling capacitors inside the module to reduce the commutation loop [14].Other designers have attempted to reduce the dv/dt of the module by embedding gate resistors to slow down the fast switching transients [15] or embedding resistor-capacitor (RC) snubbers and ferrite beads to reduce voltage ringing during switching events [9].These techniques help mitigate CM current by reducing the switching speed; this approach offsets the benefits offered by WBG devices.
Other studies have focused on the capacitive coupling to the baseplate to mitigate the flow of CM current.The literature has proposed mitigating CM current by reducing the capacitive coupling of the switching-node to the baseplate present in the power module [16].In traditional power modules, an insulated substrate is patterned to form a half-bridge configuration, with the switching-node pad being a significant portion of the footprint.This switching-node pad has capacitive coupling across the substrate insulation to the baseplate, creating a critical path for CM current to flow through.This capacitive coupling can be reduced either by shrinking the footprint of the switching-node or increasing the thickness of the insulation dielectric [17].Other techniques include removing regions of the insulated substrate's bottom copper layer and replacing it with low-permittivity material [18], and canceling the CM current through the baseplate of a single-phase inverter with symmetric input and output impedances with respect to EMI testbed ground [19], [20].This CM current cancellation is achieved by manipulating the ratio between the switching-node capacitance and the equivalent baseplate capacitance.In addition, it has been shown that reducing the switching-node capacitance of the module and balancing the DC+ and DC-rail parasitics help reduce CM current by minimizing differential mode (DM) to CM conversion [21].
Another effective way to mitigate CM current is by using a CM screen.The CM screen diverts the current that would go through the switching-node capacitance away from the baseplate and contains it within the DC-bus [22].The CM screen architecture allows the CM current to circulate within the module instead of flowing into the baseplate through the baseplate [23].This CM screen can be effective in various applications, topologies, and converters.Fig. 1 shows a traditional module layout and different variations of the CM screen proposed in the literature.Fig. 1(a) shows a half-bridge schematic with each node colored.The switching-node (green) and its associated capacitance to the baseplate are labeled as OUT and C CM, respectively.The DC+ node is represented by red, the DC-node is represented by blue, and the DC Mid node is represented by light blue, respectively.Fig. 1(b) shows a traditional baseline module layout with C CM coupled across the dielectric insulation to the baseplate [19].
Fig. 1(c) highlights a CM screen technique with the screening layer connected to the DC-node.By having two insulation layers, a middle metal layer is formed to serve as the screen and divert the CM current flowing through C CM to the connected DC bus node.A 1.2 kV SiC MOSFET module utilizing this technique was tested at 600 V in a buck converter.It showed a 14 dB noise reduction at the input noise current compared to a commercial reference module [23].In [24], it was proposed to connect the CM screen to the DC+ node using wire bonds (Fig. 1(d)), although no module or testing results were presented.
Fig. 1(e) shows a CM screen technique with the screening layer connected to the DC midpoint (DC Mid).This connection is achieved through two series capacitors (purple) to create a DC Mid voltage bus (Fig. 1(e)).In the literature, a 1.2 kV SiC MOSFET module was developed with this configuration and tested at 60 V in a boost converter.The results show a 12-dB reduction in the input noise current compared to the design without a CM screen [25].This same screening technique was proposed and implemented for a wire bond-less 10 kV SiC MOSFET module [25].Double pulse test (DPT) results at 2 kV show an order of magnitude reduction in CM current though the baseplate when compared to the module without a CM screen [25].
Fig. 1(f) shows a CM screen technique for double-sided cooling modules with two screening layers, one of which is connected to DC+ and the other to DC-.This CM screen technique was implemented in a 3D double-sided 1.2 kV module and tested at 400 V in an inverter [26].A 15-dB reduction in the input voltage noise was achieved when compared to a 2D version of the package [26].Other iterations of this double-sided screen have been proposed in [27], [28].
Although the CM screen technique has been demonstrated previously, no in-depth study of its layout and implementation has been conducted.The effectiveness of the CM screen varies by module design and the implementation of the screen.This is because the amount of CM current that is diverted strongly depends on the high-frequency impedance of the connection to the DC-bus.Overall, the literature shows that single-sided cooling modules often have a single screen connected to the DC-node [23].Double-sided modules have the flexibility of having two screens connected to the DC+ and DC-, respectively [26].Most of the CM screen techniques show a 10 dB to 20 dB CM noise reduction at the input of the converter [23], [25], [26], [29].However, since each module has different semiconductor devices, C CM values, testing conditions, and topologies, it is difficult to compare the screening techniques, and makes selection of the most effective CM screen design challenging.
This study builds on the work found in literature by performing a comparative study on the EMI behavior of four module architectures.Compared to literature, a more detail evaluation of the architectures is performed by measuring the noise at the baseplate of the module and at the input of the converter used.The effect of module architecture on the efficiency of the converter is also measured.From among the CM screen module that can be found in literature, the article focuses on the architectures in which the CM screen is connected to the DC+ node (Fig. 1(d)) and to DC Mid node (Fig. 1(e)).As previously stated, connecting the CM screen to the DC+ node exclusively has not been experimentally verified in literature.Similarly, the CM screen attached to the DC Mid node is investigated since it has shown to be promising in terms of EMI mitigation.An in-depth analysis on the screening layer's effectiveness as it is connected to the two different DC nodes is then presented.The analysis shows in detail why the two CM screen modules show different EMI behaviors and the effect dv/dt and di/dt transients have on the current i bp .

III. COMMON-MODE SCREEN MODULES A. MODULE LAYOUT
To study the impact of the CM screen, a new module design was developed.The design allows for testing the CM screen under different design conditions and provides insight into the effectiveness of containing CM current within the module.Fig. 2(a) shows the topside view of the layout where 1.2 kV, A side view of the CM screen module is shown in Fig. 2(b).The module uses two 0.35-mm-thick alumina direct-bondedcopper (DBC) substrates stacked together to create the screening layer.Wire bonds are used to electrically connect the top copper layer to the screening layer.This layout enables paralleling of many wire bonds to reduce the impedance to the screening layer.
In the literature, the CM screen is used to contain CM current but also as a path for the commutation loop [22].This enables a reduction in the power-loop inductance through magnetic field cancellation, which enables cleaner switching events that reduce EMI [22].To avoid variations in the EMI due to changes in the power-loop inductances, all of the proposed modules have the commutation loop on the topside of DBC 1 (Fig. 2(b)).This allows for the screening layer to be used only to divert CM current and not to serve as part of commutation loop.This enables modification of the screening layer while keeping the power loop inductance consistent between a baseline and CM screen design.ANSYS Q3D simulations show that the power-loop inductance with and without the decoupling capacitors inside the module is 3.5 nH and 7.5 nH at 100 MHz respectively.
The switching-node capacitance across DBC 1 to the screening layer is denoted as C CM .The screening layer capacitance across DBC 2 to the baseplate is denoted as C screen .Furthermore, C CM is 80 pF, and C screen is 437 pF for all the module variations.The module design also allows for two paralleled 10 nF decoupling capacitors to be placed in series to minimize the power-loop inductance and form the DC Mid node.

B. MODULE VARIATIONS
The amount of CM current that will be diverted to the DC-bus depends on the high-frequency impedance of the screening layer.For the CM screen to be effective, condition (1) has to be satisfied [25]: where Z screen is the impedance of the CM screen to the desired DC node and Z bp is the impedance from the CM screen to the module baseplate.For the case of the two CM screen modules shown in Fig. 3(c) and (d), Z screen can be respectively written as: where L DC+ screen , R DC+ screen and L Mid screen , R Mid screen are the equivalent inductance and resistance of the wire bonds connecting the screening layer to DC+ and DC Mid nodes, respectively; and Z C D is the impedance of the decoupling capacitors.For Fig. 3(d), Z C D will be defined: where C D is the equivalent capacitance of the decoupling capacitors between the DC Mid and DC+ or DC-nodes respectively.In both architectures, the impedance to the baseplate can be given as: where C screen is the screening-layer capacitance across DBC 2 to the baseplate of the module.Using ( 2), (3), and ( 5) the inequality of (1) for the two modules becomes Where Z C D is defined according to (4).It can be seen from ( 6) and ( 7) that it is critical to reduce the parasitic inductance and resistance of the CM screen to be effective in redirecting the CM current to its connected DC node.For the case of the CM screen (DC Mid) module, the decoupling capacitor C D (20 nF) was selected to be greater than 50 times C screen (437 pF) to better divert the CM current from flowing towards the baseplate of the module to the DC Mid node [30].It should be noted that integrating the decoupling capacitors C D into the module increases the footprint of DBC 2 and the value of C screen .For this work, compact ceramic capacitors with high capacitance values were selected to balance the trade-offs between C screen and C D .Furthermore, the capacitors are C0G type, which means they are stable with variations in temperature and voltage.This allows the CM screen to have the same effectiveness under different voltage and temperature profiles.
With the module design established, four design variations (shown in Fig. 3) were developed to study the impact of the module architecture on CM noise reduction.The variations are: r Baseline Module: This variation only uses DBC 1.
The OUT node is coupled to the baseplate through the switching-node capacitance C CM (Fig. 3(a)).
r Baseline (C D ) Module: This variation is the same as the baseline design but with the addition of integrated decoupling capacitors (Fig. 3(b)).
r CM Screen (DC+) Module: DBC 1 and DBC 2 form a screening layer connected to the DC+ node.The DC+ node is coupled to the baseplate through C screen (Fig. 3(c)).There are no integrated decoupling capacitors in this module.The architecture also serves as the CM screen counterpart to the Baseline module.3(d)).This architecture is the CM screen counterpart to the Baseline (C D ) module.In Fig. 3, the high-side and low-side SiC MOSFET dies in the half-bridge schematic are referred to as H and L, respectively, and the nodes in the schematic are color coordinated with the nodes in the module layouts.The final module prototypes are shown in Fig. 4. Testing these modules will provide a better understanding of the EMI mitigation associated with redirecting the CM current to different parts of the DC-bus.

A. TEST SETUP
A test setup was developed to evaluate the level of noise mitigation introduced by each of the module architectures.The designed testbed switches each module as a buck converter operating at a switching frequency of 100 kHz.All experiments are conducted at an input/output voltage of 600/300 V.The setup is comprised of four main subsystems: line impedance stabilization network (LISN), input capacitor C in , power module, and output load.Fig. 5 shows a simplified schematic of the setup and outlines the aforementioned subsystems.Details of various components used in each  1. Fig. 5 also highlights the measurements recorded for analysis: drain-to-source voltage v DS for the high-side switch H, voltage across output load V out , voltage across input capacitor bank V in , current flowing at input of converter i in , noise current that escapes through the module baseplate into the converter i bp and CM noise current at the input of the converter i input .The noise i bp and i input is measured for all four module architectures using the same test setup and testing conditions with only the modules swapped.The results presented were consistent and repeatable using the test setup described.
The noise current i bp was measured to experimentally quantify the noise generated by the module that escapes through the baseplate into the converter.It was measured using the method described in [16].To measure i bp , the module baseplate is clamped onto a heatsink that is physically separated from the copper sheet with the help of non-conductive separators.Current flowing through a conducting wire connecting the heatsink and copper sheet is then measured.The noise current i input is measured to empirically verify the effect of changing the module architecture on the noise flowing at the input of the converter.The noise current i input is measured with a high frequency current transformer (HFCT) clamped around the input terminals of the converter measuring the bundle current across both positive line and negative line.
The testbed was operated at room temperature and all measurements reported were recorded during the electrical steady state.Details of the measurement probes used are provided in Table 1.The analysis in this work is limited to the conducted EMI frequency range (150 kHz to 30 MHz).Measurement probes used were confirmed to have a bandwidth that would allow accurate measurement in the frequency range mentioned.The hardware implementation of the testbed is shown in Fig. 6.The copper sheet used in the test setup is connected to earth potential.

B. TIME DOMAIN MEASUREMENT
The relationship between voltage v DS , switching-node capacitance C CM , and generated noise current i bp is explained for the Baseline module architecture shown in Fig. 3(a).Fig. 7(a) shows the zoomed-in time domain waveform for voltage v DS , and Fig. 7(b) shows the noise current i bp being generated at the same instance in time.In the experiments performed, the direction of current is taken as positive if the current is flowing from the heat sink towards the copper sheet, and is taken as negative if flowing in the reverse direction.
From Fig. 7(a), during the turn-off transient, v DS increases to 600 V at a slew rate of 25.6 V/ns.During this event, the change in potential at the OUT-terminal discharges parasitic capacitor C CM , causing current to flow from the module baseplate to the switching-node [31], [32].During the voltage transition, a CM current flows from the copper sheet to the OUT terminal, resulting in the discharging of C CM (Fig. 7(b)).A negative peak of 2.7 A is observed.

C. BASEPLATE NOISE CURRENT
The frequency spectra of the noise current i bp for different module architectures are shown in Fig. 8.In Fig. 8(a) and (b), the two baseline modules are compared to their CM screen counterpart to observe how integrating a CM screen into the module affects the noise generated at the baseplate.The results confirm that the introduction of the CM screen into the architecture caused noise to be redirected to the respective connected DC node.In both scenarios, a maximum noise reduction of 26 dB is noted due to the redirection of a portion of noise i bp to the connected DC node.A minimum noise reduction of 21 dB and 26 dB is noted in the 150 kHz-1.1 MHz frequency range for the Fig. 8(a) and (b) module respectively.
In Fig. 8(c), i bp generated by the two CM screen architectures is compared.Results show a maximum mitigation of 13 dB.No significant noise reduction is noted in the 150 kHz-1.1 MHz frequency range.The mitigation observed can be attributed to the symmetric decoupling capacitances between the DC+ and DC-nodes and the screening layer [21], [26], [33]; however, the mitigation seen between the two CM screen modules is discussed in more detail in the next section of the article.The mitigation seen at frequencies larger than 10 MHz can be linked to the smaller current commutation loop due to the integrated decoupling capacitors.As previously stated, the power-loop inductance inside the module will reduce from 7.5 nH to 3.5 nH due to the addition of decoupling capacitors.

D. INPUT NOISE CURRENT
Similar to the comparison done for i bp , the effect of module architecture on the noise current i input is also investigated.A maximum noise mitigation of 17 dB and 26 dB is observed between the Baseline and CM screen (DC+) module (Fig. 9 In Fig. 9(c), i input generated by the two CM screen architectures is compared.A maximum mitigation of 18 dB is observed.No significant noise reduction is noted in the 150 kHz-1.1 MHz frequency range.It is important to note that the noise mitigation seen in i input is different from the mitigation seen in i bp and that i input has slightly larger magnitudes in the frequency spectrum compared to i bp .The noise current i bp is the noise generated by the module that escapes though the baseplate into the converter and -with the module being the major source of noise generated -is responsible for a significant portion of i input but not all of it.In particular, noise current i input also incorporates the effect of CM noise generated due to unbalanced impedances inside the converter.Detail on the impact of asymmetries in a buck converter on the CM noise generated can be found in [34].Other examples of CM noise that the noise current i input incorporates are the noise flowing through parasitic capacitances outside the module that the converter may have to the copper sheet.

E. EFFICIENCY AND SWITCHING CHARACTERISTICS
The impact of the CM screen architectures on the converter efficiency and device slew rates was also investigated experimentally.The slew rates for the modules were measured across the drain-to-source voltage v DS for MOSFET H as shown in Fig. 5. Table 2 lists the measured converter efficiencies and slew rates for each module variation.The efficiencies are reported as a percentage increase and decrease while

TABLE 2 Measured Switching Characteristics and Efficiency
keeping the Baseline module as a reference.Comparing the efficiency of the Baseline module to the CM screen (DC+) module, a decrease of 0.3% was measured.This decrease in efficiency can be explained by the increased C oss of the module.Having the CM screen shorted with the DC+ node results in C CM being in parallel with the C oss of the SiC die, thereby increasing the output capacitance of the high-side switch.
Compared to the Baseline module, the Baseline (C D ) and CM screen (DC Mid) showed an increase in efficiency.This increase in efficiency can be explained by investigating the trends observed in the slew rates (Table 2).The Baseline (C D ) module was measured to have a 47% larger falling slew rate.This increased slew rate can be attributed to the reduced current commutation loop that occurs due to the addition of the decoupling capacitors.Similarly, the CM screen (DC Mid) module demonstrates a 59% faster falling slew rate.The shorter turn-on time results in lower switching losses and, therefore, an increase in the efficiency of the overall converter.

V. SIMULATION ANALYSIS A. LTSPICE SIMULATION MODEL
Based on the hardware results presented in Fig. 8, a LTspice simulation model was created for the test setup.Fig. 10 shows the simulation model of the test setup with the Baseline module.In Fig. 10, Z   The experimental results in Fig. 8(c) showed the maximum mitigation of 13 dB between 2.3 MHz and 3.5 MHz frequency range.The simulation shows a maximum mitigation of 9 dB in the same frequency range -a 4 dB lower noise mitigation prediction compared to the hardware results.No significant noise mitigation is noted in the 150 kHz-1.1 MHz frequency range.It can be observed that the simulation is not able to predict the mitigation magnitudes in the frequency spectrum with high fidelity; however, it is able to capture the mitigation trends seen in Fig. 8 with reasonable accuracy.For example, in Fig. 11(c) the CM screen (DC+) and CM screen (DC Mid) modules show similar frequency spectrums in the 150 kHz to 500 kHz frequency range.Similarly, the peak in the frequency spectrum at ∼2.7 MHz for the CM screen (DC+) module slightly shifts to a lower frequency for the CM screen (DC Mid) module.A change in the roll-off slope in the frequency spectrum of the CM screen (DC Mid) module at ∼13.5 MHz is also predicted by the simulation resulting in the module having lower EMI compared to the CM screen (DC+) module.Since the simulation is able to capture the mitigation trends seen in Fig. 8 with reasonable accuracy it can therefore be used to analyze the EMI behavior of the modules in more detail.The inability of the simulation model to predict exact magnitudes can be attributed to using linear, lumped circuit elements to model parasitics inside the converter and the module, and to the die model used not being accurate at high frequencies [36], [37], [38].

B. NOISE MITIGATION IN COMMON-MODE SCREEN MODULES
To understand in more detail why the two CM screen module architectures show different levels of noise mitigation, the flow path taken by i CM -the CM noise current flowing through the capacitor C CM -is looked at more closely.To identify the paths i CM flows through, the substitution theory and superposition principle are applied [39], [40].Substitution theory states that the SiC MOSFET dies in an application can be replaced with a voltage or current source having the exact same terminal voltage or current behavior [41].Either type of source can be used to replace the SiC MOSFET die; however, a substitution that results in the formation of a voltage source loop and/or a current source node must be avoided [40].Fig. 12(a) and (b) shows the simulation model for the two CM screen module architectures shown in Fig. 3(c) and (d).Fig. 12(c) and (d) show the module architectures after the substitution theory has been applied.The SiC MOSFET Q H was replaced with a current source i H and SiC MOSFET Q L was replaced with a voltage source v L .The sources i H and v L have the same respective terminal current and voltage characteristics that MOSFET Q H and Q L would have had during the switching operation of the converter and are therefore the main sources of noise escaping the baseplate into the converter.
Since the converter schematic now consists of no non-linear circuit components, superposition is applied to observe the flow path each source has for i CM .The superposition principle states that the excitations generated by multiple independent current and/or voltage sources present in a circuit is the linear sum of the excitation generated by each individual source.Fig. 13 shows the two superposition states for each of the CM screen modules after being introduced into the simulation model shown in Fig. 10.For this analysis, the component of i CM generated due to the sources i H and v L are referred to as i i H CM and i v L CM (shown in green) respectively.The sum of paths taken by i i H CM and i v L CM equate to the path i CM will flow through during the converter operation.It can be seen from Fig. 13 that more than one path is available for i i H CM and i v L CM to flow through once they reach the screening layer.The portion of i i H CM , i v L CM diverted away from the baseplate by the CM screen is referred to as i i H screen , and i v L screen (shown in purple).The portion that flows into the baseplate of the module is referred to as i i H bp , and i v L bp (shown in orange).The summation of i i H screen and i v L screen , and i i H bp and i v L bp is referred to as i screen , and i bp .The superposition states of voltage source v L and current source i H also allow to study the effect dv/dt and di/dt transients have on the current i bp separately.According to [31], [42], [43], the frequency spectrum of the noise i bp can be equated to the two superposition states through (8) and (9).
Where i v L bp (s) and i i H bp (s) are the frequency spectrum of the noise i bp that escapes the module into the converter during  According to (9), the EMI frequency spectrum of i bp is the sum of the effect of dv/dt and di/dt transients.Looking at the current transfer function magnitude, it can be noted that the magnitudes seen in the current transfer function curve are larger than the magnitudes seen in the admittance transfer function at almost all frequency points.It can therefore be concluded that for the two CM screen modules the di/dt transients have a significant effect on i bp and that the current transfer function cannot be ignored.
The magnitude of the current transfer function |K bp (s)| of the two CM screen modules behave differently: the CM screen (DC Mid) module has a smaller |K bp (s)| compared to the CM screen (DC+) module for the majority of the frequency spectrum.The difference in the current transfer function magnitudes for the two CM screen modules can be understood through Fig. 13(b) and (d).The direction of current i i H screen and i i H CM has been inverted to facilitate ease in understanding.In Fig. 13(b), i i H screen now has a low impedance path available to the screening layer from the DC+ node through parasitic inductance and resistance L DC+ screen and R DC+ screen .The CM screen (DC Mid) module in Fig. 13(d

VI. DISCUSSION
Based on the discussion and analysis presented, it can be seen that integrating a CM screen into a power module can result in mitigation of more than 20 dB and 10 dB at the baseplate of the module and the input of converter.The CM screen (DC Mid) module also showed a 0.5% increase in efficiency compared to a conventional module architecture (Baseline module).The multi-layer design of the CM screen modules has many benefits but come at a cost.
The implementation of a CM screen requires a second substrate in the module design.Although multilayer ceramic substrates have been demonstrated in the literature, they are not yet commercially available [44].This means a second substrate will be needed along with large-area sintering or soldering to join the substrates together.Although this can increase the cost and the manufacturing complexity of the power module, the added expense of adding a second substrate layer to a module can be offset by the lower EMI (e.g., lower filter costs) and increased efficiency.The use of stacked substrates can also increase the complexity of the packaging process when taken to scale.The modules shown in this article were manufactured by hand in small batches, but doubling the amount of substrate material for each module and implementing large-area sintering or soldering to attach substrates is yet to be fully understood in terms of large-scale production and reliability.
The multi-layer design could also come at a cost of decreased thermal performance.To study this, thermal resistance measurements were completed on the Baseline module and CM screen (DC Mid) module using the Analysis Tech Phase 12B Thermal Analyzer.A larger thermal resistance usually signifies a higher junction temperature and worse thermal performance.The R TH, JC was measured according to the transient dual interface method (TDIM) as defined in the JEDEC JESD51-14 standard [45], [46].The results show that the Baseline module has an R TH, JC of 0.69 °C/W and the addition of the CM screen increases the R TH, JC to 1.00 °C/W, which is a 45% increase.It should be noted, however, that the increase in thermal resistance also has to do with the substrate material itself.As previously stated, the module uses alumina DBC substrates since its affordable, widely available, and an industry standard.It should be noted that alumina substrates have a thermal conductivity of ∼20 W/mK, which is far less than the thermal conductivity of other DBC ceramics like aluminum nitride (AlN) with a thermal conductivity of ∼250 W/mK.The higher thermal conductivity of AlN can enable better heat spreading for stacked substrates and reduce peak junction temperature.This is seen in [47] where a multi-layer AlN substrates helped reduce the peak junction temperature of the module by 15% compared to a single AlN substrate.The thermal resistance can be further reduced in stacked substrates by reducing the thickness of the dielectric (alumina) material.This is seen in [22] where by adjusting the thicknesses of the individual layers the heat dissipation of a multilayer module was adjusted to reach a desired maximum chip temperature of 150 °C.The CM screen (DC Mid) module also reduces the electric field concentration at the triple point of the power module [25].This means there is less stress on the dielectric layer which enables thinner dielectric materials to be used (below 0.32 mm).This reduction in the thickness can compensate for the increase in thermal resistance.
Overall, we can see that the CM screen offers many benefits but can create other issues that will need addressing.The tradeoffs and the benefits of a module with a CM screen will ultimately come down to the application it will be used in and the EMI and cooling requirements.

VII. CONCLUSION
In this work, the EMI performance of four different module architectures found in literature is compared.A second substrate layer was added into two of the module architectures to serve as a physical screen to redirect the noise generated by the switching-node to the DC-bus.The experimental results show that integrating a CM screen into the module architecture can reduce the EMI footprint of the module by more than 20 dB.The experimental results also show that changing the DC node connected to the CM screen results in different mitigation levels and efficiencies.From the module architectures analyzed, the CM screen (DC Mid) module showed the best results in terms of EMI performance and efficiency of the converter -a current noise reduction of up to 26 dB at both the baseplate of the module and the input of the converter, and a 0.5% increase in efficiency of the converter.Overall, the results show that an integrated CM screen can reduce the EMI and increase the efficiency of converters and is an essential step in realizing the full benefits of WBG power modules.

FIGURE 1 .
FIGURE 1.(a) Half-bridge schematic with nodes color-coded, (b) side view of a traditional power module with the switching-node pad and capacitance [19], (c) CM screen connected to DC-as proposed by [23], (d) CM screen connected to DC+ [24], (e) CM screen connected to DC Mid [25], (f) CM screen for double-sided module screened by DC+ and DC-[26].

FIGURE 2 .
FIGURE 2. (a) Top view, and (b) side view of common-mode screen module.

FIGURE 3 .
FIGURE 3. Variation of the module (a) baseline module with no common-mode (CM) screen (b) baseline module with no CM screen but with decoupling capacitors, (c) CM screen module with screening layer connected to DC+, and (d) CM screen module with screening layer connected to DC Mid.

FIGURE 4 .
FIGURE 4. Images of the fabricated CM screen module prototypes.

FIGURE 5 .
FIGURE 5. Simplified schematic of EMI test setup for the buck converter.r CM Screen (DC Mid) Module: Two series decoupling capacitors are included to create the midpoint DC Mid.DBC 1 and DBC 2 form a screening layer connected to the DC Mid node.The DC Mid is coupled to the baseplate through C screen (Fig.3(d)).This architecture is the CM screen counterpart to the Baseline (C D ) module.In Fig.3, the high-side and low-side SiC MOSFET dies in the half-bridge schematic are referred to as H and L, respectively, and the nodes in the schematic are color coordinated with the nodes in the module layouts.The final module prototypes are shown in Fig.4.Testing these modules will provide a better understanding of the EMI mitigation associated with redirecting the CM current to different parts of the DC-bus.

FIGURE 6 .
FIGURE 6. Hardware setup of EMI testbed for buck converter.

FIGURE 7 .
FIGURE 7. Zoomed-in time domain waveforms for the baseline module architecture showing (a) high-side SiC MOSFET H drain-source voltage v DS and (b) noise current i bp .

FIGURE 8 .
FIGURE 8. Frequency spectra of noise current i bp for (a) the baseline and CM screen (DC+) modules, (b) the baseline (C D ) and CM screen (DC Mid) modules, and (c) the CM screen (DC+) and CM screen (DC Mid) modules.
(a)), and the Baseline (C D ) and CM screen (DC Mid) module (Fig. 9(b)), respectively.A minimum noise reduction of 10 dB is noted in the 150 kHz-1.1 MHz frequency range for both the comparisons.Larger mitigation is seen in the Baseline (C D ) module and its CM screen counterpart at frequencies greater than 10 MHz.

FIGURE 9 .
FIGURE 9. Frequency spectra of noise current i input for (a) the baseline and CM screen (DC+) modules, (b) the baseline (C D ) and CM screen (DC Mid) modules, and (c) the CM screen (DC+) and CM screen (DC Mid) modules.

FIGURE 10 .
FIGURE 10.Simulation model of test setup with the baseline module architecture.
Cin and Z C PCB are the total impedances of the input capacitor bank C in and the decoupling capacitors C PCB -capacitance installed on the PCB board used to interface the module with the rest of the converter.The impedances Z Cin and Z C PCB incorporate the equivalent series inductance (ESL) and equivalent series resistance (ESR) of the capacitors.The impedances Z Jx where x = {1 − 6} represent the parasitic impedances of the wires connecting the LISN to Z Cin , Z Cin to Z C PCB , and of the PCB interfacing Z C PCB to the module architecture.The impedances Z H1 and Z H2 are the parasitic impedances of the wire connecting the heat sink to the copper sheet and of the copper sheet used in the EMI test setup.The capacitance C H1 is the parasitic capacitance between the heat sink raised through non-conductive separators and the copper sheet.Estimates of these impedances were obtained using the methodology detailed in [35] with an Agilent 4294A precision impedance analyzer.The simulated noise current i bp is the current flowing through the impedance Z H1 .The impedances Z Jy where y = {7 − 11} model the parasitic inductances and resistances inside the module and C DC+ , C DC-, and C CM are the parasitic capacitances the DC+, DC-and OUT terminal (Fig. 2) have to the baseplate from across the DBC substrate.

FIGURE 11 .
FIGURE 11.Frequency spectra of noise current i bp from simulation for (a) the baseline and CM screen (DC+) modules, (b) the baseline (C D ) and CM screen (DC Mid) modules, and (c) the CM screen (DC+) and CM screen (DC Mid) modules.

FIGURE 12 .
FIGURE 12. Simulation model for module architecture (a) CM Screen (DC+) (b) CM Screen (DC Mid) and substitution theory applied to module architecture (c) CM screen (DC+) (d) CM screen (DC Mid).

FIGURE 13 .
FIGURE 13.Converter schematic showing path taken by noise current i CM flowing through C CM due to (a) voltage source v L in CM screen (DC+) architecture (b) current source i H in CM screen (DC+) architecture (c) voltage source v L in CM screen (DC Mid) architecture (d) current source i H in CM screen (DC Mid) architecture.All other current path other than for i CM are ignored.

FIGURE 14 .
FIGURE 14. Magnitude of (a) admittance transfer function Y bp and (b) current transfer function K bp for the CM screen (DC+) (red) and CM screen (DC Mid) (blue) module architectures.
i H(s) are the admittance and current transfer functions obtained from the simulation of the superposition states shown in Fig.13.To evaluate the effect the two CM screen modules have on the noise i bp , the magnitudes of the transfer functions Y bp (s) and K bp (s) are simulated and compared.Although the location of poles, zeros and the physical factors they depend on would be interesting to explore for the two transfer functions, they are beyond the scope of this study.The flow path taken by i CM in the case of the CM screen modules is shown in Fig. 13.The magnitude of the admittance transfer function Y bp (s) and current transfer function K bp (s) for the CM screen (DC+) and (DC Mid) module is shown in red and blue in Fig. 14 respectively.The reason why the two CM screen modules show different EMI results can now be explored.It can be observed that |Y bp (s)| for the two CM screen modules behaves differently: the CM screen (DC+) module has a smaller |Y bp (s)| compared to the CM screen (DC Mid) module for majority of the frequency spectrum and only after ∼9 MHz does the CM screen (DC+) module have a larger admittance magnitude than the CM screen (DC Mid) module.The smaller admittance magnitude seen in the CM screen (DC+) module below ∼9 MHz can be explained by looking at Fig. 13.In Fig. 13(a), i v L CM branches of into i v L screen and i v L bp at the screening layer.Current i v L screen flows through parasitic inductance and resistance L DC+ screen and R DC+ screen before it reaches the DC+ node the screening layer has been shorted to.The CM screen (DC Mid) module in Fig. 13(c), however has the additional impedances Z C D present in the path taken by i vL screen .The |Y bp (s)| graph of Fig. 14(a) shows that less current is diverted away from the baseplate in case of the CM screen (DC Mid) module below ∼9 MHz due to the impedances Z C D , resulting in i vL bp for the CM screen (DC Mid) module to have a larger admittance with respect to v L than the CM screen (DC+) module.This implies that the CM screen (DC Mid) module should have a larger EMI footprint compared to the CM screen (DC+) module for the majority of the frequencies below ∼9 MHz.This prediction, however, is not mirrored in the EMI noise spectrum obtained in Figs.8(c) and 11(c).The reasoning behind this can be understood by looking at (9) and Fig. 14(b).
) however has an additional impedance of Z C D present in the path taken by i i H screen resulting in a smaller portion of i H being diverted into the screening layer.The |K bp (s)| graph of Fig. 14(b) also shows that the additional impedance of Z C D results in less noise current entering the CM screen thereby resulting in less current flowing out of the baseplate.The trends shown in the |K bp (s)| plots for the two CM screen modules follow the trends seen in the EMI noise spectrums obtained in Figs.8(c) and 11(c).The trends do not match exactly as the effect of dv/dt transients cannot be completely ignored.

TABLE 1 Summary of Setup Specifications subsystem
have been provided in Table