Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement

Realizing an isolated three-phase Power Factor Correction (PFC) ac-dc converter as a phase-modular system, i.e., by star-connecting three single-phase PFC rectifier front-ends with individual isolated dc-dc converter stages generating a common dc output voltage advantageously facilitates the use of standard single-phase converter modules. Further the low dc-link voltage level of typically <inline-formula><tex-math notation="LaTeX">$400 \,{\rm {V}}$</tex-math></inline-formula> (for a grid with <inline-formula><tex-math notation="LaTeX">$230 \,{\rm {V}}_{\rm{rms}}$</tex-math></inline-formula> line-to-neutral voltage) allows to employ high performance <inline-formula><tex-math notation="LaTeX">$600 \,{\rm {V}}$</tex-math></inline-formula> power semiconductors. The main drawback of this concept, however, is the fact that the time-varying single-phase input power only sums to a constant three-phase output power at the isolated dc output, such that large dc-link capacitor values are required in each module (in the range of several <inline-formula><tex-math notation="LaTeX">$100 \,{\mu }{\rm{F}}$</tex-math></inline-formula> for a <inline-formula><tex-math notation="LaTeX">$6 \,{\rm{kW}}$</tex-math></inline-formula> system), thereby limiting the achievable power density. It is known from literature that the dc-link energy buffering requirement <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> can be reduced by means of a third-harmonic common-mode (CM) voltage injection modulation and this article identifies the optimal CM voltage waveform with respect to minimizing <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula>, i.e., reducing <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> to the theoretical minimum by combining a brute-force evaluation of the time-domain CM voltage waveform with phase-symmetry considerations. Additionally, converter operation with minimum dc-link voltage and/or dc-link capacitor values is analyzed and a saturable grid current controller allowing operation of the PFC rectifier front-ends with the optimal CM voltage waveform is investigated. Experimental results with a <inline-formula><tex-math notation="LaTeX">$6 \,{\rm{kW}}$</tex-math></inline-formula> prototype system yield a reduction in <inline-formula><tex-math notation="LaTeX">$ {\Delta} {E}_{\rm{dc}}$</tex-math></inline-formula> by up to <inline-formula><tex-math notation="LaTeX">$42{\%}$</tex-math></inline-formula> (compared to conventional sinusoidal modulation), which closely matches the theoretical prediction. Also, PFC rectifier operation with a dc-link voltage level as low as <inline-formula><tex-math notation="LaTeX">$285 \,{\rm {V}}$</tex-math></inline-formula> (i.e., below the <inline-formula><tex-math notation="LaTeX">$325 \,{\rm {V}}_\mathrm{pk}$</tex-math></inline-formula> grid line-to-neutral voltage amplitude) and with ultra-low dc-link capacitor values is demonstrated.


FIGURE 1. (a) Considered converter structure of a phase-modular three-phase isolated Power Factor Correction (PFC) ac-dc converter system (main specifications are listed in
): Each phase module comprises a totem-pole PFC rectifier front-end with an HF bridge-leg and an LF unfolder bridge-leg combined with an isolated dc-dc converter stage connected to a common dc output voltage U out . The module starpointN is not connected to the grid starpoint N such that the CM voltage uN N does not drive any current in the grid [14]. (b) ac-side equivalent circuit of the system: Although the CM voltage does not impact the grid currents, the grid currents flow through the Low-Frequency (LF) Common-Mode (CM) voltageū CM which hence can be used to alter the LF module input power flow.
power. Hence, large dc-link capacitor values C dc are required which limit the maximally achievable volumetric converter power density.
Third-harmonic Common Mode (CM) voltage injection modulation [15] and Space Vector Modulation (SVM) [16] are known from the field of non-modular/monolithic threephase motor drive inverter systems and allow to increase the linear voltage operating range and/or dc-link voltage utilization. It was shown in [14], [17] that third-harmonic injection modulation, which results in a CM voltage u CM between the grid starpoint N and the module starpointN in Fig. 1(a), allows to redirect the pulsating single-phase input power among the modules, where sinusoidal grid currents i a , i b , i c are maintained due to the open starpoint configuration (a similar concept is also known from cascaded modular Hbridge converters [18], [19], [20]). Thereby, the dc-link energy buffering requirement can be reduced by up to 30% compared to conventional modulation (and up to 39% for phase-shifted third-harmonic voltage injection) [17] and further the minimally required dc-link voltageŪ dc and/or dc-link capacitance value C dc can be reduced. The analysis of CM voltage injection in literature is, however, thus far limited to specific voltage waveforms (e.g., the above mentioned third-harmonic voltage injection), and this article derives the optimum CM voltage waveform to minimize the dc-link energy buffering requirement by combining a brute-force waveform evaluation within the (time-varying) range of feasible CM voltages and phase-symmetry considerations.
This article is structured as follows: Section II discusses the impact of the Low Frequency (LF) CM voltage on the PFC rectifier front-end power pulsation and identifies the optimal time-domain CM voltage waveform. Further, the lower bound of the dc-link voltage and dc-link capacitor values for the optimal CM voltage modulation is derived. Then, Section III presents a collaborative control structure where at any given point in time only two out of three rectifier modules are switched at High-Frequency (HF), thereby enabling PFC rectifier front-end operation with the optimal CM voltage injection modulation. Experimental results with a 6 kW prototype system that verify the theoretical considerations are presented in Sections IV and V summarizes the main findings of this article. Additionally, Appendix A discusses several dc-link voltage levels and the corresponding optimal CM voltage waveforms.

II. OPTIMUM CM VOLTAGE INJECTION MODULATION A. POWER FLOW FUNDAMENTALS
The primary goal of the PFC rectifier front-ends in Fig. 1(a) (main converter waveforms are shown in Fig. 2) is to regulate sinusoidal grid currents i a , i b , i c with amplitudeÎ ac and in phase with the respective grid voltages u a , u b , u c with ampli-tudeÛ ac . The grid power of phase x ∈ {a, b, c} is defined as with the phase angles φ x = {0, −120 • , −240 • }, and comprises an ac component p g,x∼ at twice the grid angular frequency ω ac = 2π f ac on top of the average phase input power P g,x = 1 3 P N , with P N the nominal system power. Fig. 1(b) depicts the ac-side equivalent circuit of the system. The module starpointN is not connected to the grid starpoint N and therefore the CM voltage uN N (comprising an HF component u CM∼ and an LF componentū CM ) does not drive any current. However, the grid phase currents flow through the LF CM voltageū CM in each module which thereby impacts the LF input power of module x as Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.  Table 1  For a constant PFC rectifier front-end dc output power P x = P g,x (assuming a lossless power conversion) the energy buffered by the dc-link capacitor C dc of module x is defined as With E dc = max(E dc,x (t )) − min(E dc,x (t )) as energy buffering requirement of the dc-link capacitors C dc , and the LF peak-to-peak voltage fluctuation of the dc-link capacitors results to   Fig. 2(a.ii)) shows the characteristic twice-mains-frequency single-phase grid variation. Here, the energy buffering requirement (highlighted by a gray area) results to with E dc,0 = 6.4 J for the specifications in Table 1.
In contrast, Fig. 2(b) illustrates operation with a thirdharmonic injection amplitude of 0.4 ×Û ac . Here, the LF module input power isp x (t ) = p g,x (t ) and the power pulsation is shifted to higher frequencies such that E dc = 4.5 J is reduced by 30% compared to conventional modulation. This was verified experimentally in [17] and a reduction by up to 38% was achieved for a third-harmonic injection amplitude 0.6 ×Û ac which, however, requires a third-harmonic voltage phase shift φ 3rd = 11 • to maintain grid current controllability.
The concept of CM voltage injection modulation is, however, not limited to third-harmonic voltages and the goal of the subsequent analysis is to identify the optimal LF CM voltage waveformū CM minimizing the dc-link energy buffering requirement E dc .

B. OPTIMAL CM VOLTAGE WAVEFORM IDENTIFICATION
The system in Fig. 1(a) comprises three boost-type PFC rectifier front-ends such that the LF switch node voltageūxN of each module x ∈ {a, b, c} is limited by the respective dc-link voltage U dc,x to values Hence, for a grid with U ac = 230 V rms (line-to-neutral, 400 V rms line-to-line), a typical dc-link voltage levelŪ dc = 400 V is considered here (for completeness, Appendix A further provides the optimal CM voltage waveforms for different values ofŪ dc and Appendix B discusses operation in an unbalanced grid) which advantageously allows the use of 600 V power semiconductors and ensures sufficient voltage margin to maintain grid current controllability in case of, e.g., a load step.
In the following, the LF fluctuation of the dc-link voltages caused by the LF input power pulsation is neglected, i.e., C dc 100 μF is assumed such that U dc,x (t ) =Ū dc . Hence, the boost-type converter input voltage limit (6) for all three modules can be solved for the eligible range of the LF CM voltageū CM which is defined bȳ as highlighted in Fig. 3 forŪ dc = 400 V. Note that current controllability according to (6) is lost in the phase with the instantaneously highest absolute grid voltage value |u x | in case ofū CM exceeding this limit (7).
In order to identify the optimal LF CM voltage waveform u CM , the CM voltage range defined by (7) within one grid period T ac = 1/ f ac is discretized with n t values in the time domain and with n u CM voltage values. Fig. 3 illustrates the discretized voltage and time values with scatter points for n u = 5 and n t = 25. The number of possible LF CM voltage waveforms (i.e., the number of permutations for n u discrete CM voltage values and n t time positions) grows exponentially with the discretization resolution as n = n n t u with n ≈ 3 × 10 17 for the considered example, i.e., an excessive number of paths to be evaluated results even for the low example resolution. However, symmetry considerations allow to drastically decrease the number of paths n: 1) The CM voltage waveform must equally impact the energy buffering requirement in all three PFC rectifier front-ends, which corresponds to a 120 • symmetry of the CM voltage. Hence, the CM waveforms are only explored within one 120 Fig. 3). The full 360 • waveforms are then obtained by replicating the 120 • waveforms (i.e., with u CM (ωt ) =ū CM (ωt + 120 • )) and the total number of paths is reduced to n = n (n t −1)/3+1 u ≈ 2 × 10 6 for the considered example. 2) Within the considered 120 , symmetry along the ωt = 90 • axis is required as otherwise the energy buffering requirement E dc is, e.g., decreased in the first 60 • segment but increased in the second 60 • segment (or vice versa). Hence, the CM voltage waveforms are only explored within the first 60 • segment (ωt ∈ [30 • , 90 • ]) and mirrored to the second segment (i.e.,ū CM (90 • + ωt ) =ū CM (90 • − ωt )). With (i) and (ii) the number of paths is reduced to n = n (n t −1)/6+1 u ≈ 3 × 10 3 for the considered example.
3) The number of CM waveforms to be evaluated can be further decreased by only considering the waveforms with half-wave symmetry (i.e.,ū CM (180 • + ωt ) = −ū CM (180 • − ωt )), as otherwise the energy buffering requirement E dc is, e.g., decreased in the first 180 • half-period but increased in the second 180 • half-period (or vice versa). Combined with (i) and (ii) this results toū CM (60 • + ωt ) = −ū CM (60 • − ωt ) andū CM (ωt = 60 • ) = 0 (any signal comprising only triplen harmonics with sin(k · 3 f ac ) at multiples k ∈ N of 3 f ac results to zero at ωt = 60 • ) Hence, the valid CM voltage waveforms can be defined upon a single 30 • interval and the number of paths is reduced to n = n (n t −1)/12 u = 25 for the considered example. The CM voltage waveforms (calculated in MATLAB) obtained with (i) and (ii) are highlighted in Fig. 3(b) with thin gray lines, and the resulting n = 25 valid waveforms according to (i)-(iii) are further highlighted with the line color indicating the resulting energy buffering requirement E dc relative to E dc,0 (modulation without CM injection andū CM = 0). The bestū CM,opt and worstū CM,FT CM voltage waveforms with respect to the resulting E dc are highlighted with thicker lines in Fig. 3(b) and discussed in more detail in the following.

C. OPTIMAL CM VOLTAGE WAVEFORM RESULTS
A high-resolution waveform sweep with n u = 9 and n t = 97 is conducted and the symmetry conditions (i)-(iii) reduce the number of investigated waveforms from n ≈ 4 × 10 92 to n ≈ 43 × 10 6 which is manageable with state-of-the art compute servers.
The resulting optimal LF CM voltage waveformū CM,opt is very similar to Fig. 3(b) and converges (with increasing resolution n u and n t ) to the Discontinuous Pulse Width Modulation (DPWM) strategy (which should not be confused with Digital PWM) highlighted in Fig. 4(a), where the switch-nodex of the phase x ∈ {a, b, c} with the instantaneous middle absolute grid voltage value |u x (t )| = median(|u a (t )|, |u b (t )|, |u c (t )|) is clamped depending on the instantaneous grid voltage polarity to the positive (if u x > 0) or negative (if u x < 0) dc-link rail, andū CM,opt is defined as which, e.g., for the first 120 • interval of the grid period results toū Such a modulation strategy is known in literature within the context of non-modular/monolithic three-phase PFC ac-dc converters [21] (featuring a single dc output voltage) and cascaded modular H-bridge converters [20], and the CM voltagē u CM,opt increases the LF module input powerp a in the vicinity of ωt = 30 • and decreasesp a around ωt = 90 • compared tō p a,0 representing the LF input power for conventional operation as comparison.
For this CM voltage waveformū CM,opt the energy buffering requirement of the PFC rectifier front-ends (visualized by the light-gray areas in Fig. 4(a)) results to E dc = 3.6 J, i.e., a reduction of 43% is achieved compared to the conventional modulation withū CM = 0 presented in Fig. 2(a). Additionally, the semiconductor switching losses are advantageously reduced due to the 1/3 lower number of switching actions (enabled by the DPWM operation where always one out of three PFC rectifier front-ends is in a clamped state) compared toū CM = 0 (where all PFC rectifier front-ends are continuously switching). Note that the time discretization n t limits the derivative dū CM /dt at the CM voltage zero crossing at k · 60 • (k ∈ N, see Fig. 3(b)). However, for n t = 97 the resulting E dc differs by only <1% from the ideal waveforms depicted in Fig. 4(a).
For completeness, also the worst (with respect to minimizing E dc ) CM voltage waveformū CM,FT given by the Flat Top (FT) DPWM [21], [22], [23] strategy is highlighted in Fig. 4(b). There, the switch-nodex of the phase x with the instantaneous maximum absolute grid voltage value is clamped depending on the instantaneous grid voltage polarity to the positive (if u x > 0) or negative (if u x < 0) dc-link rail. Such a modulation is optimal with respect to switching losses, as the PFC rectifier front-end with the highest instantaneous current values ceases switching and is hence of interest in non-modular/monolithic PFC ac-dc converters without LF energy storage requirement. However, here, the energy buffering requirement of the PFC rectifier front-end increases by 41% compared to conventional modulation to E dc = 9.0 J. The reason for this increase in E dc becomes obvious from Fig. 4(a.ii) as, e.g., for phase a, the waveform u CM,FT further increases the module input powerp a in the vicinity of ωt = 90 • where the maximum pulsation of the grid power p g,a occurs.

D. MINIMUM DC-LINK VOLTAGE / CAPACITANCE OPERATION
For finite dc-link capacitance values C dc the dc-link voltages fluctuate due to the pulsating LF module input powerp x . Given that (6) is fulfilled for all modules throughout the fundamental grid period (i.e., grid current controllability is maintained), the dc-link voltage fluctuation does not impact the generation of the LF CM voltage for, e.g., conventional modulation and third-harmonic voltage injection. This, however, does not apply for the DPWM strategies depicted in Fig. 4: If one phase x clamps its switch nodex to the corresponding positive dc-link rail, the CM voltage reference for the two remaining PFC rectifier front-ends switching at HF is defined asū CM (t ) = U dc,x (t ) − u x (t ), i.e., is affected by the LF dc-link voltage fluctuation of phase x. Hence, according to (2) the LF fluctuation of the dc-link voltage U dc,x (t ) impacts the module input powerp x (t ), and vice versa, such that no simple analytic expression exists to describe the input voltage, current and power waveforms of the PFC rectifier front-end for finite values of C dc . Therefore, the numerical calculation of the steady-state input power waveforms and the corresponding fluctuation of the dc-link voltages is performed iteratively in MATLAB until the waveforms converge. Fig. 5(a) presents the calculated main PFC rectifier frontend waveforms for an average dc-link voltageŪ dc = 400 V and C dc = 231 μF in each phase. There, the peak-to-peak dclink voltage fluctuation results to U dc = 38.9 V and slightly impacts the generated CM voltage waveformū CM . However, the LF module input powerp a is largely identical to Fig. 4(a) with C dc → ∞ such that also the resulting E dc = 3.6 J remains unaffected by the finite dc-link capacitor value.
The relevant question for the practical realization of the optimal CM modulation of Section II-C is hence what minimum amount of dc-link capacitance C dc,min is required in each phase module to assure the safe PFC rectifier front-end operation. For this, two relevant conditions exist: First, the current controllability according to (6) needs to be maintained. Second, the maximum blocking voltage of the power semiconductors must be respected, corresponding in each phase x to the constraint with typically U b,max = 420 V for 600 V power semiconductors to assure a blocking voltage margin of 30% which is considered in the following. Fig. 6 investigates the minimally required dc-link capacitor value C dc,min of the optimal CM voltage injection modulation for nominal power operation according to Table 1 as a function of the average dc-link voltage levelsŪ dc . The steadystate input power waveform and the corresponding fluctuation of the dc-link voltages are again calculated numerically in MATLAB and for a given value ofŪ dc , C dc,min is obtained by decreasing C dc iteratively up to the point where either (6) or (10) is no longer fulfilled.
The previously discussed operating condition in Fig. 5(a) is highlighted in Fig. 6 and the selected capacitance value corresponds to C dc,min = 231 μF forŪ dc = 400 V, which is substantially below C dc,min,0 = 400 μF required to comply with (10) for the conventional operation illustrated in Fig. 2(a) [14], [24]. The resulting minimum values U dc,min and maximum values U dc,max within a fundamental period of the dc-link voltage U dc,x (t ) are also highlighted in Fig. 6 on the second y-axis. There it becomes obvious that forŪ dc = 400 V the minimum dc-link capacitor value C dc,min is constrained by the maximum dc-link voltage value U dc,max and (10).
Hence, lowering the average dc-link voltage toŪ dc = 315 V (at this point C dc,min is equally constrained from (6) and (10)) allows operation with a substantially lower C dc,min = 88 μF (i.e., a 62% reduction compared toŪ dc = 400 V). Note that now the grid voltage amplitude is larger than the average dc-link voltageÛ ac >Ū dc (i.e., conventional operation with u CM = 0 is not possible) and the corresponding main PFC rectifier front-end waveforms are presented in Fig. 5(b). Here, the dc-link capacitor utilization is high (i.e., a small C dc is sufficient to maintain PFC rectifier operation) and a voltage fluctuation of U dc = 176.7 V results. This heavily impacts the input power waveforms and increases the energy buffering requirement to E dc = 4.8 J. Note that such a high U dc imposes substantial current stresses on the dc-link capacitors C dc and a wide input-voltage range for the subsequent isolated dc-dc converter stages which needs to be considered in the system design.
Then, for a further decrease of the average dc-link voltagē U dc , the minimum dc-link capacitor value C dc,min is constrained by (6) and increases again. E.g., forŪ dc = 300 V (Fig. 5(c)) andŪ dc = 290 V (Fig. 5(d)), a minimum dc-link capacitor value of C dc,min = 116 μF and C dc,min = 179 μF, respectively, is required and compared toŪ dc = 315 V the dc-link voltage fluctuation reduces again.
In closing it can be stated that the optimal CM modulation of Section II-C enables operation with lower dc-link capacitor values C dc and/or lower average dc-link voltageŪ dc compared to conventional operation and the goal is hence to verify these findings in practice.

III. PFC RECTIFIER CONTROL WITH OPTIMAL CM INJECTION MODULATION
The identified optimum modulation requires a special control structure for the three PFC rectifier front-ends [20], [21], [22], [23], [25] as for a given point in time one out of three phases completely ceases switching and clamps the switch node potential to either the positive or negative dc-link rail and the remaining two phases realize sinusoidal three-phase grid currents i a , i b , i c resulting in a collaborative control where the burden of the grid current control is shared among the PFC rectifier front-ends.
The considered cascaded PFC rectifier control structure is depicted in Fig. 7. The dc-link voltage regulator RU dc (implemented as a Proportional-Integral (PI) controller) sets a grid conductivity reference value G * =Î * ac /Û ac (i.e., the grid current amplitude referenceÎ * ac normalized by the grid voltage amplitudeÛ ac , with the unit −1 ) based on the instantaneous dc-link voltage error and the dc module output current feed-forward term I dc . Note that here the instantaneous mean dc-link voltage 1 3 x∈{a,b,c} U dc,x is considered to later obtain symmetric three-phase current references. In case the dc-link voltage balancing among the three-modules cannot be guaranteed by the subsequent isolated dc-dc converter stages, the control strategy of [2], [26] would need to be implemented.   grid voltages u a , u b , u c which results in reference voltages  u ref,a , u ref,b , u ref,c (only u ref,a is shown)  A sinusoidal grid current reference value i * x with x ∈ {a, b, c} is then obtained by multiplying G * with the respective grid voltage u x . The grid current reference values are then tracked by the phase current controllers Ri x (again implemented as PI controllers) where only two out of three grid currents are regulated (here the currents of phase a and b) and the third control signal is derived with a symmetry condition as only two degrees of freedom exist for the grid currents in an open-starpoint configuration of three PFC rectifier front-ends.
Next, the measured grid voltages are added as feed-forward terms to the phase current controller outputs. The optimal CM voltage injection is realized by means of the saturable CM voltage modulator from [20] with the main controller voltage waveforms highlighted in Fig. 8: A large open-loop CM voltage referenceū * CM = M 3rd ·Û ac sin(3ω ac t ) (with e.g., M 3rd = 1.0) is added as a feed-forward term to the controller outputs. It is important to clarify that forŪ dc = 400 V the resulting voltage reference u ref,x with M 3rd = 1.0 violates the current controllability constraint (6). Therefore, in a second step the saturable CM voltage modulator sets a correction term u CM,s such that in each module x the final reference voltage u ref,x (t ) remains below the limit imposed by the dc-link voltage U dc,x (t ) (corresponding to uxN ∈ [−U dc,x (t ), U dc,x (t )]). Finally, the adjusted reference voltages u ref,x are translated into modulation indices m x ∈ [−1, 1] by division with the respective instantaneous dc-link voltage which allows to generate the power semiconductor control signals in each PFC rectifier front-end by means of PWM for the HF bridgeleg and based on the sign of m x for the LF bridge-leg (see Fig. 1(a)).
Note that by increasing M 3rd , the dū CM /dt at the CM voltage zero crossing (occurring at k · 60 • (k ∈ N) becomes increasingly steep and approaches the ideal waveforms of Fig. 4(a) where a CM voltage step occurs when the clamping reference transitions from one phase to another. However, as found in Section II-C the finite dū CM /dt (resulting there as a consequence of the time discretization) only marginally impacts the energy buffering requirement E dc . Further, a CM voltage reference step might negatively impact the current controllers, such that M 3rd = 1.0 is considered in the experimental verification of the concept.

IV. EXPERIMENTAL VERIFICATION
For the experimental verification of the proposed concept an existing 6 kW prototype system according to Table 1 is employed and details on the hardware can be found in [17]. The converter comprises three single-phase PFC rectifier frontends and three individual resistive loads are used to emulate the subsequent isolated dc-dc converter stages and for the operating point in Fig. 9(a) the dc-link voltage (and hence module dc output current) fluctuation remains below ±10%.
Experimental nominal power PFC rectifier front-end waveforms for conventional modulation withū CM = 0 are depicted in Fig. 9(a) where a sinusoidal grid current i a can be observed. Table 2 lists the measured performance with E dc = 6.5 J (serving in the following as the base value for the relative energy buffering reduction) buffered by the dc-link capacitor in phase a. Note that here, the maximum value of the dc-link voltage U dc,max exceeds the target value from (10) of U b,max = 420 V which prevents the use of 600 V power semiconductors FIGURE 9. Experimental nominal power PFC rectifier front-end waveforms obtained with a 6 kW prototype system according to the system specifications in Table 1 (ūāN +ūbN +ū¯cN ) (highlighted with a semi-transparent cyan line), and grid current  i a of phase a. (x.ii) phase a LF PFC rectifier front-end input voltageūāN, grid current i a , and dc-link voltage U dc,a .

TABLE 2. Measurement Results
(as discussed in Section II-D a dc-link capacitor minimum value of C dc,min,0 = 400 μF is required to allow sufficient voltage blocking margin forū CM = 0). This, however, is not problematic for the prototype system (also allowing operation in delta-configuration withŪ dc = 700 V) employing 1.2 kV SiC power semiconductors. Fig. 9(b) depicts the main converter waveforms for the optimal CM voltage modulation from Section II-C: There, the PFC rectifier front-end voltages are non-sinusoidal and only two out of three modules perform operation with PWM at any given point in time and E dc = 3.8 J is reduced -as predicted -by more than 40% compared to Fig. 9(a). The large CM voltage injection slightly increases the grid current distortion, however, the grid current i a remains sinusoidal and a small Total Harmonic Distortion (THD) of 3.0% results.
Next, the goal is to verify the operation limits of the optimal CM voltage modulation with respect to minimum average dc-link voltageŪ dc and/or dc-link capacitance C dc according to Section II-D. The nominal dc-link capacitance of the prototype system is C dc = 240 μF = 6 × 40 μF realized with film capacitors and can be decreased in steps of 40 μF to approximate the operating conditions highlighted in Fig. 6. The dc-link capacitance C dc measured with an LCR-meter slightly deviates from the nominal capacitance value due to component tolerances and is stated in Table 2 for each considered operating point. Fig. 10(a) presents operation with an average dc-link voltage reduced toŪ dc = 317 V which enables minimum dc-link capacitance operation with C dc = 80 μF while complying with (6) and (10). The grid current i a shows notable distortion FIGURE 10. Experimental nominal power PFC rectifier front-end waveforms for optimal CM voltage injection obtained with a 6 kW prototype system according to the system specifications in Table 1 and with minimum average dc-link voltageŪ dc and/or dc-link capacitor C dc values (see Fig. 6 but remains largely sinusoidal despite the massive dc-link voltage fluctuation U dc and the grid current THD results to 5.9%. It is important to highlight that E dc = 5.0 J is elevated compared to Fig. 9(b). Hence, this operating condition represents the maximum dc-link capacitor utilization, i.e., a small C dc (with a large voltage fluctuation U dc ) is sufficient to maintain PFC rectifier operation, and not the minimum energy buffering requirement. Despite this large dc-link voltage fluctuation U dc , the measured buffered energy E dc (with resistive loads) closely matches the calculated value (where isolated dc-dc converter stages with constant input power are considered) with a small deviation <5%.
When further lowering the average dc-link voltageŪ dc the minimally required dc-link capacitor value C dc increases again and Fig. 10(b) presents converter waveforms forŪ dc = 298 V and C dc = 120 μF, with E dc = 5.1 J. There, the dc-link voltage fluctuation U dc is reduced compared to Fig. 10(a) such that also the grid current quality is notably improved with a THD of 4.1%.
Last, Fig. 10(c) presents experimental waveforms close to the lower bound of feasible average dc-link voltage with U dc = 284 V where the dc-link capacitor values are increased again to C dc = 240 μF. There, the maximum dc-link voltage advantageously remains low with U dc,max < 320 V and E dc = 4.9 J. In closing it can be stated that the optimal CM modulation of Section II and the associated energy buffering savings and extreme operating conditions with minimum dc-link voltage and/or capacitance are successfully verified by the experimental results provided in this section.

V. CONCLUSION
The phase-modular isolated three-phase Power Factor Correction (PFC) ac-dc converter structure with individual isolated dc-dc converter stages presented in Fig. 1(a) advantageously facilitates the use of standard single-phase equipment and the low 400 V dc-link voltage level allows to use high performance 600 V semiconductors. The main drawback of this topology, however, is the fact that the time-varying singlephase input power only sums to a constant three-phase output power at the isolated dc output voltage, such that large dclink capacitor values are required. Therefore, recent literature proposes to reduce the dc-link energy buffering requirement E dc by means of a third-harmonic Common-Mode (CM) voltage injection modulation.
This article identifies the optimal CM voltage waveform with respect to minimizing E dc which results in a collaborative modulation where for a given point in time only two out of three phases operate with Pulse Width Modulation (PWM) while the third phase ceases switching. Further, optimal CM voltage modulation with reduced dc-link voltage levels and/or dc-link capacitance values is investigated. Experimental results with a 6 kW prototype system yield a reduction in E dc by up to 42% or, alternatively, operation with an average dclink voltage below 285 V, which closely match the theoretical considerations.

APPENDIX A IMPACT OF THE DC-LINK VOLTAGE ON THE OPTIMAL CM VOLTAGE TRAJECTORY
The analysis in Section II is limited toŪ dc = 400 V and this Appendix further provides the optimal CM voltage trajectories obtained with the method from Section II-B for different dc-link voltage levelsŪ dc = {300 V, 400 V, 500 V, 600 V}. Fig. 11(a) considersŪ dc = 300 V withŪ dc <Û ac such that the eligible LF CM voltage range according (7) does not allow for conventional modulation withū CM = 0 asū CM,max andū CM,min change signs during one fundamental period. Here, the optimal CM voltage trajectoryū CM,opt results in E dc = 4.6 J and corresponds to a DPWM strategy, where the switch-nodex of the phase x with the instantaneous middle absolute grid voltage value is clamped to the positive (if u x > 0) or negative (if u x < 0) dc-link rail [20], [21]. Hence, the same modulation strategy is optimal for bothŪ dc = 300 V and U dc = 400 V (shown in Fig. 11(b) for completeness) where the larger range of eligible CM voltages (7) withŪ dc = 400 V enables an improved energy buffering requirement of E dc = 3.6 J compared toŪ dc = 300 V with E dc = 4.6 J.
For a further increase in the dc-link voltage (Fig. 11(c) and (d)), the optimal CM voltage injection strategy changes, as the continuous clamping of the middle phase would overcompensate the instantaneous power pulsation, and E dc = 3.1 J and E dc = 3.0 J can be achieved forŪ dc = 500 V and U dc = 600 V, respectively, which is below the theoretically achievable limit for pure third-harmonic voltage injection modulation [14]. However, it is important to highlight that for U dc = 500 V andŪ dc = 600 V power semiconductors with a rated voltage > 600 V are required, thereby mitigating one of the main advantages of the converter concept such that these dc-link voltage levels are less of a practical interest.

APPENDIX B OPERATION IN UNBALANCED MAINS
The analysis in Section II is performed assuming an ideally symmetric three-phase grid. In case of a grid voltage imbalance the range of feasible LF CM voltages (7) (to satisfy the boost-type ac-dc converter voltage limit according to (6)) is altered and Fig. 12 presents the resulting maximumū CM,max  Fig. 4(a) for an unbalanced grid where the phase a voltage amplitudeÛ ac is decreased by 20%: grid voltages u a , u b , u c , ideally constant dc-link voltage U dc =Ū dc , LF PFC rectifier front-end input voltagesūāN,ūbN,ū¯cN, eligible LF CM voltage range (highlighted by a light gray area) limited byū CM,max andū CM,min according to (7), and optimal CM voltage waveformū CM . FIGURE 13. Phase-modular three-phase isolated PFC ac-dc converter system with a delta ( ) arrangement of the PFC rectifier front-ends [17] (with a typical average dc-link voltage level ofŪ dc = 700 V for a grid with 230 V rms line-to-neutral voltage): The LF CM current circulating inside the -connection (the current path is highlighted with a red dashed line) does not impact the grid currents and allows to alter the LF input power flows of the modules. and minimum CM voltageū CM,min for a 20% reduced voltage amplitudeÛ ac in phase a. Despite the grid voltage imbalance, the clamping strategy from II-C can be employed, where the resulting LF CM voltage waveformū CM is no longer 120 • symmetric.

APPENDIX C OPTIMAL CM CURRENT INJECTION MODULATION OF DELTA-CONNECTED PHASE-MODULAR ISOLATED THREE-PHASE PFC AC-DC CONVERTERS
It is important to highlight that the discussed optimal CM modulation strategy can also be employed to a delta ( ) arrangement of the PFC rectifier front-ends [17] where an LF CM currentī CM circulates between the modules (the CM current path is highlighted in Fig. 13) and thereby allows to redistribute the grid input power pulsation.
Here, the three module input currents iā, ib, ic are individually controlled and details on the required control structure can be found in [17]. Further, the dc-link voltages do not directly impose an upper bound for the LF CM current reference (as it is the case for the LF CM voltage reference with (7) for the star-connection of the modules in Fig. 1(a)). However, high values of the LF CM current amplitude are accompanied by additional conduction losses in the ac-dc front-end power semiconductors and boost inductors L (which are then also required to feature a higher saturation compared to conventional modulation withī CM = 0), such that the optimal LF CM current waveformī CM,opt cannot be identified a priori for a given grid voltage amplitude and dc-link voltage level (as it is the case for the star-connection of the modules in Fig. 1(a)), but needs to be assessed separately for each specific converter design.