Design of High-Frequency, High-Power Class $\Phi _{2}$ Inverter Through On-Resistance and Output Capacitance Loss Reduction in 650 V Parallel eGaN Transistors for Optimal Thermal Performance

This article presents a class <inline-formula><tex-math notation="LaTeX">$\Phi _{2}$</tex-math></inline-formula> inverters for high-power applications using multiple enhancement-mode gallium nitride (eGaN) switching devices operating at 13.56 MHz. The eGaN devices are beneficial in high-frequency, high-power applications such as plasma processing, thanks to the low switching and conduction losses. In addition, the small size of eGaN devices increases power density while reducing the impact of parasitic package components. However, their small package size makes it challenging to manage power dissipation, particularly at higher frequencies where additional conduction losses due to dynamic <inline-formula><tex-math notation="LaTeX">$R_{DS(on)}$</tex-math></inline-formula> and switching losses due to <inline-formula><tex-math notation="LaTeX">$C_{OSS}$</tex-math></inline-formula> can significantly increase power dissipation. To address these challenges, we investigate the individual contributions of dynamic <inline-formula><tex-math notation="LaTeX">$R_{DS(on)}$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$C_{OSS}$</tex-math></inline-formula> to power losses at high frequencies by paralleling multiple devices. We also propose criteria for selecting the optimum number of parallel eGaN devices to decrease power dissipation per device by reducing conduction losses greater than the addition in <inline-formula><tex-math notation="LaTeX">$C_{OSS}$</tex-math></inline-formula> losses. This approach helps to alleviate thermal stress in the devices. Finally, we demonstrate the effectiveness of our approach by designing a 1 kW single inverter and a 2 kW push-pull inverter at 13.56 MHz, which achieve over 90% drain efficiency while reducing thermal stress in the device.

Radio-frequency (RF) power amplifiers (or dc-to-ac power inverters) have been used in semiconductor manufacturing for plasma processing to operate at high frequency (HF: 3-30 MHz) and very high frequency (VHF: 30-300 MHz) while delivering over several hundred watts of output power [1]. For example, dc-to-ac resonant inverters are promising designs for these applications to achieve high efficiency at high frequencies thanks to their soft-switching properties. Among the resonant inverters, the class 2 inverter has the advantage of having a maximum drain voltage twice the input voltage and an easy-to-drive ground-referenced switching device [2], [3]. However, in high-power, high-frequency operation, even with the class 2 inverter, it is challenging to switch at MHz frequency due to high input capacitance C ISS and achieve high inverter efficiency owing to the high on-resistance R DS(on) of silicon (Si) MOSFETs.
Recently, state-of-the-art wide bandgap devices, such as enhancement mode gallium nitride (eGaN) transistors, extend the limit on size, switching frequency, and efficiency in the resonant inverters while operating them under high-voltage, high-power conditions [4]. Specifically, eGaN FETs operate efficiently at high frequencies due to their lower C ISS and R DS(on) values. In addition, eGaN FETs are smaller than Si and SiC devices of comparable ratings, resulting in higher power density. However, the small package and low thermal conductivity of the eGaN transistors limit their thermal performance at HF and VHF. For example, a class 2 inverter designed at 40.68 MHz and 1 kW power showed simulated power loss of over 26 W in a single eGaN transistor [5]. Moreover, eGaN transistors in the high-frequency range exhibit significantly more conduction losses due to dynamic on-resistance R DS(on) than their nominal low-frequency resistance [6], [7], [8], [9]. A dynamic on-resistance originates due to trapped charges and results in higher channel resistance, which increases with the voltage across the device during offstate and with the device's temperature [10], [11], [12], [13].
To overcome the challenges of managing power dissipation and thermal performance in eGaN devices, multiple eGaN FETs are connected in parallel, offering several advantages. First, a positive temperature coefficient of R DS(on) and a negative temperature coefficient of device trans-conductance g m in the devices result in thermal balance among the paralleled devices. Secondly, the devices have a stable gate-source threshold voltage over temperature, reducing variations in the current sharing between the paralleled devices [14], [15]. In addition, the unique packaging of eGaN FETs improves the paralleling performance by lowering its source inductance even with commercially available packaged devices. Lastly, since paralleling devices reduce effective device ON resistance, the power losses due to a dynamic on-resistance R DS(on) are reduced due to paralleling. Therefore, paralleling multiple eGaN FETs in a resonant inverter is beneficial to maximize the performance of eGaN FETs for high-power, high-frequency operation.
Previous studies have investigated the parallel operation of eGaN transistors to increase the power handling capability of a power converter by reducing the temperature of the individual eGaN transistor. In [16], an isolated full-bridge dc-dc converter with four eGaN transistors using optimal PCB design was presented to provide an output power of 2.4 kW at 50 kHz. Similarly, the improvement in the power converter's electrical efficiency and decrease in the maximum temperature of the eGaN transistors were demonstrated for 480 W of output power at 300 kHz in a buck converter in [17]. The study also highlighted that differences in the source inductance of parallel eGaN transistors could affect their dynamic current sharing. On the other hand, current balancing using coupled inductors was investigated among four eGaN switches in parallel in 1 MHz, 250 W resonant class-E dc-dc converter [18].
However, most research on parallel devices and current sharing focuses on low frequencies, typically much lower than 10's of MHz, and are limited to hard-switched pulse width modulated (PWM) converters. Also, while determining the number of parallel devices, these studies did not consider power losses due to the phenomenons that manifest at high frequencies, such as dynamic R DS(on) and losses due to parasitic device output capacitance C OSS . In the HF and VHF operations, C OSS , a voltage-dependent non-linear output capacitance of the eGaN device, is not lossless [19], [20]. C OSS incurs losses during charging and discharging at high frequencies, and these losses increase with a value of C OSS , magnitude, and a rate of change of voltage across the transistor and switching frequency [21], [22]. Therefore, resonant converters incur C OSS related losses despite negligible switching losses due to zero voltage switching (ZVS).
In addition, the ratio between losses caused by C OSS and dynamic on-resistance R DS(on) in eGaN devices is crucial for determining what device can be paralleled as well as the number of parallel devices to use. Prior studies connected the OFF device to the operating device in parallel to split losses from C OSS and dynamic on-resistance R DS(on) at high frequencies [19], [23]. However, assessing a device's OFF-state losses can be challenging due to a thermal coupling between the switching device and the OFF device caused by a temperature gradient, as reported in previous studies [21]. These high-frequency losses, dynamic R DS(on) and C OSS , motivate our work to investigate and optimize the use of parallel eGaN transistors in high-frequency, high-power class 2 inverters.
This article, an extension of our conference article [24], proposes parallel devices to investigate and separate losses due to R DS(on) and C OSS . We also propose criteria for the optimal number of parallel eGaN transistors at 13.56 MHz to keep C OSS losses with the addition of parallel devices below conduction losses, including a dynamic on-resistance R DS(on) . Additionally, we implement a push-pull class 2 inverter with an optimal number of parallel eGaN transistors to deliver 2 kW power output without any matching network, unlike equivalent parallel inverters for plasma processing at 13.56 MHz. For current sharing, the transistors are placed symmetrically with short loop lengths on the circuit board to reduce the parasitic inductance. Since it is challenging to measure power losses or current through eGaN transistors at high frequencies without introducing parasitic impedance, we use infrared imaging to demonstrate the reduction in power loss across each transistor achieved through paralleling. Section II describes the design methodology for a class 2 inverter with a single device and multiple devices. Section III explains power losses in an eGaN transistor, the method to estimate C OSS and R DS(on) losses, and parallel device selection criteria. Section IV illustrates the experimental results of the class 2 inverter and push-pull inverter with single and multiple parallel devices. Finally, Section V concludes the article.

A. SINGLE DEVICE CLASS 2 INVERTER
A class 2 inverter must be designed with a single device before paralleling multiple devices. Thanks to a finite DCinput inductance L F , the inverter, shown in Fig. 1(a), reduces its sensitivity to load variation. Also, the ground-referenced switching device Q experiences low voltage stress of twice the input voltage with a series resonance formed by L MR and C MR at a second harmonic frequency. The capacitor C S is the DC blocking capacitor and L S acts as an impedance divider to control the amount of AC power at the output. C P is the external capacitance in addition to device output capacitance C OSS . The impedance at the drain-to-source Z DS , as illustrated  in Fig. 2, is shaped using the following empirical criteria to achieve zero-voltage switching (ZVS) and zero-dv/dt switching (ZVDS) [2]: i) A near zero drain-source impedance at the second harmonic (27.12 MHz) of the switching frequency. ii) At the fundamental frequency, the phase of drainsource impedance is between 30 • and 60 • inductive. In addition, the phase of drain-source impedance at the third harmonic (40.68 MHz) is capacitive. iii) A 4 to 8 dB ratio between the fundamental and third harmonic to lower the maximum drain-source voltage. The design process aims to select the circuit components for the class 2 inverter with design specifications of input voltage V IN , output power P OU T , switching frequency f s , and load R LOAD . First, the circuit components C MR and L MR are selected with the least possible value for C MR , which satisfies the criteria (i) mentioned above. The maximum voltage across C MR , which is related to the capacitor's voltage rating, is the primary constraint that dictates the lower limit of C MR selection. The C S is a large DC blocking capacitor, and L S is selected using an equation in [3]: Next, an iterative process is used to determine L F , starting with selecting any real number for σ in the range, such as 0 < σ < 2. Once the σ value is selected between 0 and 2 and C P + C OSS is chosen to satisfy the number of parallel devices requirements, then L F can be determined based on (2): Finally, with designed values of L F and C P + C OSS , the Z DS is checked to verify if it meets the criteria (ii) and (iii) mentioned earlier. If it fails to meet the criteria, a new σ value is selected, and this process to determine L F is repeated until criteria (ii) and (iii) for the Z DS are met. If the σ value is close to 2, even though peak voltage across the switching device is reduced, it increases circulating current, which reduces efficiency. Therefore, we have set the σ value to closer to one in our design.

B. MULTIPLE DEVICES CLASS 2 INVERTER
Assume multiple devices Q 1 to Q N in parallel are in the class 2 inverter, as seen in Fig. 1(b). Except for C P , all component values remain the same as in single device class 2 . With the addition of the switching device, C P is adjusted (decreased) to accommodate the increase in the device's output capacitance, C OSS . However, due to the non-linear (voltagedependent) nature of the device's capacitance C OSS and the linear (voltage-independent) nature of the external capacitance C P , adjustments to C P are made until ZVS is achieved, rather than until (an increase in) C OSS and (a decrease in) C P are equal. Consequently, as depicted in Fig. 2, the inverter's effective Z DS decreases when more switching devices are added in parallel.
The switching device's output capacitance C OSS is nonlinear and varies with the drain-source voltage across the switching device such that the value of C OSS is the highest at 0 V and decreases as the voltage across it increases up certain voltage after which it does not change noticeably. To estimate this voltage-dependent C OSS value of a single switching device, we approximated class 2 resonant inverter drain-source waveform in three intervals as shown in Fig. 3. At intervals I and III, C OSS has the highest value (C OSS@0 V ), while at interval II, C OSS has the lower value (C OSS@2V IN ). These values of C OSS at different voltages can be obtained from the device manufacturer's datasheet. The equivalent capacitance C OSS contributed by a single device during switch-off duration is a weighted sum of these minimum and maximum capacitances, with each capacitance value multiplied by the proportion of the total waveform period that the corresponding voltage exists as given by (3), where D is the duty ratio of the class 2 inverter when the switching device is ON and δ 1 and δ 2 are intervals for which drain-source waveform is approximated to zero. The durations of δ 1 and δ 2 are measured between zero voltage and a voltage, for which C OSS value does not change significantly. The estimated C OSS from (3) serves as an initial guess in LTspice simulation, allowing us to iteratively reduce C P with the addition of each device until ZVS is attained in the simulation with the addition of each parallel device.
As C OSS depends on the voltage and the switch-off duration (and thereby on duty ratio D), higher input voltage and lower D result in minimum C OSS allowing maximum parallel devices. Since the duty ratio, D, is fixed in the class 2 inverter, the inverter's input voltage V IN is an important parameter that decides the maximum number of devices that can be paralleled.

C. PUSH-PULL CLASS 2 INVERTER WITH MULTIPLE DEVICES
To achieve higher power, we selected the push-pull class 2 inverter topology because it uses two single class 2 inverters to provide power to load without any matching network while providing high efficiency. Suppose the exact power requirement has to be delivered by parallel inverters or a single highpower inverter. In that case, the system requires a relatively lower R LOAD value for the same output power. Therefore, a matching network is required to match the typically used 50 RF load. However, the matching network significantly reduces efficiency and bandwidth, which is unfavorable, especially in high-power, high-frequency applications. Moreover, unlike parallel class 2 inverters, a push-pull inverter is less sensitive to the mismatch of the two class 2 inverters caused by the component tolerance, phase shift between gate driving signal, or parasitic effects. Additionally, in the push-pull inverter, the ripple frequency is doubled at the input side, reducing input filter size and improving the electromagnetic interference (EMI) performance [25], [26], [27].
It is also true that in typical RF plasma drive and generation applications, especially for semiconductor fabrication processes, the plasma drive-point impedance can vary dramatically, diverging both in resistance and reactance from the 50 standard [28], [29]. Nonetheless, with the ability to accommodate large load impedance variations, the proposed design could serve as an important building block of future high-efficiency direct-drive systems for RF plasma applications.
Therefore, we design a push-pull class 2 inverter with multiple switching devices to meet the higher power requirements of the plasma processing application at 13.56 MHz while reducing power dissipation across each transistor. A push-pull class 2 topology consisting of two class 2 inverters with a 180 • phase difference between them, and their output connected to the 50 RF load, as shown in Fig. 4. If C OSS losses are maintained lower than the conduction losses with the parallel eGaN devices, we can obtain high power with high efficiency with the multiple eGaN devices as described in Section III.

III. POWER LOSS ANALYSIS AND OPTIMIZATION
To select the number of paralleled eGaN FETs in the class 2 inverter, we analyze the power losses, select appropriate eGaN devices and optimize the number of devices.

A. LOSSES IN EGAN DEVICES
The losses in the eGaN device consist of the conduction loss, including the dynamic R DS(on) loss, and switching loss comprising of C OSS related loss.

1) CONDUCTION LOSS (R DS(on) )
When the switching device is ON, the current flowing through it dissipates power in its DC ON-resistance R DS(on) reported in the datasheet. However, at HFs, the effective R DS(on) , referred to as dynamic R DS(on) , is found to be as high as five times its low-frequency resistance caused by the peak device voltage during turn-off state due to charge trapping [10], [11]. According to indirect measurement method [11], in GS66504B eGaN transistor, a five times increase in dynamic R DS(on) occurs at HFs as compared to static R DS(on) value mentioned in the datasheet. Moreover, recent direct measurements revealed a similar increase in R DS(on) value of GS66504B eGaN transistor [13]. To reduce the effect of dynamic ON-resistance, we parallel multiple transistors to decrease the power loss and device temperature. This conduction loss P R DS(on) Loss in the device ON-resistance R DS(on) due to the RMS value of the current flowing through the switching device i s (ωt ) is calculated as [30]: where It shows a decrease in conduction losses with a number of parallel transistors for a single class 2 inverter at 13.56 MHz.

2) SWITCHING LOSS (C OSS )
As a result of the ZVS, a switching device dissipates little power during the turn-on transition. Also, the loss due to parasitic inductance can be neglected. Therefore, turn-on and turn-off transition losses are negligible. However, the off-state losses account for most switching losses which occur in the process of charging C OSS until the voltage across the switch reaches a peak value of 2V IN and discharging when the voltage across the switch reduces to a zero from 2V IN just before the turn-on. At HF, these losses in the parasitic capacitance of transistor C OSS are significant and increase with a frequency and voltage change rate across the transistor, compared to SiC devices [22], [31]. Moreover, this voltage change rate is significantly influenced by total non-linear device capacitance C OSS [32]. As the number of paralleled eGaN FETs increase, C OSS becomes more significant, resulting in greater power dissipation, as shown in Fig. 5.

B. ESTIMATION OF C OSS AND R DS(ON) LOSSES
Since it is challenging to measure the dynamic R DS(on) at high frequencies, their contribution to power losses at high frequencies is difficult to be found. However, by paralleling multiple devices, the contribution of dynamic R DS(on) and C OSS losses can be measured as follows. It should be noted that this method assumes that losses due to P Cond and P C OSS are equal in parallel N devices. In addition, the accuracy of this method is limited by the precision of infrared thermal imaging.
First, we measure the temperature of the single device in a class 2 inverter. To estimate power loss associated with this temperature, we passed DC current through the eGaN device by keeping the eGaN device ON until the device temperature matches the device's temperature in a class 2 inverter. Then, we note down power loss P Loss1 across the eGaN device by measuring its voltage and computing V × I. This power dissipation is primarily composed of conduction losses P Cond , including dynamic R DS(on) and switching losses P C OSS due to C OSS : Next, we parallel N identical devices and measure the temperature of the individual device in a class 2 inverter. To estimate power loss associated with this temperature, we again DC bias the devices until the device temperature matches the temperature of the devices in a class 2 inverter. Then, we note down total power loss P Loss2 across the eGaN device by measuring voltage and computing V × I and express it as: Lastly, we determine P Cond and P C OSS across the eGaN device by solving (6) and (7) simultaneously. The individual contribution of P Cond and P C OSS is essential to select the appropriate device and determining optimum parallel devices for high power at high frequencies, as explained in the next section.

C. DEVICE SELECTION CRITERIA AND OPTIMIZATION
With the dynamic R DS(on) and C OSS losses, it is essential to select appropriate eGaN devices for parallel operation. First, we analyze R DS(on) and C OSS and classify them, as shown in Fig. 6. Those devices with lower R DS(on) and higher C OSS are suitable as a single switching device because they do not gain much in terms of reduction in the conduction losses by paralleling. However, as devices are added in parallel, they incur higher switching losses due to lossy C OSS . On the other hand, devices with higher R DS(on) and lower C OSS are proper candidates for paralleling as a decrease in the conduction loss is significant as compared to an increase in the switching loss.
After selecting the device, the number of parallel devices (N) has to be chosen to decrease conduction losses. The decrease in total conduction loss P Cond and increase in total switching loss P C OSS due to C OSS for N parallel devices are given by (8) and (9). where k, α, and β are the parameters in the Steinmetz equation obtained empirically in [22], and i sw_RMS is the RMS value of the switching current. For paralleling of devices to be beneficial, the total decrease in conduction loss P Cond has to be higher than the total increase in switching loss P C OSS , as shown below.
(10) Therefore, N is determined by calculating the ratio of the single device's conduction losses P Cond and switching losses P C OSS : We simulated two different eGaN FETs, as shown in Fig. 6, and determined N by using only single device conduction and switching loss in the class 2 inverter. The losses related to C OSS and dynamic R DS(on) are obtained from experimental data in [22], [31] and [11]. As seen in Fig. 6, GS66504B performs better in terms of paralleling as compared to GS66508T with two parallel devices since it has half the C OSS and double R DS(on) than GS66508T. In addition, to absorb C OSS from the paralleled devices, the class 2 inverter needs to minimize equivalent capacitance C E at the fundamental frequency contributed by L MR and C MR . L MR and C MR resonate at the second-harmonic frequency to eliminate the second-harmonic component in the voltage across the drain-to-source. In order to reduce C E , it is beneficial to increase the ratio of L MR to C MR within the feasibility of implementation. This higher ratio of L MR to C MR is achieved by reducing C MR and increasing L MR by a scaling factor of γ , which lies between 0 and 1 to obtain a reduced equivalent capacitance C E at the fundamental frequency of 13.56 MHz as:

D. SIMULATION RESULTS OF CLASS 2 INVERTER
We utilized LTspice to simulate the class 2 inverters with the circuit parameters determined using the methods described in Section II-A. We simulated the designed class 2 inverter with single and multiple devices for for V IN = 250 V , D of 25%, P OU T = 1 kW , R LOAD = 25 , and f s = 13.56 MHz. Multiple devices were added by reducing the external capacitance C P by C OSS until ZVS is achieved. Two different eGaN FETs − GS66508T and GS66504B, were used for the simulation, for which LTspice simulation results are shown in Table 1. The manufacturer provided a spice model for the GS66508T, and GS66504B eGaN transistors were utilized in the simulated circuit. In the case of GS66508T, we observe a considerable advantage in reducing device loss from one to two devices, but there is no considerable advantage above two parallel devices. Paralleling more than two devices has reduced advantages because with three parallel devices, although power loss per device decreases, total power loss across three devices is more than the total power loss due to two devices in parallel. On the other hand, compared to the GS66508T device, the GS66504B device, which has half the output capacitance C OSS and twice the value of ON resistance R DS(on) of the GS66508T, the reduction of conduction losses is significant. Therefore, GS66504B shows a better trend regarding maximum parallel devices than the GS66508T.
However, the LTspice simulation results in Table 1 with spice models of GS66508T and GS66504B devices do not capture dynamic R DS(on) and C OSS losses due to the high-frequency phenomenons, which have to be determined through experiments. In [11], dynamic R DS(on) related losses in GS66504B eGaN transistor at 3 MHz have experimentally estimated as high as five times static R DS(on) . In addition, C OSS related losses were experimentally estimated at around 7.6 W for the GS66508T device and 3.8 W for the GS66504B devices in [22], [31]. However, these losses due to dynamic R DS(on) and C OSS vary non-linear with the voltage across the device, rate of change of voltage, and temperature.
Since the advantage of paralleling devices depends on whether the increase in switching loss due to C OSS is lower than the decrease in the conduction loss due to R DS(on) , we investigated and separated these losses for GS66508T and GS66504B to determine an optimal number of parallel devices in experiments as described in the next section.

A. EXPERIMENTAL RESULTS OF A CLASS 2 INVERTER
Prototypes of the class 2 inverter were constructed using single and two eGaN transistors of GS66508T and GS66504B. The circuit boards used for the prototypes are shown in Fig. 7(a) and (b), and the components used are listed in Table 2. The prototypes were tested with two parallel 50 RF loads, as shown in Fig. 7(c), and the power loss distribution was determined by using a FLIR A655sc infrared camera to measure the case temperature of the devices at steadystate [33].
The printed circuit board design was optimized to ensure current sharing among paralleled transistors. Parallel transistors can perform unevenly in terms of thermal performance due to unequal current sharing during transients and steady states, limiting the benefits of parallel transistors. Therefore, the eGaN transistors were arranged in a single row and driven with separate gate drivers ISL55110 and 1 gate resistors to minimize and equalize gate loop length in the design. We constructed the inductors using a 3-D printed support structure (air cores) and 12 AWG copper wire in a toroidal shape with a quality factor of roughly 150 measured at 13.56 MHz. This quality factor of the air-core inductors, L F , L MR , and L S , was determined by using a Keysight vector network analyzer (VNA) E5061B. Fig. 9 illustrates the ZVS in the drain-source voltages of the inverters with GS66508T and GS66504B. The variations in the waveform shape depicted in Fig. 9 are attributed to the differences in the contribution of device voltage-dependent capacitance C OSS and external voltage-independent capacitance C P to total capacitance C OSS + C P . The output power and efficiency obtained with single and two transistors class 2 inverters are presented in Fig. 10. The increase in output power from one device to two devices inverter is attributed to the greater contribution of the non-linear voltage-dependent capacitor C OSS from the two devices. Notably, the efficiency of the two-device inverter is higher than the single-device inverter, indicating that conduction losses due to R DS(on) are more significant than those due to C OSS . Furthermore, the experimental efficiencies were lower than the simulated values in Table 1, due to the effects of dynamic R DS(on) and C OSS captured in experiments.
We investigated the thermal performance of single and two-device class 2 inverters and separated losses using the method described in Section III-B. Fig. 8 shows the steadystate temperatures measured with single and two devices inverters. The decrease in conduction losses in GS66508T compared to C OSS gives N of nearly two by (11) as represented in Fig. 10. Increasing the number of parallel devices beyond this point results in higher switching losses that exceed the reduction in conduction losses. On the other hand, N is greater than two for GS66504B. However, in this study, we limited our experiments up to two parallel GS66504B devices as this study mainly focuses on showing how larger R DS(on) GS66504B devices are better when it comes to paralleling  than small R DS(on) GS66508T devices at 13.56 MHz. This result demonstrates that a single device operation is suitable for lower R DS(on) and therefore higher C OSS devices such as GS66508T, while the parallel operation is more efficient for higher R DS(on) and lower C OSS devices like GS66504B at 13.56 MHz, as illustrated in Fig. 6. Given that the gating loss, given by the C ISS V 2 GAT E f , is minimal − approximately 0.1 W per GS66508T device and 0.05 W per GS66504B device with a gate voltage V GAT E of 6 V, it has not been included in the efficiency calculations.
As compared to the LTspice simulation results presented in Table 1, experimental results in Fig. 10 show an increase in efficiency with parallel devices. This discrepancy arises because the LTspice device model does not account for dynamic R DS(on) or C OSS -related power losses that are observed in experiments. These power losses are as high as ten times than those predicted by LTspice. Consequently, while the LTspice results show device losses of around 5 W, which do not significantly affect efficiency due to the paralleling of devices, experiments reveal much higher device losses than those predicted by LTspice or the device datasheet leading to a significant improvement in efficiency as seen with parallel devices in Fig. 10.
The GS6650x series devices we studied are paralleled versions of each other at the die level. In the results in Fig. 10, we noticed that two GS66504B devices exhibited lower losses than one GS66508T device, despite having similar die areas. Our hypothesis for this observation is that it might be due to a lower operating temperature and device area, as seen in Figs. 8 and 10, respectively, along with potential influences of fringing effects associated with device structure components such as field plates, the two-dimensional electron gas (2DEG) channel width, and packaging. This indeed constitutes an area that warrants further investigation, and we plan to delve into this in our future work.

B. EXPERIMENTAL RESULTS OF PUSH-PULL CLASS 2 INVERTER
Building on the findings from the previous section, which determined that the optimal number of parallel devices for a class 2 inverter with an output power of 1 kW is two, we constructed a push-pull class 2 inverter prototype capable of delivering even higher power of 2 kW. We used the optimal number of two parallel devices for each switch in the pushpull design. The prototype for the push-pull inverter board and the separate gate driving board, as shown in Fig. 11(a). The GS66508T transistors were mounted on the bottom side of the circuit board. The push-pull inverter's drain-source voltage waveform shown in Fig. 11(b) is symmetrical, which is crucial for its drain efficiency. This push-pull inverter consisting of two parallel switching devices delivered 2.3 kW output power at 13.56 MHz with 93.5% drain efficiency.

V. CONCLUSION
This article presents a high-frequency class 2 inverter design through R DS(on) and C OSS loss reduction in 650 V parallel eGaN transistors for optimal thermal performance. The use of eGaN transistors, with their low C OSS and R DS(on) characteristics and high power density, is a promising technology for high-power and high-frequency applications. However, high-frequency phenomena such as dynamic R DS(on) and lossy C OSS significantly increase power dissipation which is challenging to manage in the eGaN device's small packaging. Unlike low-frequency operation, paralleling low R DS(on) devices is disadvantageous at high frequencies due to increased C OSS with the addition of parallel devices. Therefore, we determine the optimum number of parallel eGaN devices based on estimating loss in a single device due to R DS(on) and C OSS . We tested a class 2 inverter at 13.56 MHz with up to two devices in parallel for 1 kW of output power and observed the thermal characteristics. The results show that increasing the number of paralleled devices is advantageous as long as the increase in losses due to added C OSS does not nullify a decrease in R DS(on) losses. The results obtained with GS66504B and GS66508T demonstrated that a single device operation is suitable for lower R DS(on) and, therefore, higher C OSS devices such as GS66508T. In contrast, the parallel operation is more efficient for higher R DS(on) and lower C OSS devices like GS66504B. Since two eGaN devices were optimal at an input voltage of 250 V and frequency of 13.56 MHz, we implemented a push-pull inverter consisting of two parallel switching devices, which delivered 2.3 kW output power at 13.56 MHz with 93.5% efficiency.