A PCB-Embedded 1.2 kV SiC MOSFET Package With Reduced Manufacturing Complexity

This article presents a printed circuit board (PCB) -embedded 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) half-bridge package for a 22 kW electric vehicle (EV) on-board charger (OBC). The package meets the application's thermal and electrical requirements while eliminating or reducing factors that drive up manufacturing complexity and footprint in PCBs. Factors such as integration necessity, trace width, and layer count are considered. The package has been prototyped and subjected to electrical and thermal characterization. Static characterization performed on the package prototypes has revealed that the package contributes approximately 0.4 mΩ of parasitic resistance to the power loop. The simulated minimum power-loop and gate-loop inductances of the final package are 2.4 nH and 1.6 nH, respectively. Double pulse tests (DPTs) performed on the final package at 800 V and 25 A revealed that the low loop inductances allow the high-side and low-side switches to achieve 41 V/ns and 37 V/ns turn-off dv/dts, respectively, with drain-to-source voltage (VDS) overshoots of 34 V and 30 V, respectively. The selection of a non-isolated case, along with other design choices, has helped limit the junction-to-case thermal resistance (RTH,JC) of each MOSFET to 0.074 K/W.


I. INTRODUCTION
Power electronics research has focused on improving power density, efficiency, and integration since the advent of the field [1]. As one of the most important components in power electronic systems, semiconductors have played an important role. The Baliga figure of merit, published in 1982, predicted that wide-bandgap (WBG) semiconductors-silicon carbide (SiC) in particular-would overtake his own invention, the silicon (Si) insulated gate bipolar transistor (IGBT) [2], [3]. Using his figure of merit, Baliga concluded that SiC devices would have lower conduction losses per unit breakdown voltage and would switch faster than their Si counterparts. Those facts combined with the high thermal conductivity and maximum operating temperature of SiC mean that SiC devices can operate at higher frequencies than Si, allowing for smaller capacitors and magnetics that result in higher power densities [4].
With such promising predicted performance metrics, it comes as no surprise that bare SiC switching devices were made commercially available in 2006 and packaged devices appeared shortly thereafter [5]. Some of these first packages adopted technology developed for packaging Si to accelerate commercial availability. This approach is attractive because it allows old package manufacturing procedures and power converter designs to be recycled, reducing the cost of adopting the new and improved semiconductors. One example is the TO-247 package seen in Fig. 1, which includes some of the components that commonly raise concerns about directly substituting SiC devices into Si packages: wire bonds and lead terminals. Wire bonds and lead terminals contribute to high loop inductances that can limit the electrical performance advantage that SiC devices are intended to offer [6], [7]. Even in Si packages, wire bonds are also responsible for three of the common failure mechanisms in the packages that contain them: interconnect corrosion, wire-bond heel cracking, and wire-bond lift-off [8].
The on-board chargers (OBCs) in electric vehicles (EVs) are one example of an application that would benefit from the adoption of SiC devices. Through its "EV Everywhere Grand Challenge," the U.S. Department of Energy (DOE) listed OBC cost, power density, and peak efficiency targets of 35 $/kW, 4.6 kW/L, and 98%, respectively, that should be reached by 2025 [9]. For reference, the leading commercially available OBCs have a 2 kW/L power density [10] and a 96% peak efficiency [11]. The use of WBG semiconductors is the only way to meet such aggressive targets. As part of the U.S. DOE grand challenge, the electrical and electronics tech team developed a roadmap that identified packaging structures and materials as two of the major technical barriers to meeting the necessary targets, coming to the same conclusions made in the last paragraph [12].
The EV industry requires cost-competitive components that meet rigorous automotive standards such as the AEC-Q101 [13], so solutions proposed to meet the U.S. DOE's targets would ideally use low-cost, mature technologies. Printed circuit board (PCB) embedding has been identified as a promising technology for automotive power semiconductor packaging because-unlike other advanced packaging technologies-it is based on an inexpensive, mature technology and offers the possibility of sufficient electrical and thermal performance [14]. Due to these merits, researchers have invested significant effort to make PCB embedding a commercially viable technology.
Huesgen [15] provides an extensive review on different PCB-embedding techniques, alternative materials, demonstrators for a variety of applications, and promising reliability results, all of which aid in the advancement and adoption of PCB embedding; however, much of the literature focuses on demonstrating and characterizing a novel PCB-embedded package architecture or subjecting a PCB-embedded package to tests previously unexplored in literature [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34]. Literature that provides more extensive detail about the tradeoffs considered in the package design procedure tends to explore non-universal aspects, such as the relationship between thermal conductivity and via density for dual-sided die attach [35], the impact of lead frame geometry on thermal and thermomechanical performance [36], the thermal performance provided by alternative top-side die-attach methods [37], or the thermomechanical performance of alternative dielectric materials [38], [39]. In [40], more extensive information was provided about how certain dimensions were chosen to achieve good thermal performance while minimizing problematic parasitics. However, no consideration was given to how the design choices in [35], [36], [37], [38], [39], [40] impacted cost. In [41], dieintegrated PCB packages are proposed as an alternative to PCB-embedded packages to reduce costs. While this may be a good solution, the focus was on adjusting the fabrication method instead of investigating how package design choices impact the cost of PCB-embedded packages.
Unfortunately, it is difficult to determine how the cost of research-level packages will scale to mass production. However, manufacturing complexity and footprint are known to impact PCB cost [42]. Although [42] was published in 1995, PCB manufacturing was a mature technology at the time and the processes that drive cost have remained relatively unchanged. For example, using the default settings in a PCBway's online quote calculator, the cost of quantity 1000 PCBs with dimensions of 5 mm by 5 mm and 10 mm by 10 mm are $126.9 and $134.87, respectively [43]. Similarly, if the same 5 mm by 5 mm PCB is quoted to have four layers-instead of the default two layers-the price increases to $162.37 [43].
For that reason, the PCB-embedded 1.2 kV SiC MOSFET half-bridge package designed in this article targets minimized manufacturing complexity and footprint while meeting the electrical and thermal performance necessary to operate in a high-power-density 22 kW OBC. More specifically, the electrothermal viability, manufacturing complexity, and footprint size of alternative package designs with varying levels of gate-and power-loop component integration, layer counts, and trace widths were evaluated. The relative manufacturing complexity of each design alternative was determined using factors that drive up manufacturing complexity in standard PCBs, such as layer and via counts [42]. To the best of the authors' knowledge, this is the first attempt to explore the impact of package design choices on manufacturing complexity and footprint size of PCB-embedded packages for the purpose of cost reduction. Although the package designed in this work targets a 22 kW OBC, the conclusions drawn about the impact of design choices on manufacturing complexity and footprint size of PCB-embedded packages will aid in the design of PCB-embedded packages for other applications.
The final package is electrically and thermally characterized to verify that it meets the needs of the application. Static electrical characterization, double pulse tests (DPTs), and a continuous switching test are used to verify the electrical performance. The junction-to-case thermal resistance (R TH,JC ) is measured to support the claim that the package meets the thermal requirements of the OBC.

II. PCB-EMBEDDED HALF-BRIDGE PACKAGE DESIGN
The design of this package was performed after the work presented in [33], [34], which saw the successful design and implementation of a PCB-embedded 1.2 kV SiC MOSFET half-bridge package with integrated gate-drive and powerloop circuitry in a 22 kW ac-dc converter. Although the previous work ended with a satisfactory result, the design, assembly, and testing phases revealed many areas for improvement such as efficiency, manufacturing complexity, and footprint. The flow chart seen in Fig. 2 depicts how design alternatives were compared based on their electrothermal viability, manufacturing complexity, and footprint size.

A. INITIAL POWER STAGE
An initial power stage design is required to act as a jumpingoff point, from which improvements can be made. To arrive at the initial power stage design seen in Fig. 3, a process like that found in [33], [34] was used. The via-to-via pitch, via diameter, and via pad diameter were again chosen to be 0.44 mm, 0.14 mm and 0.35 mm, respectively, based on the guidance provided in the literature [44] and manufacturing limitations. The trace widths and spacings were again chosen according to the IPC-2221B standard and associated calculators [45], [46], [47]. A similar philosophy helped determine the SiC MOSFET die and decoupling capacitor locations. Finally, the same embedding process from AT&S was selected including the same high glass transition temperature (>250°C) FR4.
There are, however, some major differences between the initial power stage design presented here and that in [33], [34]. A series of critical-conduction-mode (CRM) boost converter tests performed on the package in [33], [34] revealed that the header pins of each package contribute a non-negligible 5-7 m to the power loop [34]. To eliminate the parasitic resistance contribution from the terminals, the initial power stage presented here uses pads to form surface-mount terminals instead of header pins. Switching from through-hole header pins to surface-mount pads also provides flexibility in terminal placement that results in a more symmetrical power stage. The surface mount pads also allow the package to be mounted to the motherboard during the same soldering step as other components on the motherboard, so no additional assembly steps are required to mount the package. The second major difference between the two designs is the thickness of the copper layers. Here, all four layers are composed of 2 oz copper. Thicker copper was selected in [33], [34] to provide additional thermal spreading but the benefit was minor. Lower copper weight results in a thinner PCB.
The downside of using surface-mount terminals is that direct dual-sided cooling of the package is no longer possible; however, the PCB-embedded package presented in prior work has a 39% lower drain-side R TH,JC than a TO-247 package, and six of them were demonstrated in an ac-dc converter up to 25 kW with exclusively drain-sided cooling [33], [34]. As seen in Fig. 3, the solder mask openings used for heat sink attachment are placed on the drain side, and the terminal pads are placed on the source side, since drain-side cooling has proven to be more effective than source-sided cooling [33].

B. GATE DRIVE INTEGRATION INVESTIGATION
With the initial power stage design complete, the next step is to select the gate-drive circuitry and determine whether it is necessary to integrate it into the SiC MOSFET package. The gate-drive circuitry described in [34] was chosen because it has already proven itself effective for the application. Fig. 4 shows the two possible combinations of the gate-drive circuitry and initial power stage described in Section A. The Fig. 4(a) option has gate-drive circuitry external to the package, while the Fig. 4(b) option is a single PCB with embedded die and integrated gate-drive circuitry.

TABLE 1 Tabular Comparison of Gate-Drive Circuitry Options
Analyzing the options seen in Fig. 4 helped determine whether to integrate the gate-drive circuitry into the package. Table 1 provides tabular results of this analysis. Included are the gate-loop inductances (L GL s) extracted using ANSYS Q3D-Extractor, the dimensions of the PCB containing the embedded die, and qualitative advantages of each design.
Integrating the gate-drive circuitry into the package does improve the L GL ; however, the improvement is not drastic enough to significantly impact the switching behavior of the SiC MOSFETs in this application. Packages with integrated gate drive circuitry are attractive because they require less design work for the customer. In contrast, external gate-drive circuitry allows for changes to the circuitry after the package is fabricated, offering benefits such as supply chain robustness in case an IC becomes unavailable and flexibility if greater functionality is needed in the gate drive circuitry. The external gate drive circuitry option also reduces the footprint size of the package. Therefore, the package will not contain integrated gate-drive circuitry to reduce the footprint size and allow for adaptability of the gate drive circuitry for future designs.

C. DECOUPLING CAPACITOR INTEGRATION INVESTIGATION
The necessity of integrating the decoupling capacitors into the package is also investigated. The power-loop inductance (L PL ) of the initial power stage design (depicted schematically in Fig. 5(a) and seen in Fig. 5(b)) and a version with external decoupling capacitors placed on the opposite side of the motherboard from the package (depicted schematically in Fig. 6(a) and seen in Fig. 6(b)) are evaluated using ANSYS Q3D-Extractor. For this analysis, only the section of the motherboard with the decoupling capacitor circuitry is included in the model. The final motherboard design will also include additional circuitry required by the converter. The simulated  L PL of the initial power stage is 2.0 nH at 10 MHz, and the simulated L PL of the version with external decoupling capacitors is 2.1 nH at 10 MHz. A 0.1 nH increase in the L PL will not have a significant impact on the switching performance of the SiC MOSFETs in the target application. Fig. 7 shows the four-layer package that was redesigned without integrated decoupling capacitors. Removing the decoupling capacitors from the package allowed for a reduction in length from 44.2 mm to 38.4 mm. Vias and traces used to form electrical connections to the capacitors in the embedded die PCB were also eliminated, reducing manufacturing complexity. Since removing the decoupling capacitors has only a minor impact on electrical performance, and the footprint and manufacturing complexity are reduced, the package will not contain integrated decoupling capacitors.

D. LAYER COUNT SELECTION
The removal of the decoupling capacitors also eliminated the need for the DC-node to cross over the AC plane to form the electrical connection between the source side of the lowside device and the appropriate decoupling capacitor pad. That electrical connection was one of the main reasons a four-layer design was required in the first place. The two-layer design    Fig. 8 was made possible by removing the decoupling capacitors from the package and moving the DC+ terminal to the other side of the high-side SiC MOSFET. Table 2 lists the key simulated parameters of the two-layer and four-layer designs. Reducing the number of layers resulted in the two-layer package's lower L GL , but the DC+ and DC-terminals in the two-layer package are farther apart, so the L PL is higher; however, a 0.4 nH higher loop inductance is not enough to have a significant impact on the performance in this application. ANSYS Workbench Steady State Thermal simulations were performed on the two-layer and four-layer designs with 15 W loss applied to the junction of each die and an ambient temperature of 50°C to identify their maximum T J . A convection coefficient h of 1000 W/m 2 K was applied to the heat sink side of the packages. These same conditions were used for thermal simulations listed later in the article. The slightly higher maximum T J of the two layer design is the result of the die being closer together, but the two-layer package has no FR4 layer between the die and the heatsink, which will result in a lower R TH,JC .
Since the performance differences between the two packages are relatively balanced, the layer count selection comes down to which design has a lower relative manufacturing complexity and footprint. The two-layer design is 4.7% shorter than the four-layer design in Fig. 7 because the required clearance distance between the DC+ and DC-planes is eliminated. More obviously, the two-layer design also has two fewer layers than the four-layer design. Finally, due to the elimination of FR4 layers, the two-layer design has 5022 fewer microvias than the four-layer design. Therefore, the two-layer design was selected because it has sufficient electrical and thermal performance for the application, but it has a lower manufacturing complexity and a smaller footprint than the four-layer design.

E. TRACE-WIDTH SELECTION
The IPC-2221B standard helped determine trace widths for the traces in the power loop in previous iterations of the package. That standard applies only when both sides of the PCB are exposed to air, allowing for dual-sided natural convection; however, this package is intended to be surface mounted to a motherboard PCB, so verifying that there is an acceptable internal temperature rise in the traces is necessary. The internal temperature rise is defined as the difference between the maximum temperature of the traces in the PCB and the ambient temperature when the only heat-generation source is the ohmic loss of the traces themselves and the only form of heat exchange is conduction within the modeled bodies and natural convection (10 W/m 2 K) at exposed surfaces. Fig. 9 shows the model used to simulate the internal temperature rise in the traces of the package.
ANSYS Workbench was used to develop a two-stage simulation procedure. In the first stage, the 3D ohmic losses are extracted using ANSYS Maxwell 3D. Fig. 10 shows how current was applied to the traces in the two-layer package. The losses from ANSYS Maxwell 3D are then passed to the Steady State Thermal module in Workbench, where they are applied to the traces as an internal heat-generation source.  Since internal temperature rise is a differential measurement, the ambient temperature is arbitrarily set to 22°C.
The 3D ohmic loss and temperature distributions resulting from applying this simulation procedure to the two-layer package seen in Fig. 8 are illustrated in Figs. 11 and 12, respectively. The peak ohmic loss occurs near the die because the current must funnel into the drain side of the die, pass through the die, and travel back out through the source-side copper-filled microvias. The local temperature maximums in the temperature distribution occur where two current-carrying traces in the package overlap, doubling the ohmic loss in that area of the package. Table 3 lists the simulated internal temperature rises for the two-layer packages with the initial and final trace widths. Common practice is to limit the internal temperature rise to less than 30°C. The final motherboard design was unknown, so a 10% margin was added, resulting in a target internal

TABLE 4 Comparison of Simulation Results, Manufacturing Complexity Metrics, and Footprint
temperature rise of less than 27°C. The two-layer package requires an 18.5 mm width to limit the simulated internal temperature rise to 26°C. Fig. 13 shows trimetric views of the top and bottom of the final PCB-embedded SiC MOSFET half-bridge package. Table 4 lists simulation results and manufacturing complexity metrics for the final design from this work and the package found in [33], [34], which was designed with minimal consideration given to manufacturing complexity. The key advantage of the final design from this work is that the manufacturing complexity and footprint are reduced while maintaining sufficient electrical and thermal performance for the application. As noted in the introduction, manufacturing complexity and footprint impact the cost of PCBs [42]. The final design from this work has a lower layer count, a lower microvia count, and a smaller footprint while maintaining comparable simulated L PL and L GL . The maximum simulated T J of the final design from this work is 73°C higher but is still lower than the 175°C maximum temperature of the SiC MOSFETs. Although the final package's 0.47 mm thickness may raise some concerns about the mechanical rigidity, the package is intended to be surface mounted to a motherboard which would provide the required mechanical rigidity and durability.  Fig. 13(b) shows some minor modifications made after the trace width selection. To ensure the power terminals can carry sufficient current, they were widened from 1 mm to 2 mm. The corners of traces and pads attached to the gate and kelvin nodes were rounded to reduce electric field peaking. Appropriately named anti-rotation pads were added to the bare corners of the package to reduce the likelihood of rotation during solder reflow.

III. EXPERIMENTAL CHARACTERIZATION
Following the fabrication of the final package design, various tests helped characterize its electrical and thermal performance. Static characterization and DPTs were performed on the high-side and low-side switches to experimentally characterize the electrical performance of the package. Six of the packages were also tested in an ac-dc converter to demonstrate the package's performance in continuous operation. R TH,JC measurements were taken to experimentally characterize the thermal performance of the package. The following subsections provide details about each of these tests.

A. STATIC CHARACTERIZATION
A curve tracer measured the static characteristics of nineteen packages. The minimum, mean, and maximum drain-tosource leakage currents (I DSS ), gate-to-source leakage currents (I GSS ), drain-to-source on resistances (R DS,on ), threshold voltages (V GS,th ), and body diode forward voltages (V F ) extracted from those 38 MOSFETs are listed in Table 5. The I DSS and I GSS results indicate that the package provides sufficient isolation and that the die survived the packaging process. The mean measured R DS,on is only 0.4 m higher than the typical value listed in the datasheet; therefore, the package contributes little parasitic resistance to the power loop. The V F and V GS,th are within the normal ranges listed in the datasheet, providing additional evidence that the MOSFETs are healthy following the packaging process.

B. DOUBLE PULSE TESTS
DPTs provided the measured dynamic behavior of the package. In the first test, the high-side device functioned as a free-wheeling diode for the load inductor current (I L ) while the low-side device took the role of the active switch. In the second test, the high-and low-side switches swapped roles.
Each component labeled in the generalized test setup shown in Fig. 14 was chosen to promote quality dynamic characterization of the device under test (DUT) [48]. A 440 µH load inductor allowed for the desired pulse widths. Two parallel 590 µF, 1.3 kV capacitors supplied the bulk DC-link capacitance necessary for the test. Six parallel 15 µF, 1.5 kV capacitors with lower equivalent series inductance to suppress higher-frequency input voltage ripples provide additional DClink capacitance. The bleed resistance necessary to discharge the DC-link capacitors between tests was provided by two parallel 100 k , 100 W resistors. The drain-to-source voltage (V DS ) was measured with a Tektronix THDP0200 200 MHz, 1.5 kV differential probe, the I L was measured with a Tektronix TCP0030A 120 MHz, 30 A current probe, and the gate-to-source voltage (V GS ) was measured with a Tektronix TIVP1 1 GHz isolated measurement probe with the TIVPMX10X ±50 V probe tip. Unfortunately, due to the integrated nature and terminal placement of the PCB-embedded packages, it was impossible to measure the drain currents of the active devices without disrupting the ideal placement of decoupling capacitors. A fiber optic gating signal was supplied to the input of the gate-drive integrated circuit (IC) to eliminate the common-mode noise path between the DPT circuitry and the function generator. The turn-on and turn-off external gate resistances were 4.55 and 0 , respectively. For comparison, similar DPTs were performed on a TO-247-3L half-bridge and the half-bridge package found in [33], [34], both of which contain the same die as the package designed in this work. Comparing to a TO-247-4L package would have been preferred because it has a similar cost to the TO-247-3L but superior switching behavior. Unfortunately, the chosen semiconductor was not commercially available in a TO-247-4L package. Fig. 15 shows the turn-on and turn-off waveforms resulting from the DPTs of the high-side and low-side devices. Table 6 lists the V DS rise times and rates, fall times and rates, and overshoots. The rise times were measured from the point where V DS reached 10% of the input voltage to the point where V DS reached 90% of the input voltage. Similarly, fall times were measured from 90% to 10%. The dv/dts were measured at the steepest point along the curves.
The slightly higher turn-off V DS overshoots of the package designed in this work compared to those of the package found    [33], [34] are related to the faster switching transient and a slight increase in L PL . The faster switching transient is the result of lower parasitic output capacitance (C OSS ) [50]. The slightly higher L PL of the package designed in this work is related to one of the tradeoffs evaluated: whether to integrate the decoupling capacitors. The analysis presented in Section II of this article indicates that integrating the decoupling capacitors into the PCB-embedded package is not strictly necessary for this application. The experimental results support that claim because the turn-off overshoots of the package designed in this work are still an improvement over those of the TO-247-3L half-bridge and are well under the 1.2 kV rated maximum of the devices.
The oscillations seen in the V DS waveforms at turn-off are caused by resonance between the C OSS of the device acting as the free-wheeling diode and the L PL [51], [52]. Equation (1) relates C OSS and resonance frequency (f res ) to L PL . Table 7 lists the C OSS , f res , and L PL for all six devices. There is good agreement between the L PL s calculated using the high-side and low-side DPT results for each package. The L PL s found using ANSYS Q3D-Extractor in Section II of this article did not account for the equivalent series inductance of the decoupling capacitors, which could help explain the difference between the measured and simulated L PL s.  The V GS waveforms of the package designed in this work and the package presented in [33], [34] are very similar. By comparison, the V GS waveform of the TO-247 half-bridge is much noisier. The PCB-embedded packages allow for much lower L GL which can explain some of the differences in the V GS waveforms; however, the main contributing factor to the difference in the V GS waveforms is that the PCB-embedded packages have kelvin source connections that decouple the power and gate loops, while the gate and power loops in the TO-247 half-bridge share a common source.

C. CONTINUOUS SWITCHING TEST
Initial continuous switching tests were performed to demonstrate the final package's ability to function in a converter. The ac-dc converter topology and control strategy identical to those found in [34] were chosen for this purpose. The ac-dc converter specifications are listed in Table 8 and the associated switching waveforms are seen in Fig. 16. These waveforms match those of the converter demonstrated in [34], indicating the reduced manufacturing complexity and footprint size of the final package did not impact its continuous switching performance.
It should be noted that the specifications listed in Table 8 are only for the operating point chosen to demonstrate the continuous operation of the package for the purposes of this article. The converter was designed to operate up to 22 kW output power. The complete demonstration of these packages in a 22 kW OBC is the focus of on-going work and is outside the scope of this article.

D. THERMAL-RESISTANCE MEASUREMENTS
The R TH,JC of the high-side and low-side switch were measured using the Analysis Tech Phase 12B Thermal Analyzer according to the transient dual-interface method (TDIM) defined in the JEDEC JESD51-14 standard [53]. The procedures and conditions used to measure the R TH,JC s were chosen based on the guidelines found in [54]. A custom clamp tip provided a clamping pressure of 10 PSI. The two thermal interface materials were Dow Corning TC-5026 thermal grease (2.9 W/mK) and silicone oil (0.1 W/mK). The thermal grease was screen printed with a thickness of 2 mil and the silicone oil was applied with a pipette. A 1 mm thick copper standoff was used in conjunction with a custom alignment jig to measure the R TH,JC of one die accurately without shorting the half-bridge. Fig. 17 shows the test setup used to collect the heating curves for R TH,JC measurement.
Visual analysis was used to reject R TH,JC measurements with suspect heating curves according to the guidelines in [54]. Table 9 lists the average, standard deviation, and maximum deviation of the repeated R TH,JC measurements. An example of the transient thermal impedance curves used to extract the R TH,JC from the package designed in this work is seen in Fig. 18. Fig. 19 compares the R TH,JC of this package with the R TH,JC of a TO-247 package and the R TH,JC s of the package described in [33], [34], all of which were measured under the same test conditions. The R TH,JC of the package  designed in this work is lower than that of the package described in [33], [34] because, as predicted in Section II-D of this article, the elimination of an FR4 layer between the heatsink and the die results in a lower R TH,JC .

IV. CONCLUSION
This article presented a PCB-embedded 1.2 kV SiC MOSFET half-bridge package with reduced manufacturing complexity and footprint that meets the electrical and thermal performance demands of a high-power-density 22 kW OBC. The final design is a 37.1 mm × 18.5 mm surface-mount package with an extremely low profile of just 0.47 mm. Experimental characterization validated the claim that the package meets electrical and thermal requirements. Static characterization revealed that the package provides sufficient electrical isolation and contributes little parasitic resistance to the power loop. DPTs performed on the top switch at a V DS of 800 V and an I D of 25 A resulted in turn-off and turn-on dv/dts of 41 V/ns and 41 V/ns, respectively, and a V DS overshoot of 34 V. Six of the packages were operated in an ac-dc converter to demonstrate their performance under continuous operation. The measured R TH,JC was 0.074 K/W.
As identified in the U.S. DOE's "EV Everywhere Grand Challenge," a key barrier to the adoption of SiC in EVs is the availability of low-cost, mature packaging technologies that allow the packaging structures necessary for SiC devices to outperform their Si counterparts. PCB embedding is a promising approach due to the maturity of PCB technology. This article evaluated different PCB-embedded package structures to identify one that meets the electrical and thermal requirements of a 22 kW OBC with reduced manufacturing complexity and footprint for the purpose of cost reduction.