Power Flow Control for Decoupled Load Performance of Current-Fed Triple Active Bridge Converter

This article presents a phase-shift control method for a converter containing a multi-winding transformer. The control strategy is developed from a power flow analysis of the converter and uses the derived power flow equations to supply constant power at a load port while the second load port experiences large load changes. This control method prevents the constant load port from experiencing transient behavior caused by magnetic coupling with the other load port. The approach is demonstrated with an experiment using a controller within a control hardware-in-the-loop set-up and then a full experimental setup within a lower power test bed. By using control to mitigate the effects of mutual flux within a multi-winding transformer, the load ports of the converter are effectively decoupled. The analytical procedure described in this article can also be applied to other converter topologies containing multi-winding transformers to achieve similar decoupled load performance, as demonstrated in the triple active bridge converter test bed.


I. INTRODUCTION
The widespread adoption of dc systems for low-voltage applications at the distribution level has spurred further research into even higher power dc networks, including increased system voltages into the medium voltage (MV) range. However, as the capacity of dc networks is increased, certain concerns arise. Namely, DERs themselves typically increase the control burden of the network [1], [2], [3]. In addition, the intermittent nature of renewable energy resources usually requires the system designer to include energy storage devices to reduce transient power fluctuation within the network [4]. On top of it all, traditional AC circuit breakers cannot be used currently within MVDC networks, making fault protection of these networks difficult.
A key component within dc networks that can address many of these issues is the converters that interface with the network. Modern solid-state switches and stacked topologies have recently enabled the possibility of operating at the kilovolt level for connection to the utility grid [5], [6], [7]. Power electronics can be used to increase flexibility of the dc network and also to respond to DERs [8], [9], [10], [11].
In addition, multi-port converters provide a method to tie in energy storage into the network using centralized control [12], [13], [14], [15]. At present, there are also at least six different categories of fault current limiting power converters available to protect the network from fault events [16].
A centralized converter with multiple ports can be used within a dc network to incorporate DERs, storage, and other networks into a grid with minimal conversion steps [13], [17], [18], [19]. Also, by adding inductance to a converter, fault tolerant operation can be achieved [20]. If these features are combined, the result is a current-fed, multi-port converter that can interconnect multiple MVDC buses within a dc network [21]. See Fig. 1 for an example dc network that makes use of such multi-port converters to create a ring network.
The current-fed triple active bridge (CFTAB) converter design is the basis for the research performed in this article [21]. With emerging state-of-the-art magnetics enabling the design of transformers and inductors for solid-state transformers (SSTs), the previously theoretical coupled inductor design becomes within hardware. Before taking that next step into hardware, further study into the converter performance to design a stable controller is required.
The contribution of this article is twofold. First, this article provides a comprehensive power flow analysis for all operating modes of the CFTAB converter. This article provides a step-by step description of the analysis, which makes the method easily repeatable not only for this topology, but for other converter topologies containing multi-winding transformers. The second contribution of this article is to harness the results of the power flow analysis to propose a control strategy based on the resulting power flow equations. Such a controller for the CFTAB converter has not been proposed before in the literature. The critical feature of the proposed control is that transient power flow conditions at one of the load ports do not affect the power flow performance at the second load port. This is because the coupled flux effects within the multi-winding transformer are predicted from the power flow analysis and compensation is incorporated within the controller. This control compensation is useful when significant load changes can create voltage disturbances at the other two dc ports, particularly in the case of weak grid systems like an islanded microgrid [22]. In electric vehicle applications as well, it is an important controller design metric to shield the battery port from transient disturbances [23]. Traditionally, a decoupling matrix is used to prevent transient disturbances. However, this method requires linearization around an operating point to derive the decoupling gain matrices. The proposed control strategy will be able to achieve decoupled performance without the need to re-calculate the control laws as the operating point changes.
The article layout is as follows: in Section II, the circuit schematic and phase shift control strategy are introduced. Then in Section III, the power flow analysis is performed to provide power output equations of each port for the entire operating range of the converter. Next, in Section IV, the control strategy is developed from the results of the power flow analysis. Section V demonstrates stable operation and provides the results of a control hardware-in-the-loop experiment employing the proposed control strategy. Section VI contains experimental results of using the controller with a prototype triple active bridge converter. Finally, Section VII concludes with the results of the work effort.

II. CIRCUIT SCHEMATIC
Traditionally, a dual active bridge (DAB) converter is comprised of a high frequency transformer with both the primary and secondary windings each having a full H-bridge interface to the primary and secondary dc buses [2], [24], [25], [26]. This traditional DAB topology can be controlled by adjusting the phase angle delay of the secondary side square wave with respect to the primary. Triple active bridge (TAB) converters are similar, with the addition of a tertiary H-bridge port and a 3-winding high frequency transformer [12], [27].
The CFTAB converter developed in this article takes the typical design of a TAB converter and adds mutual inductor pairs to the medium voltage windings of the three-winding transformer [21]. The topology of the converter is shown in Fig. 2. The secondary and tertiary ports are both connected to their respective MV dc buses and could represent a redundant connection to a critical load, or to two separate dc buses all with independent load and generation profiles. To operate at MV levels, the secondary and tertiary sides will require switching submodules to be placed in arm configurations as shown in the figure. The arm configurations of the MV ports resemble the stacked submodule style within a modular multilevel converter (MMC). A simplification is made in this article by approximating each stacked arm submodule as a single ideal voltage source.
The winding leakage inductance of the primary, secondary, and tertiary windings are L 1 , L 2 , and L 3 , respectively. The MV ports have mutual inductor pairs, and the naming convention is based on the pattern L xDCyz , where x is the port number, y is either 'h' for high-voltage side (positive polarity of xfmr) or 'l' for low-voltage side (negative polarity of xfmr), and z is either 1 or 2 which identifies which inductor within the mutual inductor pair.
The converter power flow is determined by the voltages v 1 , v 2 , and v 3 and currents i 1 , i 2 , and i 3 which correspond to the primary, secondary, and tertiary transformer windings, respectively. The power flow at any port x can be computed as: Since MMF is shared within an ideal transformer, the overall power flow of the converter can be defined as: Phase shift control is used to regulate the power flow of this converter. As is typical based converters, the average current through the transformer is assumed to be zero under stable operation. The proposed control is phase shift-based and uses average power output as the control reference. Shown in Fig. 3 are the square voltage waveforms that are applied at each port of the converter. Note that while the voltage v 1 is directly applied to the primary windings of the transformer, the arm voltage waveforms v arm2 and v arm3 are not directly applied to the secondary and tertiary MV transformer windings due to the mutual inductors. The voltages across the secondary and tertiary windings of the transformer (v 2 and v 3 ) can nevertheless be computed from the three controlled switched voltage waveforms (v 1 , v arm2 , and v arm3 ) The primary voltage waveform v 1 is used as the reference, and the two controllable parameters are the phase shifts of the secondary (φ 2 ) and tertiary (φ 3 ). In addition to controlling phase shift, it is possible to additionally regulate the duty cycles of each square wave.
However, the duty cycles at the ports with mutual inductors are bound by the relationship in (3), [28].
Where D = 0.5 is an ideal square wave. If this condition is not met, the mutual inductor pairs will experience a dc voltage bias, and the current will become unstable. Therefore, the duty cycles at the secondary and tertiary ports in this application are not freely available to be used as control variables.

III. AVERAGE POWER FLOW ANALYSIS
The average power flow was computed by using a switched circuit model for all eight possible states. There are potentially more states, but in this application a duty cycle of D = 0.5 was maintained on the secondary and tertiary ports for stability purposes. To reduce possible states, the duty cycle of the primary was maintained at 0.5 as well.
A single switching cycle of this converter is expected to be within the kilohertz range. This makes it intuitive to assume that the dc bus voltages and submodule voltages will remain constant within a switching cycle. Under this assumption, the currents become linear, and a state space representation of the circuit can be constructed.

A. DECOUPLING MUTUAL INDUCTOR CHARACTERISTIC EQUATIONS
One key challenge in the circuit analysis is mathematically decoupling the currents within the mutual inductor pairs. The standard equation for the voltage applied across an inductor with mutual coupling is: Where α denotes the first inductor within the coupled pair and β denotes the second inductor. This equation is unfortunately not linear but it is possible to perform a circuit analysis to substitute for one of the inductor current derivatives.
Reflecting on the topology in Fig. 2, there are two mutual inductor pairs on each of the two MV ports. This equates to a total of eight inductors that have non-linear state equations. Performing the substitution to a linear form will require 21 equations. The equations can be derived from the circuit diagram in Fig. 2 and will be shown now.
Mutual inductor equations from Kirchhoff's voltage loop within one MV port: Kirchhoff's voltage loops within each MV port: Kirchoff's current law at ports 2 and 3: v L2 Faraday's law for mutual inductors in ports 2 and 3: Note that the second current slope term is added instead of subtracted as in (4). This is simply due to the current direction defined in the other direction in the circuit schematic in Fig. 2.
Three-winding transformer turns ratio and current balance equations: The final step in preparation to solve the equations is to establish which variables are states within the system and which are controllable inputs. After decoupling the mutual inductor currents, the system can then easily be rewritten into state space form. The state space equation is of the forṁ x = Ax + Bu where the arrays x and u are: Solving for each state variable is done through MATLAB's symbolic solver toolkit. This solver was used to solve the system of 21 equations to mathematically decouple the mutual inductor currents from their respective pair. The result of the analysis provided a linear equation for the current derivatives for each mutual inductor, which allowed the system to be put into state space form.

B. COMPUTING INITIAL CURRENT
Before computing the average power flow, the average current through the transformer inductors must equal zero. Typically, this means that at steady-state, the current values at the start of a switching cycle are non-zero. To determine the correct initial current values, begin with zero initial current within all inductors, and then compute the final current values after the third switched state (halfway through the switching cycle). The initial current is equal to: i(0) = − 1 2 i( T s 2 ). As the system is in state-space form, the linear derivatives of currents are known. The change in current during a state is equal to the following equation where ϕ is the fraction of the total switching cycle that the state is active: All switching signals have a 50% duty cycle, the converter will be exactly halfway through a switching cycle after three states.
Once the steady-state initial current values are known, the current waveform for an entire cycle can be computed by applying (28) for each of the six states. Since there are six states, there will be six intervals to compute the change in current. The current value at the end of each state can be computed with (29): Where x represents the port number, t f n is the final time at the end of state n, and i Lx (0) is the initial current at the beginning of state n.
Computing Average Power Flow The voltage during a state is assumed to remain constant. The current changes in a linear trajectory. Therefore, the average power flow at a port during a single state is equal to Where x represents the port number and t f n is the final time at the end of state n. Recall that the current i x is equivalent to the current flowing through the transformer winding at that port i Lx . The MV voltages can be computed from (9) and (10), and the primary port voltage is already known. Since the transformer leakage inductor currents are states, the initial and final current at each state can easily be computed using the state space matrices using the method described in (28). The average power flow through the converter during an entire Where P xn is the average power at port x during state n, and ϕ xn is the fraction of the total switching cycle that state n occurs. The phase shift ϕ can be converted to radians by multiplying by 2π .

C. AVERAGE POWER FLOW ACROSS ALL MODES
The average power flow was computed for the entire operating range of the converter (−0.5 < ϕ 2 ≤ 0.5 and −0.5 < ϕ 3 ≤ 0.5). A key feature to note is that the power flow equations are unique to the sequence of the switches. There are eight possible switching sequences, and each sequence will be called a 'mode' of the converter. See Table 1 for the list of possible operating modes of the converter. The resulting power flow equations for the first five modes are as follows: Where,  Table 2 provides the circuit design parameters for the CFTAB converter, as mentioned. These parameters are based on the design parameters of a previous analysis and are similar to analyses on other multi-port structures [13], [21]. One key feature to note is that the switching frequency of the design has been slowed down from 40kHz to 1kHz to account for performance restrictions within the TI controller and real-time digital simulator (discussed in Section V). To achieve similar output power of the converter, the inductance values are increased by a factor of 40 from the reference design. Note that this limitation of the experimental setup is not in itself a limitation of the speed of the proposed control or converter.
The circuit component values in Table 2 were substituted into (32)-(47) and the resulting power output waveforms at each port are plotted in Fig. 5 for the full switching range for −0.5 ≤ φ 2 ≤ 0.5 and −0.5 ≤ φ 3 ≤ 0.5. The eight different modes are colored separately in the graphs to clearly show each mode. A key feature to note is that the power output at a port x trends from negative to positive for the range −0.25 ≤ φ x ≤ 0.25, regardless of the phase shift at the other port. This linear behavior is used in typical control strategies to independently control each port by increasing its phase shift to increase power flow to that port, and vice versa. A key result of any change in phase shift, however, is a clear change in power output at both ports. For example, if an increase at port 2 power flow is desired and φ 2 is increased accordingly, the power output at port 3 will certainly change as a result. The following section of this article will describe a method of adjusting the power output at one port without affecting the power output at the other port. As a reminder, the power output at port 1 is simply equal to the sum of the power flow to ports 2 and 3 as described in (2). Therefore, the power output at port 1 is also controlled by manipulating φ 2 and φ 3 .
Ports 2 and 3 power output with 5 kW power reference at port 3. Valid operating points that output 5 kW at port 3 are highlighted in dark black. Note that at port 2, the power output can equal zero near the origin with power output increasing or decreasing according to the phase angle φ 2 .

IV. AVERAGE POWER FLOW CASE STUDY-CONSTANT 5 KW POWER OUTPUT AT PORT 3
Deriving the power flow equations makes it possible to compute the valid operating points of (φ 2 , φ 3 ) that will deliver a constant power output at one of the ports. Then, a trajectory of these operating points can be discovered to allow the other port to adjust power flow while maintaining constant power at the original port. To demonstrate this concept, a case study will be explored using the parameters in Table 2 for a constant 5 kW load at port 3.
In Fig. 4, the highlighted operating points (dark black) are in a flat plane at 5 kW for port 3 output power while the trajectory of port 2 output power can range from approximately −10 kW to 10 kW. It can also be noted that the control strategy can be simplified further by restricting the operating points to −0.25 ≤ φ 2 ≤ 0.25 and −0.25 ≤ φ 3 ≤ 0.25 to force proportional control. This means the power output at port 2 increases as the phase angle φ 2 is increased (and vice versa), which makes standard feedback control well-suited to regulating the power output at Port 2 by regulating φ 2 . The phase shift φ 3 can then be computed from φ 2 to achieve a constant 5 kW power output at port 3.

V. CONTROL HARDWARE-IN-THE-LOOP EXPERIMENTAL RESULTS
For the case study, port 3 was treated as a constant power load of 5 kW. The decoupled control strategy that will be described  below allows the power at port 2 to swing between 0W and upwards of 7 kW. To confirm that the proposed control strategy was viable, a Typhoon HIL 402 real time digital simulator was used to emulate the converter and grid behavior in real time. The converter control was installed onto a TI 28379 controller. A Typhoon DSP180 interface was used to connect the controller input and output signals to the Typhoon HIL 402. This control hardware-in-the-loop (CHIL) experiment successfully demonstrated steady-state stability of the simulated converter when using the external controller.

A. TYPHOON HIL SCHEMATIC AND SCADA PANEL
The circuit topology in Fig. 2 was designed within Typhoon HIL's schematic editor. The Typhoon model is shown in Fig. 5. The component values are selected per the converter parameters in Table 2.
The MV H-Bridge ports contain the switches and mutual inductor pairs according to Fig. 2. The switches are set within the Typhoon HIL simulation software to be controlled by an external digital signal produced by the TI 28379 controller. In the SCADA system the values of P 2 and P 3 are set as analog output reference signals to the controller.

B. TEXAS INSTRUMENTS CONTROLLER
The controller is programmed by flashing PLECS control blocks onto the controller using the coder compiler software package for rapid controller prototyping. The PLECS control blocks are shown in Figs. 6 through 8. Fig. 6 is the overall control system that receives analog inputs from the Typhoon HIL simulation and uses those signals to generate the phase shift control strategy. The result of the control is 6 digital output signals (2 square wave forms per port) that are sent to the switches at each port. Looking into the phase shift controller block gives Fig. 7.   Typhoon HIL SCADA to the average power output of the Typhoon HIL simulation. The error signals are then passed into a phase shift equations subsystem, which generates modulation values for the secondary and tertiary ports. The modulation signals are passed into standard phase shift PWM blocks, which uses a triangular carrier wave and waveform crossing detection to generate the switching signals for the primary, secondary, and tertiary ports of the converter. Fig. 8 shows the details of the phase shift equations block. φ 3 is generated from the value of φ 2 while in mode 2. A similar derivation and control law is applied for mode 1.
The controller receives a power reference signal for each port, as well as the measured power signal output from the Typhoon HIL simulation. The controller takes the difference of P 3 from the reference value to determine which equation to use. In this case study, if P 3 < 5kW , then the control will attempt to output a higher power (7 kW) until 5 kW is reached. Likewise, if P 3 > 5kW , the control will output a lower power (3 kW) until 5 kW is reached. Note that this control was limited to only unidirectional power flow. However, the control can be extended to the full range of operation using the computed power flow equations in (32)-(47). Also, this control strategy can be adapted to instead control the bus voltage or to control the output current at a port instead of the average power.

C. REAL-TIME DIGITAL SIMULATOR EXPERIMENTAL RESULTS
The results of the C-HIL experiment are shown in Figs. 9 and 10. The primary source feeds a continuous 5 kW to the constant power load at port 3. Initally, port 2 is disabled. When a 5 kW demand is activated at port 2, the power output at port 3 remains unaffected. Fig. 10 is provided to 1) verify stable steady-state operation, 2) verify transient load conditions at port 2 do not affect the power flow at port 3 and 3) stable steady-state operation.

A. CONTROL CARD SETUP
The PLECS controller described in Section V was downloaded to a Texas Instruments F28335 control card using a USB probe interface and the PLECS TI C2000 blockset. The F28335 controller was interfaced with the converter via a TMS320F28335 evaluation board. Digital outputs and analog inputs were buffered using op amps to introduce high impedance between the control card and the converter. This prevents common mode noise generated by the converter from affecting the F28335 control card. The USB probe interface allowed continuous communication between the F28335 control card and the PC through the PLECS coder external mode.

B. TEST BED PARAMETERS AND EXPERIMENTAL SETUP
The proposed controller's performance was validated by using a triple active bridge converter test bed. The converter components are rated for 1kV and 50 kW using 1200V CREE SiC MOSFET half bridges as the switching devices. However, due to infrastructure limitations of the power supply and loads of the test bed, a 150V, 1 kW test was implemented for validation of the control. The effects of this de-rated test will be discussed in section C. The TAB converter parameters are given  in Table 3, and further information about the TAB converter test bed can be found in [29].
One key difference between the TAB converter within the existing test bed and the current-fed TAB converter discussed in earlier sections is the absence of the mutual inductor pairs at the current-fed ports. As a result, the proposed controller was re-derived using the techniques mentioned in Sections III and IV-this time for a voltage-fed TAB converter topology. The successful implementation of the proposed controller highlights the controller's flexibility for use within voltage-fed 3-port converter topologies in addition to the original currentfed design.
The test bed setup is shown in Figs. 11 and 12. Fig. 11 is a picture of an individual H-bridge module. The bus capacitors are connected to the SiC half bridges through a bus plane. The gate drivers are mounted directly above the MOSFETs. The entire assembly is mounted to a heat sink. Each H-bridge module is mounted to the chassis and is labeled by port number in the figure. Port 1 is the input port and ports 2 and 3 are the load ports. The 3 winding transformer is mounted at the top, and external series inductors are connected to give the inductance values in Table 3. A block diagram showing the connection between the control and the hardware test bed is found in Fig. 13.

C. EXPERIMENTAL RESULTS AND DISCUSSION
After evaluating the ac waveforms of the converter, the steadystate stability of the dc bus voltages were confirmed. Also, the  transient behavior of the dc bus voltages were studied. The converter was operated with a traditional PI controller as a reference, and then operated again with the proposed power flow controller. Fig. 14 shows the results of PI dc bus voltage regulation at ports 2 and 3. The PI control was tuned to have a critically damped response with no overshoot. The figure shows port 2 tracking a 52V reference (200W) with a reference transition to 74V (400W) and port 3 tracking a 25V reference with a reference transition to 50V. The settling times during a voltage reference change can be seen in Fig. 14. The settling time for port 2 is approximately 125 ms during a voltage reference change at port 2 and approximately 500 ms during a voltage reference step change at port 3. Likewise, the setting time for port 3 is approximately 125 ms during a voltage reference change at port 3 and approximately 500 ms during a voltage reference change at port 2. Fig. 15 shows the results of the power flow controller at port 2 with a PI controller at port 3. Fig. 15 shows port 2 tracking a 200W reference with a reference transition to 400W and  port 3 tracking a 25V reference with a reference transition to 50V. The voltage references were continually changed in this experiment since part of the motivation for developing the power flow control strategy was to operate during varying bus voltages. One thing to note is the transient voltage drops in the dc bus voltage waveforms. This is a disturbance caused by the converter operation and not due to the control. In future work, ringing at the load ports for the test bed will need to be suppressed to prevent this transient discharging of the dc bus capacitors. Fig. 15 demonstrates stable operation of the power flow controller at port 2. Port 2 was selected instead of port 3 for the power flow controller because, due to its lower inductance, port 2 was more susceptible to experiencing coupled transients due to a load change at port 3. One key requirement for correctly tracking the power reference at port 2 is to have exact parameter information for the inductance values of the transformer. If not, the output power at port 2 will not accurately track the power reference. Fig. 15(a) shows the performance of the controller using the inductance values from Table 3, before tuning. Note how the steady-state bus voltage at port 2 changes with the bus voltage at port 3. Fig. 15(b) shows the performance of the controller after manually tuning the inductance values within the control until the power reference was properly tracked at port 2, regardless of the bus voltage at port 3. Finally, after tuning the control, an outer PI control loop was added to increase/decrease the input into the controller if the measured power output deviated from the reference. The settling times for port 2 in Fig. 15 are approximately 20 ms during a voltage reference change at port 2 and approximately 500 ms during a voltage reference change at port 3. Likewise, the settling times for port 3 in Fig. 15 are approximately 20 ms during a voltage reference change at port 3 and approximatly 500 ms during a voltage reference change at port 2. This applies to both Fig. 15(a) and (b). Referring back to the purely PI control in Fig. 14, this is an improvement of the ∼125 ms settling time at a port when a port undergoes a voltage reference change.
While the real-time experiment in Section V was able to both demonstrate stable operation of the controller as well as compensation to eliminate voltage disturbances, a key gap in this test bed experiment for Section VI is the inability to implement a large enough load change to create a voltage disturbance. This scenario requires a power supply and loads rated for the 50 kW converter. However, despite not being able to generate a significant voltage sag during a load change, the stability of the power flow controller can still be confirmed when comparing Figs. 14 and 15. The proposed power flow controller in Fig. 15 achieves similar steady-state performance to the PI controller in Fig. 14.

VII. CONCLUSION
This experiment successfully employed a control strategy for a current-fed triple active bridge converter that prevents disturbances at a load port from disturbing the power flow at the second load port. By computing the relationships between the phase angles φ 2 and φ 3 and the port power outputs P 2 and P 3 , the power output at port 2 was able to be freely controlled by φ 2 while φ 3 was used to maintain a constant power output at port 3. The procedure was presented in such a way that the process for deriving the control relationships can be replicated for the CFTAB converter topology, enabling a pathway for further advanced magnetics within the multi-port converter. The controller was validated at the MV scale using real-time digital simulation and at a low voltage and power scale with a triple active bridge converter test bed.