A Partial Discharge Inception Voltage Modeling Approach

A partial discharge inception voltage modeling approach promoting design-for-reliability considerations in advanced power modules is presented. As power modules are being operated at higher voltages and become more compact to meet power density demands, there is an increased risk of partial discharge, the silent precursor to electrical breakdown that degrades insulation material. The trade-off between voltage class and module compaction must be quantified. This work presents a methodology to model the tradeoff for any substrate and encapsulant material. A surface charge density-based partial discharge inception voltage (PDIV) model was developed to overcome the challenges in electric field-based models. The model consists of a closed-form equation that accepts finite element simulation results as input and produces PDIV as output. The model was experimentally validated for various trace gaps in a 12/25/12 mil alumina DBC using Dow Corning 3-6635 dielectric gel. An expected trend of diminishing returns was observed between PDIV benefit and trace-gap. This approach quantifies this diminishing returns point. To design for reliability, the maximum operating voltage must be limited to the PDIV. For a material set and manufacturing process, this methodology can be used to determine the voltage class and trace gap design rules.


I. INTRODUCTION
Partial discharge in power modules has captured the interest of the power electronics industry because of the significant cost it incurs in maintenance time and the risks involved with the safety of personnel in the event of an electrical breakdown. This work envisions an approach of pre-determining safe operation design rules for power modules to ensure reliable operation. Power module designers, especially those working in industries like electric vehicles, where power density is a crucial metric, will benefit most from this work.
Technologically, wide bandgap (WBG) semiconductors have advanced significantly over the past couple of decades. However, the lack of packaging innovation for these devices impedes the advancements offered by WBG technology [1], [2], [3], [4], [5]. Thus, there is a great push towards advancing power module optimization and packaging innovation to harness the complete utility offered by WBG devices. However, thermal coupling, mechanical instability, electromagnetic interference, and partial discharge [5], [6], [7], [8], [9], [10] are just some of the reliability-related side-effects of high speed power conversion and high power density packages. The focus of this article is partial discharge mitigation in compact power modules.
Partial discharge (PD) is a localized electrical breakdown in an insulating material that does not fully bridge the gap between the electrodes [11]. The voltage at which repetitive PDs of a pre-specified quantity/threshold are observed is called the partial discharge inception voltage (PDIV). PD is commonly found in the insulating materials of cables, motor and transformer windings, and in power modules [5], [7], [12], [13], [14], [15], [16], [17], [18], [19] due to the ever-decreasing trace gaps between conductors in module layouts. While PD does not always immediately cause a breakdown, the continuation of PD beyond the PDIV starts the slow and steady degradation process of the material, sacrificing the reliability of the entire module. Progressive PD is a silent pre-cursor to electrical breakdown and can lead to catastrophic damage if it goes undetected. This can cause, at best, a significant down-time to remove and replace the damaged part from an adequately protected circuit, or at worst, a sustained arc that can cause severe consequences. To prevent such hazards, one must account for PD at the design stage instead of managing its effects later.
The general practices to mitigate PD at the design stage include substrate stacking [5], guard rings [5], gap extension between the copper edge and the ceramic edge [17], metal layer protrusion past the ceramic edge [14], coatings for field grading [14], and corner filleting [12]. These intuitive practices are good, but there are no design rules codifying these practices. Since the power module physical design process is automated [2], [20], PD rules need to be accounted for in module design automation. This work is a step toward providing a methodology or approach to account for PD systematically in the design automation of power modules.
One way to design for PD prevention is to consider PDIV as a maximum voltage constraint in the design process of power modules. For cases where the voltage class is already fixed, the material and layout choices can be adjusted. In Very Large Scale Integration (VLSI), design rule checks (DRCs) and process design kits (PDK) are commonplace for the rapid and reliable design of integrated circuits. For power modules, PD-related DRCs can be employed in an analogous fashion, and the voltage class for each material set can be saved in a manufacturing design kit (MDK) library. It is therefore essential to quantify PDIV. And to do so, one must first understand how to model PDIV.
Modeling PDIV is challenging because PD is nondeterministic. A lot of fundamental scientific work has been done in understanding the PD phenomenon at the physical level [21], [22], [23], [24], [25], [26], [27], especially in modeling the electric field (E-field) inside voids of various geometries. However, PD is stochastic in nature [28], [29] and this is one of the key modeling challenges addressed in this work.
The other modeling challenge is the singularity at the triple point (TP), where it is difficult for a computational tool to converge on an E-field value. Fig. 1(a) depicts a simple example of a power module cross-section highlighting the TP, the point where three different materials meet: the metal, the ceramic, and the encapsulant. There is a high potential difference across the ceramic isolation and the lateral trace gap. Theoretically, E-field concentrates at the triple point due to: 1) Field lensing caused by the change in the dielectric constant of the materials at the TP [21], and 2) Accumulation of charges at the sharp geometric asperities [30] at the TP. Sharp corners are caused by a) active metal brazing, b) the concave profile created by wet chemical etching, and c) the geometry of the corner itself. Researchers have navigated around the convergence issue either by using 2D E-field simulations or by keeping the measurement point (MP) a fixed distance away from the TP [5], [13], [18], [19], [31], [32]. 2D models can be too simplistic as they do not account for the depth factor, and the fixed distance solution can be challenging if the measurement point (MP) is inside the trace-gap, a variable feature. The convergence issue is overcome in this work in a novel way that is accurate and validated by experiments.
Many of the existing PD-modeling and mitigation efforts consider PD only in the ceramic isolation material of a power module. Fig. 1(a) shows the various layers of a typical power module. Since there is a high potential difference across the ceramic isolation material, a breakdown is certainly possible if the isolation layer is not thick enough to withstand the E-field or there are significant defects present. However, the lateral trace gap is also a common site for PD, since a high potential difference exists in the trace gap, especially when these gaps are being reduced to meet density demands. Experiments done by the authors and corroborated in the literature [32] have shown that breakdown can happen in the trace-gap ( Fig. 1(b) and (c)) even in the presence of a metal plane on the backside of the DBC. The effect of the lateral trace gap on the PDIV of the module is a technology gap that is being addressed in this work.
To date, there are no standardized DRCs developed to prevent PD inside power modules, except for preliminary work done by the authors based on 2D computational models [33]. In previous work, the authors found a way to navigate the convergence issues at the triple point singularity while still capturing the effects of the trace gap dimension. This was done by considering charge density instead of E-field. The authors developed an initial charge density vs. trace gap curve-fit model for a simple power module template structure through finite element analysis. Continuing the effort in the current work, a more accurate 3D version of the model was developed in terms of PDIV vs. trace gap that was experimentally validated. Such a relationship addresses the urgent need to formulate PD design rules for power module design.
The key contribution of this work is an approach to model PDIV and quantify a voltage class and corresponding trace gap for a chosen DBC and encapsulant technology. This approach includes: 1) a unique way to measure surface charge density through 3D FEA simulations that avoids the challenges of measuring E-field at the triple point, 2) equations to estimate PDIV from surface charge density simulation results, 3) calibration of the PDIV model through experimental results using analysis of the stochastic nature of PD across multiple identical samples, 4) experimental validation of the trend of diminishing returns in the PDIV vs. trace gap relationship observed in the prediction model, and 5) quantification of the point of diminishing returns in terms of a voltage level and minimum trace gap, validated by experiments. The contribution enables the development of design rules for power modules specific to PD mitigation. The methodology used to develop this model paves the way for the future development of more comprehensive design rules that can be added into the MDK as power module architectures mature.
The scope of this work is limited to: A single material technology, expandable to include others in future work. Material technology consists of the DBC's relevant material properties, dimensions, and encapsulants' material properties. In this work, the technology is fixed while the layout geometry changes. Simple trace geometry with a parallel trace gap, not the diagonal gap between one corner of a trace to that of another or curved traces. Vertical-trace-etch face instead of the concave wet-etch profile, to ease calculations and avoid numerical convergence issues.
Finding the voltage at which PD begins instead of the exact location where it happens. In sum, while there is ongoing foundational work in understanding and modeling the complicated physics of partial discharge and the engineering of various PD mitigation strategies, there are no hardware-validated rules or standards codifying the likelihood of PD in native trace gaps. This work is pioneering the movement toward a reliability-based DRC paradigm specific to partial discharge prevention inside power modules using automation tools.
The following section gives an overview of the PDIV modeling methodology. Section III details the derivation of the prediction model. Section IV details the experimental procedure to calibrate the model. Section V is a description of the results and the outlook for future work.

II. PDIV MODELING METHODOLOGY OVERVIEW
The methodology presented is a way to model PDIV vs. trace gap for any combination of: -Technology (DBC and Encapsulant) and -Manufacturing process. This approach involves determining the PDIV vs. trace gap relationship computationally using the PDIV model and then validating the relationship experimentally. Calibrating the computational model to PDIV lab test results using a calibration factor will validate the relationship. A couple of closed-form equations are used to model PDIV computationally. These equations take surface charge density values extracted from 3D FEA simulations of a simple DBCencapsulant test structure and transform the values into PDIV. The calibration factor predicts the voltage at which PD begins relative to the theoretical breakdown voltage. The approach to model PDIV is summarized in Fig. 2. A patterned and encapsulated DBC test coupon is simulated in ANSYS Maxwell, a 3D FEA software. The trace gap (tg) is varied, and the surface charge density (Q surf ) is recorded for each trace gap. Q surf is then transformed into PDIV using appropriate material properties such as dielectric constant (ε r ) and dielectric strength (E DS ). The predicted PDIV values (PDIV PRE ) are in terms of the calibration factor, k, which predicts PDIV as a fraction of the theoretical breakdown voltage. The k-value incorporates practical aspects that can not be simulated such as material defects, manufacturing-related artifacts, excitation profile, and environmental aspects. The simulated DBC test coupon is then built physically with multiple identical samples for each trace gap to perform a statistical analysis. PDIV tests at 10 pC charge level are conducted on all the samples, and a Weibull statistical analysis is performed to determine the characteristic PDIV (PDIV EXP ) for each trace gap.
Juxtaposing the predicted PDIV vs. trace gap curve with the experimental PDIV vs. trace gap curve, the k-value can be found through regression analysis to close the offset. This work demonstrates this methodology using the example of a 12/25/12 mil alumina DBC and Dow Corning 3-6635 dielectric gel built in a university cleanroom facility.
Once the PDIV model is validated, the PDIV vs. trace gap curve can be used to determine the voltage class and trace gap design rules for the technology and manufacturing process selected. The PDIV vs. trace gap curve shows an expected trend of diminishing returns, which is validated through experiments. There is a point past which increasing the trace gap further will not have any PD-related benefit. This point of diminishing returns is quantified in terms of the trace gap and the corresponding PDIV value. For reliable operation, module voltage must not exceed this PDIV value.

III. PDIV MODEL DERIVATION FROM SURFACE CHARGE DENSITY SIMULATIONS
A modified power module building block was modeled in AN-SYS Maxwell 3D simulation software, and a surface-charge density-based PDIV model was derived. The 3D model geometry designed for the simulations matched the samples that were to be fabricated. The traces in Fig. 3 are marked A, B, and C. Traces B and C were held at ground potential, while Trace A was connected to a variable voltage with respect to ground. The voltage excitation on Trace A is the stimulus, and all responses, such as E-field in the trace-gap and surface charge density on the trace, are directly proportional to this excitation. Because of this relationship, the voltage was kept constant at 1 kV. Since the gap between the traces is measured in mm and the dielectric strength of materials is measured in kV/mm, the excitation on Trace A was measured in kV for ease of calculations.

B. PDIV DERIVATION FROM SIMULATIONS
The spatial point in the 3D model geometry where the response is measured is called the measurement point (MP). PD is stochastic and its actual location, onset voltage, exact magnitude, etc. are random. Because of its stochastic nature, it is impossible to predict exactly where PD will occur. The purpose of this work is to derive a working approximation of the voltage at which PD will begin, discussed next, without spatially locating the PD event exactly. However, there is general wisdom about where PD is likely to occur, and the measurement point location was chosen accordingly, and is described later in this section.

1) PDIV DETERMINATION FROM LOCAL E-FIELD
Most industrial designs factor in a safety margin off the breakdown voltage of the materials the insulation is made of. Since PD happens before breakdown, this margin may or may not incorporate PDIV. But it should be incorporated because, as shown before, PD is a silent and destructive phenomenon, and progressive PD leads to breakdown. Each insulation material has a dielectric strength prescribed in its datasheet, which tells us that under ideal conditions, if the E-field in the material exceeds that threshold, the material will break down. Often, with simple geometries, the breakdown voltage can be predicted using the V BD =E * d equation where E is the dielectric strength of the insulation material, d is the thickness of the insulation material between two parallel conducting plates, and V BD is the breakdown voltage. This only works for uniform E-fields. E-field in the insulation material may not be uniform. E-field may concentrate in certain regions due to various factors including intentional geometric features, geometric defects, material defects, etc. There is also a back side metal that influences the E-field distribution. The local E-field in an encapsulant material near a sharp metal edge or in a void inside an encapsulant is much higher than the E-field in the bulk of the insulation material. This is due to the concentration of surface charges at sharp corners [30] and the resulting E-field nearby, and due to the reduced permittivity in the void of the encapsulant compared to the bulk encapsulant, respectively. These regions become PD nucleation sites, and a much lower voltage across the insulation material would drive breakdown in those specific regions. Finding the voltage at which the E-field in these nucleation sites exceeds the bulk dielectric strength of the material is important in determining a better safety margin that incorporates the likelihood of PD. When the material breaks down only in a small local region of the larger insulation, it is a partial discharge. In this work, E LOCAL is defined as the E-field in such local regions of interest for a 1 kV applied voltage, E DS as the uniform dielectric strength of the bulk insulation material (as prescribed in its datasheet), and V BD,LOCAL as the applied voltage that pushes E LOCAL to the E DS threshold of the material, causing a local breakdown. We express this as: This local breakdown is essentially a partial discharge because it does not bridge the gap between the conductors. PD is a precursor to the actual breakdown of the entire encapsulant material, but V BD,LOCAL is a theoretical value based on simulations of perfect materials and geometries, and can not be considered as the PDIV. Also, the E DS value in the datasheet is based on ideal conditions; the actual dielectric strength of the material is much lower. Therefore, a practical assessment to help calibrate PDIV is needed. In this work, PDIV is assumed to be proportional to and a fraction of the theoretical breakdown voltage, V BD,LOCAL , and needs to be accounted for in the safety margin. This is expressed as: where k is the proportionality constant or calibration constant that represents the fraction of the local theoretical breakdown voltage at which partial discharge inception practically occurs. It incorporates physical aspects of materials and manufacturing, as well as operational factors such as the excitation profile and the environment. These factors are discussed in a later section.
In this study, E LOCAL was derived from the surface charge density on the adjacent metal trace, described later. In the following section, the decision on where to reliably measure a response is described.

2) MP LOCATION DETERMINATION
As mentioned before, E-field in the encapsulant is not uniform. It concentrates near sharp metal corners and in voids. Voids are randomly found in the encapsulant whereas sharp corners exist by design. Therefore, it is easier to model sharp edges. The etched profile of DBC traces contains sharp edges. Charges accumulate here, and the E-field in the encapsulant adjacent to these sharp edges is much higher than the E-field in the bulk encapsulant.
The TP is the most likely location for PD as shown in literature [21], [30]. However, in this work, the authors did not place the MP at or very close to the TP, or even in the trace gap, because: 1) the E-field and surface charge density at geometric sharp corners of conductors are theoretically infinitely high [30], 2) the gradients of E-field and surface charge density near geometric corners and triple points are extremely high, and 3) the mesh density at sharp corners is extremely high and inversely proportional to the trace gap size. The MP must be chosen carefully so that it reflects the effect of design parameters like trace gap on the E-field at the TP without being dominated by singularity effects of the physical phenomenon or numerical effects from the changing mesh density. To accommodate all these constraints, the authors avoided putting the MP in the trace gap within the insulating material, but rather on a conductive surface, away from any triple points, and in a place where the mesh density would be relatively more constant with the change of the trace gap while registering the effect of the trace gap. To get more consistent values by reducing the error due to the way the simulation works, the MP location was adjusted. Considering these constraints, the general location to place the measurement point, therefore, is on the vertical face of the higher potential trace that is next to the trace gap. To avoid the effect of singularities and to have a common reference point instead of one that changes with the design, the location chosen for this work for the MP is in the middle of the vertical face of the higher potential trace, facing the gap (Trace A in Fig. 4). This location for MP also offers versatility for various more complex designs including flip-chip or multi-layer geometries.
Since the MP is on a conductor (Fig. 4), surface charge density is the appropriate direct parameter to be measured, from which E-field can be derived. This derivation is described in the next section. The mesh around the MP is indirectly controlled. It is driven by the maximum number of mesh elements, the minimum size of the elements, and the convergence criteria. Performing a mesh analysis, these factors were varied for a 0.1 mm trace gap. Once a stable charge density output was reached, the mesh settings were kept the same for all other simulations of trace-gap variation. Controlling the mesh using these driving factors, any changes in the surface charge density response were primarily due to changes in the design parameter (trace gap) instead of the numerical noise.
There are limitations in representing PD through simulations. PD is usually assumed to be at the TP. But since simulations cannot predict the exact location where PD will happen because simulations cannot predict material defects, we must assume that PD will happen either in the encapsulant or in the ceramic close to the metal trace, and that the onset of PD is at a fraction of the theoretical breakdown voltage of that material. Even if breakdown happens in the TP, the E-field at the MP is still proportionate to the E-field in the TP according to simulations in this work. So, the simulations can capture the trend, if not the exact value. That is why the proportionality constant, k, is used to account for factors beyond the scope of this work and lab tests are used to calibrate simulation results with experimental data. The experiments validate the trend predicted by the simulations. The k-value can depend on the manufacturing quality of the materials which cannot be predicted by simulations.

3) LOCAL E-FIELD DERIVATION FROM SURFACE CHARGE DENSITY
According to Gauss's law, the electric flux across any closed surface is proportional to the net electric charge enclosed by that surface. Assuming a small bounding box is drawn around the MP, the net flux perpendicular to the box is equal to the net charge enclosed by the box. The physical meaning of the differential form of Gauss's law relates electric field to charge distribution. Using this concept, one can derive that the local E-field in the insulating material adjacent to the MP is proportional to the surface charge density over the conducting surface bounded by the imaginary box. (3) shows this relationship, where Q surf is the surface charge density at the MP in C/m 2 , E LOCAL is the calculated E-field in the insulating material adjacent to the MP in kV/mm, ε 0 is the permittivity of free space in F/m, and ε r is the relative permittivity of the encapsulant material. This is the response for an excitation of 1 kV.
E LOCAL is directly proportional to the excitation voltage, V a . As V a increases, E LOCAL scales proportionately. As discussed before, the V a for which E LOCAL reaches the threshold E-field of E DS is called the V BD,LOCAL . For electrical reliability, V a must stay well below the V BD,LOCAL threshold. In fact, it must stay below the PDIV threshold where partial discharges of a fixed charge level (typically 10 pC) begin. The k-value in (2) determines how far below V BD,LOCAL the PDIV threshold should be.
Another way to look at the k-value is as a ratio of the PD strength of the material and the breakdown strength of the material. Equation (4) shows one way to relate the E-fields. It is analogous to (2) where k is a ratio of the local breakdown voltage to the PD inception voltage of the material. Depicting it this way emphasizes that there is a threshold E-field below the traditional dielectric strength of the material, and this is the threshold being proposed as a design constraint in this work.
The k-value is a derating factor that is dependent on many factors including materials and manufacturing processes, simulation settings such as mesh density, and environmental factors such as temperature and pressure, etc. It helps calibrate the simulation settings to the experimental results for a specific material set, manufacturing process, excitation profile, and environment. The k-value thus determined can be transferable for reasonably similar materials, processes, excitation and environment. And, for a significantly different material set, manufacturing process, excitation profile and environment, the methodology presented in this work can be used to determine an appropriate k-value. This "k" is the same as the one in (2). This work shows an example of how to determine the kvalue for a simple test structure where the design parameter (in this case, trace gap) changes, while the materials remain the same, and the manufacturing, environmental factors, and simulation settings remain mostly the same, though not perfectly controlled since that is outside the scope of this work. The k-value accounts for mesh differences across data sets to relate the simulated E-field values to the practical breakdown strength.
FEA simulations were performed to determine the surface charge density at the MP. The local E-field was then derived from it using (3). The local breakdown voltage is determined by comparing the local E-field to the dielectric strength of the material, as in (1). Finally, the PDIV is determined by using hypothetical values of k applied to the local breakdown voltage, and later calibrated using experiments. Table 1 shows the various parameters that were varied and by how much. Some of the parameters affect the layout, while others affect the technology (the vertical stack of materials). Trace-gap is a parameter that affects the layout, and its limits define the design rules for the trace gap. The layer stack ( Fig. 1(a)) is usually pre-set by the user in the MDK before layout options are explored. For this example, a 12-25-12 mil Cu-Al 2 O 3 -Cu DBC and a Dow Corning 3-6635 dielectric gel were used as the technology. Their physical properties are mentioned in Table 1. The same materials were used for physical experiments to calibrate the k-value. For the scope of this work, the trace-gap was varied between 0.1 mm to 8.0 mm, and the surface charge density was recorded as the response. In the physical experiments, trace gap was varied between 1 mm and 3 mm to compare the trend of PDIV between the simulated and experimental cases.

5) LIMITATIONS
The simulations do not explicitly account for temperature, pressure, or other environmental factors. They only consider factors like trace gap and material thickness, and geometric features that are part of the designable parameters.

C. SIMULATION RESULTS AND PDIV CALCULATION
Constants were set as mentioned in Table 1, and the trace gap was varied. The surface charge density value on the MP was recorded. Fig. 5 depicts the surface charge density field plot and mesh density around the MP for a 1 mm trace gap. Using 20 kV/mm as the breakdown strength of the dielectric
The plot shows that as the trace gap increases, PDIV increases. This makes sense because E-field and surface charge density are inversely proportional to the gap between the conductors. However, according to the simulations, beyond a particular trace gap, there is practically no impact on the PDIV as the PDIV reaches almost a steady state. This, too, makes sense, as factors besides the trace gap dominate beyond this point. Since PDIV constrains the operating voltage, increasing the trace gap past this point has no benefit in terms of the operating voltage. Conversely, decreasing the trace gap below this point has significant implications for the operating voltage. This point of diminishing returns is specific to the technology and processes and must be determined experimentally. The next step in the methodology is to determine the k-value experimentally for the chosen technology set and manufacturing process.

IV. PDIV MODEL VALIDATION THROUGH EXPERIMENTS
To calibrate the PDIV model derived from simulations and validate the PDIV vs. trace gap trend, three different trace gap variations were chosen to be built and tested for PDIV at a 10 pC PD threshold. One of these points (1 mm trace-gap) was in the rising region of the curve in Fig. 6, while the other two (2 mm and 3 mm trace gaps) were in the steady-state region. Ten samples for each design variation were tested and analyzed statistically using Weibull plots according to IEC 62539 [35]. The experimental and predicted PDIV values were compared to determine the k-value. This section describes the fabrication, test setup, test results, and statistical analysis steps.

A. TEST STRUCTURE FABRICATION
Test coupons were built in-house at the university's High-Density Electronics Center (HiDEC) clean rooms. The thirty samples were built and processed in the same batch to minimize any differences in manufacturing. All dimensions of the samples matched those of the 3D model designed for simulation. The only design variation was the trace-gap.
To fabricate the samples, a 12/25/12 mil alumina DBC from Remtec was patterned on both sides using wet chemical etching. After dicing the DBC and cutting the FR4, the pieces were cleaned and attached using silver epoxy. A plastic housing was attached that held the gel dielectric. After bubble removal and gel curing, a completed sample is shown connected to the test setup in Fig. 7.

B. PARTIAL DISCHARGE TEST SETUP
The samples built were individually submerged in a bath of fluorinert dielectric fluid 3M FC-3283. Fig. 7 shows one of the 2 mm samples held down in a ceramic bowl by electrical tape  so that it does not float in the high-density fluid. The dielectric fluid is one among many measures to prevent arc formation. A kapton sheet was put between the terminals for additional protection. The terminals of the device under test (DUT) were connected using high voltage cables to the rest of the circuit. Figs. 8 and 9 show the partial discharge test circuit schematic and the high voltage (HV) area of the test bench, respectively. Omicron's MPD 800 PD tester was used to measure PD in the DUT and determine the PDIV. This equipment is specially designed for PD tests as it is sensitive enough to detect discharges much smaller than 1 pC and fast enough to detect the PD inception voltage.
For safety, the high voltage (HV) section of the test bench was kept isolated from the control bench. In Fig. 8, this section is marked off with dashed lines.
Voltage was applied with a pre-determined ramp rate. Fig. 10 shows the voltage profile that was used. The coupling capacitor stores the charge and supplies the energy needed in the DUT when a partial discharge occurs. The PD equipment calculates the apparent charge of the PD event by mathematically integrating the current supplied by the coupling capacitor to the DUT over time. The equipment records the charge and the voltage at which the PD occurs. PDIV, in this case, is the voltage at which a discharge of 10 pC happens for the first time. 10 pC is the recommended value for component level structures according to IEC 61287 [36]. The equipment was calibrated to measure PD accurately using Omicron MPD 800's calibrator. The calibrator injects a known amount of charge (10 pC, for example), and the measurement unit measures it accurately by applying a correction factor as needed. The maximum noise level for this test structure was less than 4 pC. IEC 60270 [11] recommends the noise level be no greater than half of the PD magnitude to ensure that the PD signal can be clearly distinguished from the noise. So, the noise level for a 10 pC measurement must be below 5 pC. This was ensured during each test.
A 30 kV 0.33 mA DC power supply with less than 4 pC of noise was used to energize the DUT. The power supply was programmed using LabView software. PD signals were transmitted from the MPD 800 to the control unit through fiber optic cables, and the real-time discharges were shown graphically on the monitor and recorded as text files.

C. EXPERIMENTAL RESULTS AND STATISTICAL ANALYSIS
Since PD is stochastic in nature, a statistical method needs to be used to determine PDIV over a given set of identical samples. IEC 62539 (Guide for the statistical analysis of electrical insulation breakdown data) recommends using the Weibull method for statistical analysis. A sample size of 10 is considered sufficient [35]. This work and others [31], [37] have used this standard successfully to make reliability predictions.
In the physical test, PD signals were captured over time as voltage was increased. An example graph of the raw data for one of the 1 mm trace gap test coupons is shown in Fig. 11. For this test, the PDIV was 6.83 kV, where the needle point graph shows the first needle point to cross the 10 pC threshold.
The test coupons described earlier were tested for partial discharge to determine the PD inception voltage for a  threshold PD level of 10 pC. The PDIV test results for each 1, 2, and 3 mm samples were plotted on Weibull probability plots, as shown in Fig. 12. Each dot represents the PDIV value of a single sample. The PDIV values are ranked, and their corresponding percent failure value is determined based on their position in the ranked list and the sample size [38]. A reference line (the straight line in the Weibull plots) can be drawn through these points, and the PDIV value for any percent failure can be determined. The PDIV value for the 63% failure point on the line represents the characteristic value or the scale value of the Weibull plot.
The characteristic PDIV values (or scale values) for the 1, 2, and 3 mm samples are listed in Table 3. For the 1 mm sample set, the characteristic value is 6.03 kV. This means that 63% of the samples are likely to reach their PDIV by 6.03 kV for a 10pC PD threshold level. The characteristic values of the 2 mm and 3 mm trace gap Weibull plots are 6.50 and 6.48 kV, respectively. This means that the general trend of PDIV over trace-gap is the same as shown in Fig. 6, where PDIV first increases with trace gap and stays steady beyond a particular trace gap. In this case, PDIV reaches a steady-state by a 2 mm trace-gap. The chosen data nodes (1 mm, 2 mm, 3 mm) sufficiently cover the gamut of manufacturing possibilities, because 1: More data nodes (such as 1.5 mm) will not eliminate the stochastic nature of PDIV, 2. The manufacturing error of 0.1 mm will become significant when testing more data points, example: the difference between 1.0 mm and 1.5 mm may be too close to differentiate because the manufactured gaps may be 1.1 mm and 1.4 mm, and 3. This is a reasonable expectation for the volume of fabrication and testing at a university research fabrication facility.
The natural dispersion of data is due to the stochastic nature of PD and is accounted for by the Weibull method of determining a mean value (called the characteristic value or scale parameter) and a spread quantity (called the shape parameter). The Weibull plots in Fig. 12 show some spread in the data for each trace gap set, quantified by the shape parameter. This parameter is analogous to the inverse of the standard deviation of a normal distribution. The higher the slope of the reference line, the larger the shape value and the narrower the data spread. The shape values of the 1 mm, 2 mm, and 3 mm trace gap samples are 5.26, 7.37, and 7.38 ( Table 3). The data spread is narrower for both the 2 mm and 3 mm data sets, compared to the 1 mm sample set. A large spread is the expected nature of reliability data. It can be attributed primarily to the stochastic nature of PD, and secondarily to some differences in manufacturing since no two samples can be perfectly identical. Numerous other factors can cause differences. Analyzing each is outside the scope of this article. Despite these differences, there is a trend in the characteristic values over the three design variations for a large enough sample size.
The curved lines in Fig. 12 indicate the 95% confidence bound lines of the data. So, for the 2 mm trace-gap Weibull probability plot, there is 95% confidence that the PDIV characteristic value is between 6.1 kV and 7.1 kV. For higher confidence levels, the voltage interval becomes larger.

D. MODEL VALIDATION AND DISCUSSION
The predicted PDIV values from Table 2 that were represented in terms of k can now be compared to the experimental  values to determine the k-value. Tables 4 and 5 show how the characteristic values from experiments are applied to obtain the best k-value for the PDIV model (k = 0.65 for 1 mm, and k=0.66 for 2 mm and 3 mm). k = 0.66 yielded the best fit for the PDIV model due to its lowest average error across all trace gaps and the least sum of squared residuals. Fig. 13 shows the predicted and experimental PDIV vs. trace gap curves overlayed on each other. The error bars represent the 95% confidence level on the characteristic value. The experimental values follow the diminishing returns trend seen with the prediction model. The values show a close match with k=0.66 for all the trace gaps. Fig. 14 shows the calibrated PDIV prediction model with k=0.66 for intermediate trace gap values. The point of diminishing returns is at 2 mm with a PDIV limit of 6.5 kV. This model informs us that for a 12/25/12 mil alumina DBC with Dow Corning 3-6635 gel encapsulant, the maximum operating voltage should be limited to 6.5 kV to prevent PD above 10 pC. Increasing the trace gap beyond 2 mm offers no additional benefit in terms of PD mitigation or increased operating voltage. It also means that below 2 mm, the max operating voltage should be reduced significantly. Considering these factors, 2 mm is the optimum trace gap to be maintained for maximum voltage benefit. This model, with its unique k-value, is applicable for the chosen technology set and manufacturing process. The k-value may be different for a different technology and manufacturing process and must be determined experimentally. The methodology presented here can be used to determine a model for predicting PDIV vs. trace gap for any technology and manufacturing process.
PDIV increases with increasing trace gap because surface charge density and E-field reduce with increasing trace gap. Beyond a particular trace gap, other factors dominate, and the charge density and E-field concentrate in those parts of the test structure, such as the ceramic. If the backside metal were not present, the PDIV would keep reducing following an inverse square law relationship as in Coulomb's law. This was evident in the experiments conducted by Wang, et al. [31]. With the backside metal, the least resistance path for PD changes from the lateral trace gap to the vertical gap through the ceramic beyond a particular trace gap. And since the ceramic thickness remains constant for a given technology, PDIV no longer changes past the diminishing returns point. It is important to note that the encapsulant and the ceramic material's dielectric constant and dielectric strength are other factors that come into play in determining the preferred path for partial discharge to happen. Which factor dominates is an ongoing investigation and is outside the scope of this article. Fig. 14 clarifies that there is a point of diminishing return beyond a particular trace gap for any given technology, and this point can be quantified using the methodology demonstrated.

V. CONCLUSION AND OUTLOOK
A novel charge density-based PDIV vs. trace-gap modeling approach has been developed, and a voltage class and optimum trace gap quantified for a DBC-encapsulant technology that was validated through PD tests. For a 12/25/12 alumina DBC with Dow Corning 3-6635 dielectric gel, the voltage class was 6.5 kV, and the trace gap was 2 mm. It was seen that extending the trace gap beyond 2 mm did not change the PDIV; it remained steady at 6.5 kV. This point of diminishing returns is a critical piece of information. It indicates the maximum operating voltage for PD prevention and the corresponding optimum trace gap to the designer. For smaller trace gaps, the serious trade-off with voltage is evident.
The methodology presented in this work included the derivation of PDIV from surface charge density simulations. The simulations creatively avoided the challenges presented by E-field-related singularity problems. The prediction model was then experimentally calibrated through statistical analysis, validating the PDIV modeling method and the PDIV vs. trace-gap trend.
Further development and application of this methodology can lead to several future work opportunities: Assessment and modeling of the conditions when PD happens in the ceramic versus in the encapsulant is an ongoing investigation by the authors.
Ongoing work also includes characterizing other material technologies (such as AlN and Si 3 N 4 substrates of varying thicknesses, epoxy encapsulants, and other gel encapsulants) for their voltage class and optimum trace gap at the point of diminishing returns and storing them in an MDK-type library. A good user design experience would let the designer constrain either the technology or the voltage class. The automation tool determines the other and then delivers various reliable layout options based on PD-aware design rules. Future work may involve controlling environmental factors such as temperature and pressure. The model presented here only accounts for design factors such as trace gap, material choice, and voltage class. Future work may include assessment of PDIV for various voltage profiles including unipolar square pulses and the effect of dv/dt. Since industrial processes have higher manufacturing consistency than a university lab process, samples taken off an industrial production line would have a smaller statistical spread in PDIV test results. Manufacturers can use this method to determine a more appropriate k-value for their unique processes. Such manufacturer and process-specific models could then be compared for further analysis. Manufacturers can characterize their novel materials using this method, storing their results in an MDK. Non-proprietary models can be populated into a growing MDK library across research labs and commercial fabrication facilities. The lab-developed open module package tested in this work is useful for demonstration of the model. Proprietary information of industrial modules like trace gaps and material details are not available to universities. So, testing actual industrial devices is outside the scope of this work. However, such information can be used in an industrial setting on actual industrial devices with different inception voltage ratings to further validate and generalize the model.
Reliability percentiles can determine safety margins for the operating voltage and % yield. The wet-etching profile on the otherwise vertical face of the metal traces can be challenging to model in an FEA tool but may provide further insight on PD mitigation. Dielectric behavior can be non-linear, which could also be accounted for. Design rules for the various PD mitigation strategies mentioned in Section I can be developed using a similar methodology. Design rules for different trace gap geometries can also be set. Design rules supplementary to creepage and clearance for the case of a module may be introduced to account for effects like surface charge dissipation for specially treated insulation materials. As research on PD in power modules advances, so must its incorporation into automation tools as design rules. This work introduces a new paradigm in power module design automation where PD-awareness is considered an integral part of the DRC framework for module reliability. This ensures that module reliability is addressed at the design stage of the life cycle of a power module. This work is a step toward the vision of having power module design-for-reliability fully automated. Innovation and research such as what is presented here can bring the design automation of power modules up to speed with that of wide bandgap devices, closing the technology gap.