A Review of Current-Limiting Control of Grid-Forming Inverters Under Symmetrical Disturbances

Grid-forming (GFM) inverters are recognized as a viable solution to increase the penetration of renewable energy in bulk power systems. However, they are physically different from synchronous generators in terms of overcurrent capability. To protect the power semiconductor devices and support the power grid under severe symmetrical disturbances, the GFM control systems should be able to achieve the following requirements: current magnitude limitation, fault current contribution, and fault recovery capability. Various current-limiting control methods are reported in the literature to fulfill these goals, including current limiters, virtual impedance, and voltage limiters. This paper presents an overview of those methods. Emerging challenges that need to be addressed, including temporary overcurrent, unspecified output current vector angle, undesired current saturation, and transient overvoltage, are pointed out. Comparative simulations are conducted to demonstrate the performance of different methods under grid voltage drops and phase jumps. Finally, open issues of current-limiting control methods for GFM inverters, including transient stability assessment, voltage source behavior under overcurrent conditions, and windup of voltage controllers, are shared.


INDEX TERMS
grid impedance between fault location and grid, in p.u.

I. INTRODUCTION
Grid-forming (GFM) inverter technology is treated as a promising solution for future bulk power systems with high penetration of renewable-energy power generation [1], [2].
Differing from conventional grid-following (GFL) inverters, GFM inverters are controlled as voltage sources behind impedance in normal operation [3], [4], and hence, they are able to establish system voltage and frequency autonomously [5], and have higher stability robustness in weak grid interconnections [6].
The voltage source behavior of GFM inverters makes their output currents highly dependent on external system conditions.Upon large disturbances such as voltage drops or phase jumps at the point of common coupling (PCC) [7], synchronous generators can, in general, supply 5-7 p.u. overcurrent [8], while semiconductor-based inverters can only handle 1.2-2 p.u. overcurrent typically [9], [10], which prevents them from maintaining the voltage profile as in normal operation [11].To successfully ride through these disturbances, appropriate current-limiting control methods are required for GFM inverters, which need to satisfy the following requirements [7], [12], [13], [14]: r Current magnitude limitation: The GFM inverter's phase current magnitude should be lower than its maximum allowed limit, e.g., 1.2-2 p.u., to protect the power semiconductor devices.
r Fault current contribution: The GFM inverter should supply required active/reactive currents to support the power grid during disturbances [13], e.g., supplying full reactive current when the PCC voltage falls below 0.5 p.u. [7].
r Fault recovery capability: The GFM inverter should be able to restore its normal operation when disturbances are cleared [13], e.g., restoring active power to 90% of its pre-fault value within 0.5 s after the disturbance clearance [14].To meet these requirements, various current-limiting control methods for GFM inverters are reported in the literature, including current limiters, virtual impedance, and voltage limiters.The current limiters usually make the inverter behave as a current source during overcurrent conditions, which can facilitate the regulation of the output current vector angle to meet the fault current contribution requirement.In comparison, the virtual impedance methods and voltage limiters can maintain the voltage source behavior of the GFM inverter to some extent during severe disturbances, which may allow for automatic fault recovery.This paper reviews those The remainder of this paper is organized as follows: Section II illustrates the basics of current-limiting control of GFM inverters.In Sections III-V, current limiters, virtual impedance methods, and voltage limiters are reviewed, respectively.Open issues are shared in Section VI.Finally, Section VII concludes this paper.

II. BASICS OF CURRENT-LIMITING CONTROL METHODS
Fig. 1 shows a simplified circuit model of a grid-tied GFM inverter.The GFM inverter consists of an internal voltage source v e and equivalent output impedance.The filter impedance will be included in Z e , if no inner-loop control is utilized.When inner-loop control is used, the filter impedance will not be included in Z e [24].
According to the Kirchhoff's circuit laws, the phase current magnitude of the GFM inverter can be expressed as where • denotes the modulus of a complex variable, j is the unit imaginary number.When a disturbance causes PCC voltage drop or phase angle jumps, the voltage difference v e − v PCC can increase.Consequently, I may exceed its maximum allowed value I M of the GFM inverter.
To prevent the GFM inverters from overcurrent tripping, various current-limiting control strategies are reported in the literature [25], [26].Based on how the current magnitude I is restricted, these strategies can be classified into three types: r Current limiter: GFM control restricts the phase cur- rent magnitude I within the maximum allowed value I M through closed-loop current control [27], [28], [29].
r Virtual impedance: GFM control adjusts the phase cur- rent magnitude I by increasing the total impedance Z e + jX T based on virtual impedance/admittance control methods [30], [31], [32].
r Voltage limiter: GFM control regulates the phase current magnitude I by reducing the voltage difference v e − v PCC via voltage limiters [33], [34].Comparisons of different methods in terms of current limitation performance, fault current controllability, and fault recovery capability are illustrated in Table 1, which will be discussed in detail in the following sections.
Fig. 2 illustrates a general control diagram of a GFM inverter furnished with current-limiting control methods.The control system is composed of two control layers, i.e., the outer-loop control layer and the inner-loop one.The main objective of the outer-loop control is to synchronize the GFM inverter with the power grid and regulate the terminal voltage magnitude.A voltage magnitude E and phase angle θ will be generated based on the active and reactive power references P re f , Q re f , voltage and angular frequency references V re f , ω re f , and the feedback variables i, i g , v t , v PCC .The innerloop control aims to produce the voltage modulation reference v PW M from v re f and θ generated by the outer-loop control.It is worth noting that the inner-loop control may not be always needed for GFM controls.

III. CURRENT LIMITER
The current limiter is usually embedded in the inner-loop control layer as noted in Fig. 2. Its principle is to restrict the original current reference i re f generated from the voltage vector control or virtual admittance control to a saturated one īre f satisfying īre f ≤ I M .Thereafter, current controllers are utilized to realize i = īre f , and thus achieves I ≤ I M .

A. INSTANTANEOUS LIMITER
The illustration of an instantaneous limiter is shown in Fig. 3(a), which utilizes an element-wise saturation function to achieve a saturated current reference īre f .

VOLUME 3, 2022
The instantaneous limiter can be implemented in different reference frames [17], [27], [35], [36], expressed as where x = a, b, c/d, q/α, β denotes the axis in the corresponding reference frame.In the natural reference frame (abc-frame), the current limit I M,x is equal to I M .In the stationary (αβ-frame) or synchronous (dq-frame) reference frame, the current limit I M,x is usually selected as I M / √ 2 to ensure that ī2 re f ,d/α + ī2 re f ,q/β ≤ I M .

B. MAGNITUDE LIMITER
The illustration of a magnitude limiter is given in Fig. 3(b), which only decreases the magnitude of the original current reference i re f .The angle of īre f maintains the same as that of i re f .The magnitude limiter is originally designed in the αβframe or dq-frame [28], [37], [38] and further extended to a generalized one in the abc-frame [39], [40], which can be expressed as with I re f ,x representing the magnitude of i re f ,x , and x = a, b, c/d, q/α, β.

C. PRIORITY-BASED LIMITER
Fig. 3(c) shows the principle of the priority-based limiter, which not only decreases the magnitude of i re f but also prioritizes its angle to a specific value φ I .Notice that φ I is a user-defined angle that represents the angle difference between īre f and the d-axis oriented to θ .The priority-based limiter implemented in the dq-frame is represented as [15], [29], [41], [42] In [29], [41], φ I = 0 is selected.Further, −π/2 < φ I ≤ 0 is chosen in [42] based on an optimized method with improved transient stability.In [43], [44], φ I is selected to be as close as possible to the pre-fault angle of i to mitigate current transients upon the disturbance inception.

D. PERFORMANCE COMPARISONS OF CURRENT LIMITERS
All these three current limiters can achieve satisfactory current magnitude limitation under severe disturbances.However, they can suffer from transient overcurrent caused by the current control loop dynamics.Among the three current limiters, the instantaneous limiter is the simplest one to achieve the overcurrent protection of GFM inverters.However, when it is implemented in the abc-frame and αβ-frame, the inverter output current i can become non-sinusoidal due to the clipping of the current reference [39].Furthermore, as shown in (2), in the αβ-frame and dq-frame, conservative current limits may be needed, which can reduce the capacity utilization of the GFM inverter and requires the use of inverters with a relatively large I M , e.g., 2 p.u. in [27], [36].Compared with the instantaneous limiter, the magnitude limiter and the priority-based one can ensure a sinusoidal output current i with extra current magnitude calculations, and fully utilize the overcurrent capability of the inverter during severe symmetrical disturbances.
In addition to the current magnitude limitation, these current limiters generally have difficulties in meeting the fault current contribution objective required by grid codes.When the current limiter is triggered, the inverter terminal voltage may not be aligned with the d-axis oriented to θ .Consequently, the angle difference between i and v t cannot be specified to meet the fault current contribution requirement [7], [13].To deal with this issue, one method is to switch the GFM inverter to a phase-locked loop (PLL-)synchronized GFL inverter [15], [37], [45].However, the PLL can suffer from small-signal or transient instability issues under weak grid conditions [46], [47].An alternative solution that avoids switching the synchronization methods is to adjust the active and reactive power references based on grid codes [16], [48], [49], which are further tracked by power control loops to achieve the fault current contribution goal [50].An example based on [7] is given as and , where V PCC = v PCC , I Q denotes the reactive current requirement of the power grid when the PCC voltage is between 0.5 p.u. and 0.9 p.u.
Furthermore, as shown in Fig. 2, once these current limiters are triggered, the inverter phase current magnitude will be fixed at I M .Therefore, the voltage vector controller and the voltage magnitude controller cannot adjust the inverter terminal voltage magnitude V t to its reference value [11].The windup of these voltage controllers may further result in a current reference i re f whose magnitude is larger than I M .Consequently, undesired current saturation occurs, which prevents the inverter from successful fault recovery [19].Extra anti-windup designs are required for these voltage controllers to address this issue when current limiters are utilized.

E. CASE STUDY
Simulation tests of the magnitude limiter and the prioritybased limiter with φ I = 0 are conducted to demonstrate their performance during severe symmetrical disturbances.The control structures in [19], [51] are utilized.During the disturbances, the power references are adjusted according to (5).The system and control parameters are given in Appendix.To test the fault current contribution performance of the current limiters, a 0.8 p.u. grid voltage drop is utilized.Further, a −60 • grid voltage phase jump, i.e., the angle difference between the internal voltage source of the GFM inverter and the grid voltage increases by 60 • , is simulated to test the disturbance ride-through capability of these current limiters.In Figs.4-6, the performance of the two current limiters under the grid voltage drop disturbance is given.From Fig. 4, one can notice that both current limiters can restrict the inverter phase currents to 1.2 p.u.The active and reactive current responses are depicted in Fig. 5.One can see that the supplied reactive current amount (i q ) can meet the grid code requirement [7].However, since the angle difference between i and v t is regulated by the power control loop whose bandwidth is typically below 50 Hz [52], the inverter has difficulty in meeting the fault current response speed required by grid codes [7].The inverter terminal voltage responses are shown in Fig. 6.When the grid voltage drop is cleared, transient overvoltage around 1.2 p.u. occurs since the inverter still injects a large  amount of reactive current to the grid that lifts up the terminal voltage [53].

2) GRID VOLTAGE PHASE ANGLE JUMPS BY −60 •
The results after the grid voltage phase angle jumps are shown in Figs.7-9.As depicted in Fig. 7, both current limiters can quickly restrict the inverter phase current magnitude to 1.2 p.u.When the magnitude limiter is utilized, a temporary overcurrent with a peak value of 1.3 p.u. for about 1 ms occurs due to the severe phase jump disturbance and the current control loop dynamics.When the disturbance is cleared, unlike the magnitude limiter that can restore normal operation automatically, the priority-based limiter cannot successfully ride through the phase jump disturbance due to the windup  of the voltage controller, though it ensures transient stability.
The phase current magnitude is always kept at 1.2 p.u. since i re f > I M .Moreover, according to the active current responses in Fig. 8, the GFM inverter with both current limiters needs to absorb active power from the power grid for more than 0.3 s, which is not permitted for certain GFM inverters, e.g., the Type-IV wind turbines.Additionally, the inverter will inject a large amount of reactive current during the fault recovery process, the inverter terminal voltage can be lifted up to 1.4 p.u. as shown in Fig. 9, which can trip the inverter.

IV. VIRTUAL IMPEDANCE
The virtual impedance methods aim to increase the impedance Z e + jX T to limit the phase current magnitude as shown in Fig. 1.Three typical virtual impedance implementation methods are demonstrated in Fig. 10.The corresponding equivalent circuit diagrams of these methods are given in Fig. 11.

A. VIRTUAL IMPEDANCE WITH INNER-LOOP CONTROL
The virtual impedance with inner-loop control is implemented in [18], [30], [31], [54], [55], [56], [57] for current limitation based on the assumption that v t = v re f can be fast realized by the voltage control loop.An equivalent circuit diagram of this method is demonstrated in Fig. 11(a).
In this method, the virtual impedance is added to v re f when the phase current magnitude I is greater than a certain threshold I thres , i.e., (6) with R v and X v being the virtual resistance and reactance, respectively.A typically selection method for R v and X v is expressed as follows [18], [31], [54], [55] where σ is a user-defined X/R ratio for the virtual impedance, K V I is a constant that satisfies with V max being the expected maximum magnitude of the voltage difference between E e jθ and v t .

B. VIRTUAL IMPEDANCE WITHOUT INNER-LOOP CONTROL
The virtual impedance without inner-loop control is presented in [32], [58], whose equivalent circuit diagram is demonstrated in Fig. 11(b).Notice that in this method, the virtual impedance is directly added to the voltage modulation reference v PW M when the phase current magnitude I is greater than I thres .
Different from the previous method, the inverter filter will be in series with the virtual impedance as shown in Fig. 11(b) [24], [59].Again, R v and X v can be selected similarly to (8) [58], satisfying

C. VIRTUAL ADMITTANCE
The virtual admittance control method shown in Fig. 10 is applied in [60], [61] for current limitation.The corresponding equivalent circuit diagram is given in Fig. 11.
Compared with the aforementioned two virtual impedance methods that require a derivative controller to achieve a virtual inductor L v [32] or uses an virtual reactor X v at the nominal frequency, the virtual admittance method can achieve a virtual inductor L v within the bandwidth of the current control loop.The virtual admittance method cannot have R v = L v = 0 in normal operation, whose selection may not follow (8) directly.Alternatively, the virtual admittance can be selected as [60], [61] where Z v = E e jθ − v t /I M , R vn and L vn are the virtual admittance parameters in normal operation, ω n is the nominal angular frequency.In [16], the virtual admittance parameters are suggested to be chosen as R vn = 0.1 p.u. and L vn = 0.3 p.u.

D. PERFORMANCE COMPARISONS OF VIRTUAL IMPEDANCE CONTROL METHODS
The virtual impedance method that directly modifies the voltage modulation reference and the virtual admittance method with a fast-tracking current control loop can achieve good current limitation performance when severe disturbances occur [23].In comparison, the virtual impedance method with inner-loop control achieves current limitation based on the hypothesis that the voltage reference v re f can be fast tracked by the voltage control loop.Since the bandwidth of the voltage control loop is relatively low [62], temporary overcurrent may be observed [63].To deal with this issue, hybrid currentlimiting methods that combine the virtual impedance with the priority-based current limiter [63] and the current magnitude limiter [64] are presented.
To achieve effective current magnitude limitation with the three virtual impedance methods, the control parameters R v and X v (L v ) are highly dependent on the magnitude of the voltage difference between E e jθ and v t , which introduces a tradeoff between current limitation and stability [18], [20], [21], [22].For the parameter selection method expressed by (8), current limitation can be achieved if the condition V max ≥ E e jθ − v t holds.On one hand, when using a small V max , the phase current magnitude I cannot be ensured to be within I M when E e jθ − v t is larger than V max .On the other hand, when using a large V max , according to (8), large R v and X v will be applied, which can induce instability issues.The instability problem also exists in the parameter selection method in (10), which requires large R v and L v when E e jθ − v t increases.
As shown in Fig. 11, the inverter under disturbances behaves as a voltage source behind adaptive impedance.The output current vector angle will be determined by the voltage difference (E e jθ − v t ) and the X/R ratio of the virtual impedance if only the virtual impedance methods are used.To meet the fault current contribution requirement, a proper design of the X/R ratio is thus needed.An alternative solution that can relax this parameter selection requirement is to combine the virtual impedance methods with the power reference adjustment method in (5) [23].However, the voltage source behavior of the inverter can be lost.
Besides, from Figs. 2 and 10, it is noticed that these virtual impedance methods will not introduce windup problems to the inner-loop current and voltage controllers, whose fault recovery capability is thus better than that of the current limiters [65], [66].However, anti-windup control designs are still required for the outer-loop voltage magnitude controller to ensure the fault recovery capability of the GFM inverter.

E. CASE STUDY
Simulation tests of the virtual impedance with inner-loop control [65] and without inner-loop control [20] are conducted.Again, the system and control parameters in Appendix are used.The virtual impedance parameters calculated according to (8) with V max = 1 p.u. are listed in Table 2. Two disturbances including a 0.8 p.u. grid voltage drop and a −60 • grid voltage phase jump are simulated.

1) GRID VOLTAGE DROPS TO 0.2 P.U. FOR 100 MS
The results of these two virtual impedance methods with an X/R ratio of 5 are depicted in Figs.12-14.As shown in Fig. 12, a temporary overcurrent with a peak value of 1.5 p.u. for 3 ms occurs upon the grid voltage drop.When the disturbance is cleared, a temporary overcurrent with a peak value of 1.4 p.u. occurs again.These overcurrent phenomena are mainly induced by the transient dc component in phase currents [23].Moreover, during the grid voltage drop, the phase current magnitude is less than 1.2 p.u. since E e jθ − v t < V max holds.The GFM inverter with these two virtual impedance methods cannot fully utilize its overcurrent capability.The active and reactive current trajectories are given in Fig. 13.By virtue of the maintained internal voltage source behavior, the inverter can supply 1 p.u. reactive current within about 6 ms after the grid voltage drops with an appropriate selected X/R ratio.However, both virtual impedance methods require more than 2 s to exit the current-limiting mode.Finally, the terminal voltage profiles are given in Fig. 14, one can notice that a slight overvoltage with a peak value of 1.06 p.u. occurs.Afterward, the terminal voltage can be kept with in 1 p.u.

2) GRID VOLTAGE DROPS TO 0.2 P.U. FOR 200 MS
The results with an X/R ratio of 5 are depicted in Figs.15-17.As demonstrated in Fig. 15, a temporary overcurrent with a peak value of 1.5 p.u. occurs when the grid voltage drops and the disturbance is cleared.During the fault recovery process, the current magnitude limitation is compromised again since the required condition for the virtual impedance methods, i.e., E e jθ − v t ≤ V max , is violated.The corresponding active and reactive current trajectories are depicted in Fig. 16.One can notice that the inverter needs about 1.2 s to recover from the disturbance and has to withstand negative active power from the power grid for more than 0.3 s.The terminal voltage   trajectories are given in Fig. 17.It can be seen that the inverter terminal voltage can be well maintained within 1 p.u. during the low-voltage ride-though process.
Next, the results with a decreased X/R ratio to 0.2 are given in Figs.18-20.One can notice that the virtual impedance with inner-loop control becomes unstable when grid voltage drops.Comparing Fig. 15(b) with Fig. 18(b), one can notice that the temporary overcurrent upon the grid voltage drops decreases to 1.3 p.u. due to the increased virtual resistance to damp the dc component in phase currents.However, temporary overcurrent still occurs during the fault recovery process since E e jθ − v t > V max .In Fig. 19, the active and reactive   current trajectories of the two virtual impedance methods are given.During the voltage drop disturbance, one can notice the inverter can again deliver reactive current to the power grid quickly with the help of the internal voltage source behavior.However, its peak value is reduced due to the decreased X/R ratio.Moreover, the inverter needs about 0.5 s to restore its normal operation.From Fig. 20, one can notice that a transient overvoltage of 1.2 p.u. happens due to the undesired reactive current contribution when the voltage drop is cleared.

3) GRID VOLTAGE PHASE ANGLE JUMPS BY −60 •
The results when a large grid voltage phase angle jump occurs are shown in Figs.21-23.The X/R ratio for the virtual impedance is selected as 5. Again, the virtual impedance with inner-loop control becomes unstable during the disturbance ride-through process.As demonstrated in Fig. 21, one can notice that a large transient overcurrent with its peak value of 1.8 p.u. happens upon the phase angle jumps.Besides, since E e jθ − v t ≤ V max is violated again, the current limitation objective is jeopardized.As shown in Fig. 22, the GFM inverter requires a period of about 1 s to recover from the large  phase jump, while the terminal voltage can be maintained with in 1 p.u. as illustrated in Fig. 23.

V. VOLTAGE LIMITER
Voltage limiters aim to directly reduce the voltage difference v PW M − v t to be smaller than Z f I M [33], [34], [67], [68], which modifies the voltage reference generated by the outerloop control to realize current magnitude limitation as shown in Fig. 2.This method is a suggested solution in [7] since it does not require adaptive virtual impedance that can destabilize the system under certain conditions [20].For the voltage limiters, the inner-control loop is commonly transparent, i.e., v PW M = v re f .Subsequently, an equivalent circuit diagram of this current-limiting method can be expressed as in Fig. 24.
The implementation of the voltage limiter is usually achieved by regulating E and θ generated by the outer-loop control, expressed as [33], [34] where θ t is the phase angle of v t , E lim and δ lim are maximum allowed magnitude difference and angle difference, respectively, which are selected to ensure that v re f − v t ≤ Z f I M .Notice that this type of voltage limiter can be implemented without the magnitude and angle information of i as the other current-limiting methods.However, it requires extra information of the terminal voltage v t , such as its phase angle θ t [33] and magnitude V t [34].
In [67], [68], a voltage limiter is directly designed in the abc-frame where the voltage limits are calculated based on each phase current.This type of voltage limiter is simple in implementation, yet introduces non-sinusoidal phase currents like the instantaneous current limiter.
Besides, to ensure the fault recovery capability, anti-windup designs for outer-loop controllers are required due to the saturation of the control signals E and θ .When both E and θ are saturated as in ( 11)-( 12), the voltage reference v re f has to follow the change of its terminal voltage v t .The output current will become i = [(V t ± E lim )e j(θ t ±δ lim ) − V t e jθ t ]/Z f .Appropriate design of control parameters E lim and δ lim is needed to meet the fault current contribution requirement.

A. CASE STUDY
Simulation tests of the voltage limiter in (11) and ( 12) are performed.The system and control parameters in Appendix are used.The parameters for the voltage limiter are δ lim = 0.05 rad/s and V lim = 0.033 p.u. Two disturbances including a 0.8 p.u. grid voltage drop and a −60 • grid voltage phase jump are simulated.The corresponding results with the voltage limiter when grid voltage drops are shown in Fig. 25-27.From Fig. 25, one can notice that a temporary overcurrent with a peak value of 2 p.u. for 20 ms occurs due to the lack of active/passive damping.Afterward, the phase current magnitude can be well maintained within 1.2 p.u. From Fig. 26, one can notice that with the help of the partially maintained voltage source behavior, the inverter can supply reactive current required by grid code quickly upon the voltage drop.However, the inverter needs more than 1 s to restore its normal operation.The inverter terminal voltage during the low-voltage ride-through process can be well maintained within its allowed operating range as shown in Fig. 27.

2) GRID VOLTAGE PHASE ANGLE JUMPS BY −60 •
The performance of the voltage limiter when the grid voltage phase angle jumps by −60 • is depicted in Figs.28-30.Again, from Fig. 28, due to the lack of damping, a large temporary overcurrent of 2 p.u. happens upon the disturbance inception.Further, as shown in Fig. 29, the inverter maintains its currentlimiting mode for more than 1 s after the phase jump.Finally, again, the inverter terminal voltage during the disturbance ride-through process can be well maintained within 1 p.u. as shown in Fig. 30.
For comparison, the simulation results of all case studies are summarized in Table 3.
Although all details of the inverter nonlinear dynamics can be included in the numerical methods for stability assessment, significant computational resources will be required for the stability analysis of a power grid with high penetration of GFM inverters.Moreover, the numerical simulations fail to shed analytical insights into the impacts of control loops.
Besides the numerical method, nonlinear system theory is also used to analyze the stability of GFM inverters, such as bifurcation theory [74], Lyapunov theory [75], phase plane analysis [23], [42], [76], [77], [78], [79], etc.The advantage of these theoretical methods is that they can guide the selection of control parameters [42].However, these results are hard to extend to the transient stability assessment of multiple GFM inverters under overcurrent conditions.
For a power grid with multiple GFM inverters, due to its complex dynamic model, transient stability is hard to be assessed either theoretically or numerically.One possible way is to develop simplified models for transient stability assessment.In general, a GFM inverter with limited output current can be modeled as a synchronized current source with fixed or state-dependent phase current magnitude or a synchronized voltage source with a nonlinear output impedance.However, the nonlinear impedance in these models introduces timevarying parameters into the electrical network, which may make the conventional transient stability assessment methods based on fixed network model invalid.How to assess the transient stability of multiple GFM inverters with time-varying electrical network parameters is still a challenging issue.

B. VOLTAGE SOURCE BEHAVIOR UNDER OVERCURRENT CONDITIONS
With current-limiting controls, the GFM inverter cannot maintain its normal voltage source behavior under overcurrent conditions.Fortunately, although the GFM inverter's phase current magnitude is limited, its vector angle can still be adjusted freely.
The first method is to precisely regulate the output current vector angle to make the inverter behave as a PLLsynchronized current source [15], [45], [80] or a powersynchronized current source [29], [81].Such a method can easily achieve the current magnitude limitation and fault current contribution [14] objectives by setting the active and reactive current references according to grid codes under disturbances [16].However, this method may require extra mode-switching mechanism to restore normal operation when disturbances are cleared since the GFM inverter loses its voltage source behavior during the severe disturbances.
Notice that the voltage source behavior of a GFM inverter is more demanded than the precise control of the output current vector angle.In other words, during severe disturbances, the output current vector angle can be indirectly adjusted through  the regulation of an internal voltage source and the equivalent output impedance such as the virtual impedance methods and voltage limiters.Such kinds of methods can improve not only the fault recovery capability of the inverter but also the speed of the output current response.A recently implemented grid code [7] requires the GFM inverters to begin injecting reactive current to the power system in less than 5 ms when the PCC voltage drops below 0.9 p.u.In such a small timescale, it seems to be a better choice to keep the voltage source behavior of GFM inverters to some extent during disturbances with a natural current response than to directly control the output current vector angle of the GFM inverter [11].However, how to generate the magnitude and phase angle for the voltage source during severe disturbances, which satisfy the current magnitude limitation and fault current contribution requirements with ensured stability, is still an open issue.

C. WINDUP OF VOLTAGE CONTROLLERS
A successful disturbance ride-through process requires that GFM inverters should be able to restore their normal operation from the current-limiting mode when disturbances are cleared [13], [52].All control loops should be able to resume their status in normal operation automatically.One main challenge in the fault recovery process is caused by the windup of voltage controllers including the voltage vector controller and the voltage magnitude controller.When disturbances occur, the inverter terminal voltage has to drop to reduce the inverter phase current magnitude [11].Therefore, these voltage controllers will suffer from the windup issues.
To solve the fault recovery issue induced by voltage controller windup, appropriate anti-windup methods should be designed for GFM inverters.In addition to the commonly used methods, such as back-calculation, clamping, etc., novel anti-windup algorithms for different current-limiting controls may be developed to help GFM inverters recover from the undesired current saturation.For example, in [51], the integrator of the voltage vector controller is set to zero when the current magnitude limiter is triggered to improve the fault recovery capability of the GFM inverter.In [76], [82], the outer-loop controllers are re-designed for priority-based current limiters to avoid the windup of the voltage vector controller.However, the application of these methods are limited to specified innerloop and outer-loop control structures and system parameters.Once the control structure or system parameter changes, such as adding or removing feedforward terms or changing the grid impedance, those methods may lose their effectiveness.The anti-windup methods for voltage controllers that guarantees the inverter fault recovery capability is still missing in the literature.

VII. CONCLUSION
This paper presents an overview of the existing currentlimiting control methods for grid-forming (GFM) inverters under severe symmetrical disturbances, including current limiters, virtual impedance, and voltage limiters.The performance and challenges of these methods in satisfying the current magnitude limitation, fault current contribution, and fault recovery objectives during the disturbance ride-through process are discussed and demonstrated by comparative simulations under grid voltage drops and phase jumps.
Among these methods, the current limiters can meet the fault current contribution requirement by adjusting current or power references but may fail to recover from severe disturbances.In comparison, the virtual impedance methods and 966 VOLUME 3, 2022

FIGURE 1 .
FIGURE 1. Simplified circuit model of a GFM inverter under fault.

FIGURE 5 .FIGURE 6 .
FIGURE 5. Fault current contribution with the current limiters when the grid voltage drops to 0.2 p.u. from 0 s to 0.2 s.

FIGURE 8 .FIGURE 9 .
FIGURE 8. Fault current contribution with the current limiters when the grid voltage phase angle jumps by −60 • at 0 s.

FIGURE 10 .
FIGURE 10.Comparisons of different virtual impedance control methods: (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control; (c) virtual admittance.VCO: voltage-controlled oscillator.

FIGURE 11 .
FIGURE 11.Equivalent circuit diagram of different virtual impedance control methods: (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control; (c) virtual admittance.

FIGURE 12 .
FIGURE 12. Inverter phase current when the grid voltage drops to 0.2 p.u. from 0 s to 0.1 s.The virtual impedance X/R ratio is 5 (σ = 5): (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control.

FIGURE 13 .
FIGURE13.Fault current contribution with the virtual impedance when the grid voltage drops to 0.2 p.u. from 0 s to 0.1 s.The virtual impedance X/R ratio is 5 (σ = 5).

FIGURE 14 .
FIGURE 14. Inverter terminal voltage when the grid voltage drops to 0.2 p.u. from 0 s to 0.1 s.The virtual impedance X/R ratio is 5 (σ = 5): (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control.

FIGURE 15 .
FIGURE 15.Inverter phase current when the grid voltage drops to 0.2 p.u. from 0 s to 0.2 s.The virtual impedance X/R ratio is 5 (σ = 5): (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control.

FIGURE 16 .
FIGURE16.Fault current contribution with the virtual impedance when the grid voltage drops to 0.2 p.u. from 0 s to 0.2 s.The virtual impedance X/R ratio is 5 (σ = 5).

FIGURE 17 .
FIGURE 17. Inverter terminal voltage when the grid voltage drops to 0.2 p.u. from 0 s to 0.2 s.The virtual impedance X/R ratio is 5 (σ = 5): (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control.

FIGURE 18 .
FIGURE 18. Inverter phase current when the grid voltage drops to 0.2 p.u. from 0 s to 0.2 s.The virtual impedance X/R ratio is 0.2 (σ = 0.2): (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control.

FIGURE 19 .
FIGURE19.Fault current contribution with the virtual impedance when the grid voltage drops to 0.2 p.u. from 0 s to 0.2 s.The virtual impedance X/R ratio is 0.2 (σ = 0.2).

FIGURE 20 .
FIGURE 20.Inverter terminal voltage when the grid voltage drops to 0.2 p.u. from 0 s to 0.2 s.The virtual impedance X/R ratio is 0.2 (σ = 0.2): (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control.

FIGURE 21 .
FIGURE 21.Inverter phase current when the grid voltage phase angle jumps by −60 • at 0 s.The virtual impedance X/R ratio is 5 (σ = 5): (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control.

FIGURE 22 .
FIGURE 22. Fault current contribution with the virtual impedance when the grid voltage phase angle jumps by −60 • at 0 s.The virtual impedance X/R ratio is 5 (σ = 5).

FIGURE 23 .
FIGURE 23.Inverter terminal voltage when the grid voltage phase angle jumps by −60 • at 0 s.The virtual impedance X/R ratio is 5 (σ = 5): (a) virtual impedance with inner-loop control; (b) virtual impedance without inner-loop control.

FIGURE 24 .
FIGURE 24.Equivalent circuit diagram of voltage limiters with v ref being a saturated voltage reference.

FIGURE 25 .FIGURE 26 .FIGURE 27 .
FIGURE 25.Inverter phase current with the voltage limiter when the grid voltage drops to 0.2 p.u. from 0 s to 0.2 s.

1 )
GRID VOLTAGE DROPS TO 0.2 P.U.FOR 200 MS

FIGURE 28 .FIGURE 29 .FIGURE 30 .
FIGURE 28.Inverter phase current with the voltage limiter when the grid voltage phase angle jumps by −60 • at 0 s.
-forming (GFM) inverter, current-limiting control, current magnitude limitation, fault current contribution, fault recovery capability.PCC PCC voltage, in p.u. V PCC PCC voltage magnitude, V PCC = v PCC , in p.u. v PW M voltage modulation reference, in p.u. Fault fault impedance between the cable and the ground, in p.u. Z f inverter filter impedance, in p.u. Z g1 grid impedance between PCC and fault location, in p.u. Z g2 q inverter output reactive current, in p.u. i re f output current reference, in p.u. īre f saturated output current reference, in p.u. P inverter output active power, in p.u. P re f inverter output active power reference, in p.u. Q inverter output reactive power, in p.u. V re f voltage magnitude reference, in p.u. ω re f angular frequency reference, in rad/s.X T transformer reactance, in p.u. Z e equivalent output impedance, in p.u. Z

TABLE 4 .
System Parameters

TABLE 5 .
Control Parameters voltage limiters can allow for automatic fault recovery.But their control parameters should be appropriately selected to supply the grid code required fault current.Moreover, temporary overcurrent and transient overvoltage are observed in the simulation results, which need to be suppressed for GFM inverters.Finally, open issues including transient stability assessment, voltage source behavior under overcurrent conditions, and windup of voltage controllers, are shared.