Single-Phase PFC Rectifier With Integrated Flying Capacitor Power Pulsation Buffer

Single-phase Power Factor Correction (PFC) rectifiers with sinusoidal grid currents are inherently subject to an input power fluctuating at twice the mains frequency. In order to potentially mitigate bulky, heavy and failure-prone electrolytic dc-link capacitors, active Power Pulsation Buffer (PPB) concepts are proposed in the literature. For converter systems employing Flying Capacitor (FC) multilevel bridge-legs, the FCs can be utilized as a twice-mains frequency energy storage, i.e., as an integrated active PPB without the need for additional power components. Such ac-dc-stage-integrated FC PPBs capable of buffering the complete input power variation are known in literature which, however, require sophisticated control strategies with varying switching frequency and discontinuous conduction mode. This paper presents a novel ac-dc-stage-integrated FC-PPB approach which is compatible with standard PFC control concepts and enables a significant reduction in dc-link voltage variation. First, a control concept cycling the FC voltage in a wide range without interfering with the grid current controller is derived step by step and verified by means of circuit simulations. Design guidelines for the calculation of suitable FC capacitance values are presented and the limits in buffering capability are discussed. The concept is then experimentally verified with a 2.2 kW three-level FC single-phase PFC rectifier employing 600 V GaN power semiconductors where the dc-link voltage variation is reduced by 28% compared to conventional operation. Last, the applicability of the ac-dc-stage-integrated FC-PPB concept to other FC converter topologies is discussed.


I. INTRODUCTION
Single-phase Power Factor Correction (PFC) ac-dc converter systems are employed in applications such as solar inverters, or server power supplies. When operating with unity power factor, the system is subject to an input power p ac comprising an inherent twice-grid frequency 2 f ac = 2ω ac 2π power pulsation p ac (t ) = 1 2Û acÎac − 1 2Û acÎac cos(2ω ac t ), whereÛ ac andÎ ac are the amplitudes of the grid voltage and current, respectively. Hence, the converter system is required to comprise low (twice-fundamental) frequency energy storage elements. In the most simple case, a large electrolytic dc-link capacitor buffers the pulsating input power, where the required capacitance value C dc depends on the admissible low-frequency peak-to-peak capacitor voltage variation U dc . However, as can be seen in [1] the electrolytic dclink capacitor of a single-phase PFC rectifier system occupies a substantial fraction of the converter volume. Moreover, electrolytic capacitors have limited lifetime, which is further reduced by large dc-link voltage variations U dc [2].
Aiming at ever more compact systems, active Power Pulsation Buffer (PPB) concepts are employed in literature [3], [4]. There, a dedicated circuitry covers the power pulsation, hence allowing for a significantly reduced dc-link capacitor value. Typically, film or ceramic capacitors are employed in an active PPB due to the high resulting voltage (current) swing. The main disadvantage of a conventional active PPB is the required additional power components, the elevated system complexity, and a reduced overall system efficiency, compared to a passive solution with electrolytic capacitors [4].
Converters employing Flying Capacitor (FC) bridge-legs (see Fig. 1) have additional voltage levels and elevated effective switching frequency and hence enable a more compact and efficient converter realization compared to a standard two-level converter [5], [6]. FCs are typically solely used for creating multi-level voltages, but do not fulfill any lowfrequency energy buffering purpose, i.e., the FCs are dimensioned mostly based on the tolerable high-frequency voltage ripple according to the voltage rating of the switches.
However, based on proper dimensioning the FCs actually represent internal energy storage elements, which can be cycled as PPB capacitors. No additional power components are required, hence making the concept very attractive for cost sensitive applications. However, it is important to highlight that (compared to standard FC converter operation), often semiconductors with an elevated voltage rating are required and the switching-frequency f sw voltage harmonics are increased. Such an FC PPB was considered in [7], [8], [9] for a Three-Level (3L) FC dc-dc converter interfacing a solar panel and a (conventional) two-level single-phase inverter. An ac-dc-stage-integrated FC PPB approach is investigated in [10], [11]. There, the complete single-phase grid power pulsation is covered by the FC by means of a rather complex, varying-switching-frequency control strategy utilizing the high-frequency inductor current (up to 32 different control modes occur within one mains period). Further, ac-dc-stage-integrated FC PPB concepts based upon buckand buck-boost-type single-phase ac-dc converters with full power pulsation compensation capability but relatively high component stresses are investigated in [12], [13], [14].
In this paper, we present an alternative ac-dc-stageintegrated FC PPB where solely the low-frequency inductor current and the redundant FC bridge-leg switching states are utilized to partially buffer the pulsating single-phase power.  Hence, the FC PPB concept can be integrated into a conventional PFC rectifier control structure, thereby enabling a simple control circuit realization.
The paper is structured as follows: Section II derives the basic FC PPB power equations and presents the proposed control concept which is verified by means of simulations in Section III. Design guidelines and the selection of suitable FC capacitance and average voltage values are discussed in Section IV. Then, Section V presents experimental verification of the concept and compares the main converter waveforms for conventional operation and active FC PPB operation. Further, Section VI discusses how the concept can be employed in several different FC converter topologies and, last, Section VII summarizes the main findings of the publication and identifies further research questions relevant for integrated active PPB concepts.

II. ACTIVE FC PPB CONCEPT
As already mentioned, the ac-dc-stage-integrated FC PPB requires no hardware changes and this section presents the key control concept enabling the utilization of the FC of a 3L FC single-phase PFC rectifier as an energy buffer as illustrated in Fig. 2. The considered control diagram is depicted in Fig. 3 and is based on a conventional PFC rectifier control concept: The outer (slow) dc-link voltage control block R Udc defines a grid current reference i * L (corresponding to a sinusoidal grid current i ac in phase with the voltage u ac ) based on the dc-link voltage control error and the output current I dc which is added as a feed-forward term.
The current reference is then tracked by the faster grid current controller R iL defining the Pulse Width Modulation (PWM) duty cycle d resulting in a local average (over a switching period) switch-node voltage u sw = d · U dc .
The FC PPB is then realized with an active FC voltage controller R uFC (which is discussed in more detail in the following subsections) adjusting the duty cycle d without impacting the generated local average switch-node voltage.

A. FC VOLTAGE CONTROL
3L FC converters typically operate with two 180 • phaseshifted PWM carriers for the half-bridges T 1 /T 1 and T 2 /T 2 (see Fig. 1) and identical duty cycles d 1 = d 2 = d such that natural FC voltage balancing [15] maintains the FC voltage Here, aiming at FC PPB operation, the goal is to increase and decrease the FC voltage with twice the mains frequency (see Fig. 2). This is achieved by active FC voltage control (in contrast to conventional FC operation with natural balancing, an FC voltage measurement is required here) where the redundant FC bridge-leg switching states are used to charge or discharge the FC with the local average inductor current i L [7], [16]. Note that the high-frequency inductor current ripple does not have an impact for this type of balancing strategy. The 3L FC bridge-leg switching states are described in Table 1 and for more details we refer to [5], [6]. A correction duty cycle d corr alters the duty cycles of T 1 /T 1 and T 2 /T 2 with d 1 = d − d corr and d 2 = d + d corr , respectively (see Fig. 3). Note that d corr does not impact the duration of the switching states 11 / 00 (see Table 1). In contrast, d corr linearly increases the duration of the charging state 01 and decreases the duration of the discharging state 10 [7], [16], hence yielding a local average FC current and local average FC power with i L and u FC representing the local average values of the inductor current and FC voltage, respectively. Hence, the correction-duty-cycle-based FC control block highlighted in Fig. 3 enables the utilization of C FC as an ac-dc-stageintegrated FC PPB in a similar fashion as in [7]. It is important to highlight that if u FC = U dc /2 the "redundant" states 01 and 10 are no longer equivalent with respect to the resulting switch-node voltage u sw (see Table 1) and the local average value u sw is defined by with r ∈ [0, 2] representing a measure for the relative FC imbalance Hence, to avoid an undesired interaction of the FC PPB and the current controller a compensation duty cycle is added to d 1 and d 2 in Fig. 3. Note that r = 1 corresponds to a balanced FC with u FC = U dc /2 and d comp = 0. Finally, the duty cycles for the half-bridges T 1 /T 1 and T 2 /T 2 in Fig. 3 result to assuring that the FC voltage control action does not disturb the grid current controller and/or does not influence the generation of the desired local average switch-node voltage u sw .

B. DUTY CYCLE LIMITATION
Compared to the dc-dc-converter-integrated FC PPB [7], a substantial challenge for the ac-dc-stage-integrated FC PPB is the duty cycle d varying in a wide range within a mains period. It is crucially important to assure valid duty cycles d 1 , d 2 ∈ [0, 1] to avoid the saturation of the PWM signals with u sw = d · U dc leading in consequence to a current controller disturbance caused by the FC PPB. Hence, the correction d corr and compensation d comp duty cycles have to be limited if d is close to zero or unity. The condition of d 1 , d 2 ∈ [0, 1] and (7) can be translated into limit values and in Fig. 3 an additional duty cycle margin of e.g., 5% is considered to assure current controllability.
To avoid undesired high-frequency coupling of the FC PPB and the current controller, the duty cycle d in (8) is substituted by the feed-forward duty cycle d * = u in /U dc which changes solely with grid frequency and can be further low-pass filtered to avoid any high-frequency noise originating from the feedforward terms.

C. FC REFERENCE GENERATION
The dc-dc-converter-integrated FC PPB [7] defines the FC voltage reference u * FC based on the instantaneous difference between the time-varying input p ac (t ) = i ac · u ac and the constant output power P dc = U dc · I dc .
Here, an additional challenge for the ac-dc-stage-integrated FC PPB is given by the fact that the regulating variable, i.e., the local average of the inductor current i L (see (2)) is time varying and during the AC current zero crossing the FC voltage cannot be actively controlled or influenced. Hence, the ac-dc-stage-integrated FC PPB is not capable of fully covering the pulsating input power, but can only perform a dc-link voltage variation reduction. It therefore makes sense, to define charging (i.e., the FC consumes excess input power) and discharging intervals (i.e., the FC releases energy towards the dc output) within a mains period, where the instantaneous input-output power discrepancy might even be overcompensated in certain time intervals. This approach is realized by a simple bang-bang-type FC reference generation block presented in Fig. 3 which sets binary reference values based on the instantaneous input-output power imbalance p ac (t ) − P dc compared to a charging/discharging threshold power P th . Note that in general u * FC,min > 0 V and u * FC,max < U dc , where the range of eligible FC voltages can be further constrained to assure that the power semiconductor voltage rating is not exceeded. By adjusting the threshold power P th , the duration of the charging and discharging intervals can be adjusted, allowing to regulate the global average (over a mains period)ū FC of the FC voltage which represents a degree of freedom for the modulation of the active FC PPB. In the following, P th is set by a (slow) controller regulatingū FC to the desired reference valueū * FC .

III. OPERATING BEHAVIOUR
The aim of this section is to illustrate the concept of the ac-dc-stage-integrated FC PPB depicted in Fig. 1 based on circuit simulation results and to allow for a qualitative understanding of the impact of the FC capacitance value on the energy buffering capability. The considered operating point specifications include a grid voltage U ac =230 V rms and frequency f ac = 50 Hz, a dc-link voltage U dc = 400 V and power P dc = 2.2 kW. The dc-link capacitor is set to C dc = 610 µF and a boost inductor L = 140 µH is selected. For comparison, Fig. 4(a) first presents the simulated waveforms within one-half mains period for standard 3L FC PFC rectifier operation. As can be observed in Fig. 4(a.i) the FC voltage is balanced naturally to u FC =ū FC = U dc /2 where a small switching-frequency f sw FC voltage variation can be observed for C FC = 10 µF. Fig. 4(a.ii) shows the employed duty cycle d = d 1 = d d and for completeness the (approximately half-wave symmetric) eligible ranges for the correction duty cycle d corr (which is here hard-coded set to d corr = d comp = 0).
Active ac-dc-stage-integrated FC PPB operation is presented in Fig. 4(b) for an identical C FC = 10 µF. A large variation of the FC bridge-leg duty cycles can be observed in Fig. 4(b.ii) where the eligible ranges for the correction duty cycle d corr are now asymmetric as a compensation duty cycle d comp (6) needs to be applied to compensate for the instantaneous FC voltage imbalance r (5). Note that the FC voltage in Fig. 4(b.i) quickly follows the reference value u * FC = {10 V, 390 V} such that no further energy can be buffered after this short charging (or discharging) interval and in consequence the dc-link voltage variation U dc can be reduced only by 6% compared to standard operation (see Fig. 4(b.iii)). Hence, C FC = 10 µF can be considered as an undersized FC value.
Accordingly, Fig. 4(c) presents the main converter waveforms for C FC = 50 µF. Here, u * FC = {10 V, 390 V} is not immediately tracked, thereby enabling longer buffering intervals and a reduction of U dc by 25% compared to standard operation (see Fig. 4(c)).
Interestingly, a further increase of the FC value to C FC = 150 µF (i.e., an increase by a factor of 3 compared to Fig. 4(c)) presented in Fig. 4(d) results in a reduction of U dc by 27% compared to standard operation, i.e., only a marginal improvement compared to Fig. 4(c). Hence, C FC = 150 µF can be considered as an oversized FC value. The culprits for the observed saturation in buffering capability are the correction duty cycle limits which (for a given instantaneous grid current and FC voltage values) limit the instantaneous power intake of the FC PPB and hence the energy buffering capability within one half-mains period.
An alternative approach to further increase the energy buffering capability with C FC = 50 µF is presented in Fig. 4(e) where the average (during one mains period) FC voltage is increased toū FC = 250 V. With the elevated FC voltage values, an injected local average FC current corresponds now to a larger instantaneous power intake of the FC PPB (compared toū FC = 200 V), thereby improving the energy buffering capability within one half-mains period [11].
Here U dc can be reduced by 33% in Fig. 4 (e.iii) compared to standard operation.
It is important to highlight that the dc-link voltage fluctuation for conventional operation in Fig. 4 (a.iii) is purely sinusoidal (at 2 f ac ). In contrast, the reduction in U dc in Fig. 4 (b.iii)-(e.iii) is accompanied by additional low-frequency components at multiples of 2 f ac which is to be considered in the design of the subsequent converter stage.
The results of Fig. 4(a)-(e) enable a basic understanding of the capabilities and limits of the ac-dc-stage-integrated FC PPB and the subsequent section provides a systematic design approach for the selection of the FC parameters.

IV. DESIGN CONSIDERATIONS
The aim of this section is to provide a guideline on how to select suitable FC values for the system with ac-dc-stage integrated FC PPB depicted in Fig. 1. The energy buffered by the dc-link capacitor, E Cdc (see Fig. 2) is defined by There, it can be observed, that FC values C FC ≈ 50 µF enable a reduction of E Cdc by up to 40%. Further, high average FC voltages up toū FC = 300 V can be identified as advantageous, whereas a further increase inū FC decreases again the buffering capability. Note that this is a major difference to the concept in [11] whereū FC = 350 V was selected (also with U dc = 400 V). As discussed in Section III, a further increase of C FC above 50 µF only allows a marginal reduction in E Cdc , as now the FC power flow is constrained by the available duty cycle limits d corr,max and d corr,min and not the lack of storing capability of C FC . Fig. 5(b) depicts the overall capacitance C FC + C dc required to maintain a constant peak-to-peak dc-link voltage variation U dc = 30 V (i.e., U dc ∈ [385 V, 415 V]) normalized by the reference dc-link capacitance required for standard PFC operation As expected from the discussion of Fig. 5(a), the total capacitance can be minimized by up to 30% for C FC ≈ 50 µF, whereas a further increase in C FC causes an increase in the overall required capacitance C FC + C dc . Then, Fig. 5(c) presents the maximum semiconductor blocking voltage within one mains period and the selected u * FC = {10 V, 390 V} implies that switches with blocking voltage equal to ≈ U dc are required for C FC ≤ 50 µF (i.e., an increase by a factor of two compared to standard 3L FC operation). It is important to highlight that the increased blocking voltage is accompanied by elevated high-frequency emissions FIGURE 6. Employed 3L FC converter prototype (details on the system design can be found in [17] and component designators refer to Fig. 1). The system is connected to an external full-bridge diode rectifier (not shown).
by up to a factor of two which, however, corresponds to an increased line-side filtering demand of only 6 dB.
Note that the blocking voltage requirement could be eased withū FC = U dc /2 = 200 V and a large C FC , which, however, would diminish the overall capacitance savings (see Fig. 5(b)), such that similar to [11] semiconductors with full dc-link voltage blocking capability are the only reasonable choice.
Last, Fig. 5(d) presents the RMS inductor current stresses I L normalized to the current stress for standard 3 L FC operation I L,0 = 9.4 A rms , which change by less than 15% across the considered ranges of FC capacitance value C FC and the average voltageū FC . Note that the semiconductor RMS current stresses also change by less than 15% throughout the considered converter specifications and are hence not further detailed here.
It is worth highlighting that for converter specifications with an increased average power P dc (or decreasing mains frequency f ac ) the results of Fig. 5 remain valid if the x-axis (i.e., the FC value C FC ) is scaled linearly with P dc and/or the inverse of f ac . Further, when aiming at a straight-forward FC PPB component sizing, the global average voltageū FC and the binary voltage swing u * FC are selected as high as tolerable from the employed semiconductors in order to maximize the buffering capability. Then, starting from a low FC capacitance value C FC , the value of C FC is iteratively increased until the decrease in E Cdc (see Fig. 5(a)) begins to saturate. Fig. 6 depicts the 3L FC converter prototype (and the main power component values) from [17] rectifying a grid voltage of U ac =230 V rms to a dc-link voltage U dc = 400 V. Employing Gallium Nitride (GaN) semiconductors with a blocking voltage of 600 V (IGOT60R070D1) capable of switching the full dc-link voltage, the FC voltage can be allowed to vary in a range u FC ∈ [0, U dc ]. Fig. 7(a.i), presents the main converter waveforms of the FC rectifier shown in Fig. 6 and P dc = 2.2 kW in conventional 3L operation with u FC ≈ U dc /2 = 200 V, where a peak-to-peak dc-link voltage variation U dc = 29.6 V can be observed.  Operation with the proposed integrated FC PPB is outlined in Fig. 7(b.i), where the FC voltage u FC varies in a wide range with twice the mains frequency and at the same time a sinusoidal grid current i ac is maintained. Note that due to the fluctuating FC voltage the switching-frequency f sw component of u sw does no longer cancel out (in contrast to conventional 3L FC operation), such that an increased high-frequency grid current ripple can be observed. Here, the dc-link voltage variation results to U dc = 21.3 V corresponding to a 28% improvement compared to conventional FC operation, which is close to the result of Fig. 4(e). This reduced U dc is especially beneficial as the expected lifetime of an electrolytic capacitor depends both on temperature and current stress [2], i.e., is extended by employing the proposed integrated FC PPB operation. Alternatively, the dc-link capacitor could be decreased while maintaining a constant dc-link voltage fluctuation.

V. EXPERIMENTAL VERIFICATION
In contrast to Fig. 7(a.ii), the duty cycles d 1 and d 2 in Fig. 7(b.ii) differ substantially. There, the correction d corr and the compensation duty cycle d comp (preventing a current controller disturbance by the active FC PPB), and the correction duty cycle limits d corr,max and d corr,min (aiming at a valid duty cycle range of [0.1,0.95]) are also highlighted.
As expected, the discharging of the FC slows down in the vicinity of the current zero crossing (see Fig. 7(b.i) for t ≈ 10 ms), which is a result of 1) the low inductor current values and 2) the limited range of admissible correction duty cycle values for d close to zero. Here, a threshold power P th ≈ 400 W increases the duration of the discharging intervals and assures that a global average FC voltageū FC = 250 V is maintained.
All in all, it can be stated that a 28% dc-link voltage variation U dc improvement is enabled by the active, ac-dcstage-integrated FC PPB operation for the topology presented in Fig. 1. Note that this dc-link voltage variation improvement, results in a slight increase of the grid current Total Harmonic Distortion (THD) (considering up to the order 40) from 1.7% in Fig. 7(a.i) to 3.2% in Fig. 7(b.i), which, however, still remains substantially below a typical THD value of 5% of industrial demonstrator systems.

VI. APPLICABILITY OF THE CONCEPT
It is worth highlighting that the ac-dc-stage-integrated FC PPB concept presented here could be also employed to topology variants of the 3L FC converter shown in Fig. 1 and several topology candidates of interest are presented in Fig. 8.
In case bidirectional power flow is required and/or the conduction losses of the front-end diode bridge of the singlephase PFC rectifier circuit of Fig. 1 should be avoided, an unfolder bridge-leg T N /T N can be employed, resulting in the converter topology depicted in Fig. 8(a). Advantageously, the unfolder only operates at mains frequency, such that T N and T N can be realized with low-on-state resistance Silicon (Si) Super Junction (SJ) semiconductors. Fig. 1: (a) bidirectional realization with a main-frequency-operated unfolder bridge-leg T N /T N , (b) bidirectional H-bridge realization employing two high-frequency-operated FC bridge-legs, (c) converter topology featuring three-phase and single-phase ac-dc power conversion.

FIGURE 8. Further applications of the 3L FC bridge-leg with integrated PPB introduced for a single-phase PFC rectifier with a front-end diode bridge in
Alternatively, Fig. 8(b) presents an H-bridge realization employing two FC bridge-legs which are both high-frequency switched. Here, an even larger reduction of the dc-link voltage variation compared to the system in Fig. 1/Fig. 8(a) is facilitated, as advantageously 1) twice the energy can be buffered due to the second FC and 2) a duty cycle of d ≈ 0.5 results in the vicinity of the grid current zero crossing enabling large correction duty cycle values and hence charging/discharging intervals of approximately equal length with additional buffering capability.
Another interesting field of application for the ac-dc-stageintegrated FC PPB concept is a PFC rectifier system capable of operating in a single-phase as well as a three-phase AC grid [18], [19] as highlighted in Fig. 8(c). For safety reasons, this system provides galvanic isolation which is realized with two isolated dc-dc converters. In three-phase operation (Fig. 8(c.i)), the grid input power is constant, and hence no PPB is required and the FC voltages remain constant at half the dc-link voltage. For a boost-type system, a large dc-link voltage is required with U dc > √ 3Û ac , where U dc = 800 V is a typical voltage level allowing to utilize 600 V GaN power semiconductors, which can be also employed in the two isolated dc-dc converters connected in an Input-Series-Output-Parallel (ISOP) configuration. In single-phase operation (Fig. 8(c.ii)), the input power p ac is pulsating with twice the mains frequency. Since the minimum dc-link voltage criterion is relaxed to U dc >Û ac , e.g., U dc = 400 V can be selected, such that the integrated FC PPB can cycle the FC voltages u FCa and u FCc in a wide range, thereby reducing the minimum required dc-link capacitor value, while the blocking voltage capability of the 600 V GaN semiconductors is respected. Here, the isolated dc-dc converters are advantageously reconfigured to Input-Parallel-Output-Parallel (IPOP), such that the isolated dc output voltage U dc,out remains identical to three-phase operation.

VII. CONCLUSION
Conventional single-phase PFC rectifier systems require large dc-link capacitors to buffer the twice-mains frequency input power pulsation. This paper presents an ac-dc-stageintegrated Flying Capacitor (FC) Power Pulsation Buffer (PPB) for single-phase ac-dc converters employing FC bridgelegs requiring no additional power components. The presented 3L FC control concept is based on the utilization of the redundant switching states and can be integrated into a standard PFC rectifier control structure. The proposed control concept allows to manipulate the FC power flow within certain bounds, thereby enabling a power pulsation and/or a dc-link voltage variation reduction.
Experimental verification with a 2.2 kW prototype presented in this paper revealed a dc-link voltage variation reduction of 28% enabled by the active, ac-dc-stage-integrated FC PPB, which is closely matching the achievable reduction found by circuit simulations. With the completed verification of the control concept based upon an existing converter system, in a next step a performance assessment with respect to the limits in power density and efficiency by means of an optimized converter prototype (including a grid-side high-frequency filter) employing the FC PPB concept can be conducted. In closing it is important to highlight that the proposed FC PPB concept can be employed in a wide variety of single-phase ac-dc FC converters.