Duty-Cycle Dependent Phase Shift Modulation of Dual Three-Phase Active Bridge Four-Port AC–DC/DC–AC Converter Eliminating Low Frequency Power Pulsations

A recently introduced Dual Three-Phase Active Bridge Converter (D3ABC) provides two three-phase ac ports (ac<inline-formula><tex-math notation="LaTeX">${}_{1}$</tex-math></inline-formula> and ac<inline-formula><tex-math notation="LaTeX">${}_{2}$</tex-math></inline-formula>), two dc ports (dc<inline-formula><tex-math notation="LaTeX">${}_{1}$</tex-math></inline-formula> and dc<inline-formula><tex-math notation="LaTeX">${}_{2}$</tex-math></inline-formula>), and galvanic isolation between the ports ac<inline-formula><tex-math notation="LaTeX">${}_{1}$</tex-math></inline-formula>, dc<inline-formula><tex-math notation="LaTeX">${}_{1}$</tex-math></inline-formula> (primary side) and ac<inline-formula><tex-math notation="LaTeX">${}_{2}$</tex-math></inline-formula>, dc<inline-formula><tex-math notation="LaTeX">${}_{2}$</tex-math></inline-formula> (secondary side). Previously documented studies confirm that the D3ABC is generally capable of transferring power between all four ports. However, it has been found challenging to operate the converter if ac voltages with different line frequencies, <inline-formula><tex-math notation="LaTeX">$f_{1} \ne f_{2}$</tex-math></inline-formula>, are present at the ports ac<inline-formula><tex-math notation="LaTeX">${}_{1}$</tex-math></inline-formula> and ac<inline-formula><tex-math notation="LaTeX">${}_{2}$</tex-math></inline-formula>. Such operation causes Low-Frequency (LF) power pulsations in the converter's dc links, leading to fluctuating dc link voltages and distorted phase currents. In this paper, a new duty-cycle dependent phase shift modulation scheme is proposed that eliminates such LF power pulsations and substantially increases the theoretical maximum transmittable power between primary and secondary sides compared to previous work. The new modulation scheme is developed on the basis of analytical considerations, which are supported by the results of numerical calculations, and verified by means of circuit simulations and experimental results. A hardware demonstrator originally designed for a rated power of <inline-formula><tex-math notation="LaTeX">$\text{8}\,$</tex-math></inline-formula>kW when operated from ac<inline-formula><tex-math notation="LaTeX">${}_{1}$</tex-math></inline-formula> to dc<inline-formula><tex-math notation="LaTeX">${}_{2}$</tex-math></inline-formula> at the European low-voltage ac mains (<inline-formula><tex-math notation="LaTeX">$V_{\mathrm{ac,1}} = \text{230}\,{\rm V}$</tex-math></inline-formula> line-to-neutral rms, <inline-formula><tex-math notation="LaTeX">$V_{\mathrm{dc,1}} = \text{800}\,{\rm V}$</tex-math></inline-formula>, <inline-formula><tex-math notation="LaTeX">$V_{\mathrm{dc,2}} = \text{400}\,{\rm V}$</tex-math></inline-formula>) is used for experimental verification. Since the operation with <inline-formula><tex-math notation="LaTeX">$f_{1} \ne f_{2}$</tex-math></inline-formula> leads to an increase of the currents in the converter, the experimental verification is conducted at half voltages and for a reduced power of <inline-formula><tex-math notation="LaTeX">$\text{2}\,$</tex-math></inline-formula>kW that is transferred from ac<inline-formula><tex-math notation="LaTeX">${}_{1}$</tex-math></inline-formula> to ac<inline-formula><tex-math notation="LaTeX">${}_{2}$</tex-math></inline-formula> at substantially different primary-side and secondary-side line frequencies of <inline-formula><tex-math notation="LaTeX">$f_{1} = \text{50}\,$</tex-math></inline-formula>Hz and <inline-formula><tex-math notation="LaTeX">$f_{2} = \text{77}\,$</tex-math></inline-formula>Hz. The measured results agree well with the simulated results. In particular, the dc link voltages show almost constant waveforms, which confirms the correct operation of the proposed modulation scheme.

primary-and secondary-side ac and dc ports can meet these requirements.
Conventionally, such a four-port ac-dc/dc-ac converter system can be realized by means of a series connection of a primary-side three-phase rectifier, a dc/dc converter with galvanic isolation, and a secondary-side three-phase inverter. However, rectifier and inverter circuits with a voltage dc link must be used, since otherwise no dc voltage ports would be available [6]. Most related publications describe the realization of a conventional ac-dc/dc converter structure, i.e., the series connection of a primary-side three-phase rectifier and a dc/dc converter with galvanic isolation, which can be immediately extended to an ac-dc/dc-ac structure. Documented examples include the series connection of a two-level sixswitch rectifier and single-phase Dual Active Bridge (DAB) converter [7] or full-bridge dc/dc converter [8]; the combination of a three-level T-type rectifier and full-bridge dc/dc converter [9] or of a three-level Neutral Point Clamped (NPC) rectifier and three-phase DAB converter [10].
In the context of improving the efficiency and/or volume requirements of power electronic circuits, the integration of several converter stages into a single converter stage is of particular importance. Examples of documented rectifiers with integrated galvanic isolation are the current-fed rectifiers with integrated LLC resonant converter described in [11] or with a DAB converter presented in [12], the rectifier with integrated full-bridge dc/dc converter presented in [13], the rectifier with integrated three-phase DAB converter explained in [14], or the nine-switch converter with integrated three-phase resonant converter described in [15]. These topologies are complemented by further rectifier topologies with integrated galvanic isolation, but without a primary-side dc voltage port, such as matrix-type converters [16], [17] and Swiss-type converters [18], [19].
If the four-port converter system would be realized with one of the topologies described in [11], [12], [13], [14], [15], a secondary-side inverter would still be needed. However, fully integrated circuits also exist for the examined four-port operation [20], [21], although the description in [20] is limited to four-port operation with one ac port and three dc ports, and the one in [21] to rectifier operation with galvanic isolation. Nevertheless, after minor adjustments, a four-port operation with two ac ports and two dc ports can be achieved with both systems. Due to the significantly higher circuit complexity of the converter analyzed in [20] (e.g., 24 semiconductor switches), the focus of this paper is on the further investigation of the D3ABC introduced in [21], which is shown in Fig. 1. Table 1 lists the nominal voltages and frequency as well as the maximum power of the considered D3ABC. This topology can be understood as the integration of two three-phase VSCs and three DAB converters.
The integration of several converter stages into a single converter stage is achieved by using the switching nodes of the half-bridges for multiple purposes. As a result, certain degrees of freedom are lost, which leads to various limitations. In case of the D3ABC it turns out that the operation with non-synchronous input and output voltage waveforms, e.g., with different line frequencies, f 1 = f 2 , may cause LF power pulsations between the two dc links. This LF power pulsation is not sinusoidal but has a spectrum with a fundamental frequency component at | f 1 − f 2 |.
If, for example, the grid frequency is f 1 = 50.0 Hz at port ac 1 and f 2 = 50.1 Hz at port ac 2 , power pulsation with fundamental | f 1 − f 2 | = 0.1 Hz can occur in the primary-side and secondary-side dc links. These can lead to unacceptable fluctuations of the dc link voltages. Usually, these voltage fluctuations are counteracted by suitably adjusting the dc link capacitances [22], improving the utilizations of the dc link capacitors by using power pulsation buffers [23], or by involving an alternative means of energy storage, such as the kinetic energy stored in an electric machine [24]. Alternatively, large filter capacitances connected to the ac ports could absorb the power pulsation. These filter capacitances could also be implemented as solid-state variable capacitors, as, e.g., shown in [25] and [26] for single-phase systems. However, since the minimum required storage capacities are inversely proportional to the frequency of the pulsation [27] and the frequency of the power pulsation can take on very small frequencies down to zero (0.1 Hz in the example described above), the issue actually cannot be solved in this way. Alternatively, the pulsating power could be supplied to the grid. However, a related study concludes that LF power pulsations can be subject to very restrictive limits, especially in the context of flicker [28], which rules out this option. Accordingly, the only remaining option is to adapt the modulation scheme such that pulsating power is suppressed in the dc links.
A previous study [29] describes the four-port operation of the D3ABC under the simplifying condition that the individual DAB converter parts of the D3ABC are operated at constant power in steady state. This leads to a major reduction of the maximum transferrable power. In this paper, a new duty-cycle dependent phase shift modulation scheme is developed which considerably increases the transferrable power. First, Section II explains the multiport operation of the D3ABC. Subsequently, the new modulation scheme for elimination of LF power pulsation is derived in Section III. Finally, Section IV verifies the derived modulation scheme through circuit simulations and measurements on a hardware prototype.

II. MULTI-PORT OPERATION OF THE D3ABC
The systematic description of the operation of the D3ABC with different line frequencies at the ports ac 1 and ac 2 and the consequences of this kind of operation of the D3ABC, is divided into the three steps listed below.
1) Summary of the general operating principle of the D3ABC in Section II-A. 2) Investigation of the known operation with synchronized three-phase ac voltages at the ports ac 1 and ac 2 (same line frequencies and no phase shift) in Section II-B. 3) Operation with three-phase ac voltages with different line frequencies at ac 1 and ac 2 in Section II-C.

A. OPERATING PRINCIPLE OF THE D3ABC
In this paper, symmetric three-phase systems are considered at the primary-side and secondary-side ac ports. Accordingly, three sinusoidal voltages are present at ac 1 and ac 2 , respectively, v ac,1,a,b,c (t ) = √ 2V ac,1 sin 2π v ac,2,A,B,C (t ) = √ 2V ac,2 sin 2π Here, V ac,1 and V ac,2 denote the rms values of the phase voltages, f 1 and f 2 denote the line frequencies, shifts between the primary-side and secondary-side phase voltages, respectively, and an initial phase shift between the primary-side and secondary-side phase voltages at time t = 0. Further, this paper consideres three different operating scenarios, S1 to S4: S1 refers to multi-port operation with synchronized line voltages, S2 to multi-port operation with different line frequencies, S3 to ac-ac operation with different line frequencies, and S4 to ac-ac operation with different line frequencies and reduced voltages as used for the hardware demonstrator. Table 2 lists the parameters for S1 to S4. In this context, it is noted that the sign of the power is defined in the generator reference system, as seen by the D3ABC. Accordingly, a power flow directed from the D3ABC to an external component (e.g., a resistor) has a positive sign. A negative power is present if the power flow at the port under consideration is directed into the converter system. In the context of the bidirectional conversion capability of the D3ABC, this careful definition serves to unambiguously define the operating condition present at each port. Fig. 2 shows the considered configuration of sources and loads, both for the circuit simulations and for the measurements performed on the hardware demonstrator. The resistor values are chosen so that the powers listed in Table 2 result. For scenarios S3 and S4, the current source at dc 1 and the resistor at dc 2 are removed.
For reasons of compactness, a description of the operating principle of the D3ABC is omitted here, since this has been described in detail in [21], [29] (for completeness, a summary FIGURE 3. Single-phase equivalent system with primary-side and secondary-side boost inductances, L ac,1 and L ac,2 , stray inductance, L σ , and isolating High-Frequency (HF) transformer with turns ratio n. A detailed derivation of this equivalent circuit can be found in [30].
of this is given in Appendix A of this paper). The following paragraphs summarize the most important aspects.
The D3ABC can be divided into three independent converter systems, i.e., one converter system per phase. Fig. 3 depicts the equivalent circuit of such a single-phase converter system. The primary-side dc link circuits of the three singlephase converter systems are combined in parallel connection and the secondary-side dc link circuits are also connected in parallel.
The energy exchange between ac 1 and the dc link capacitor connected to dc 1 is accomplished in analogy to a Power Factor Correction (PFC) rectifier. Based on the assumption that the mains-side filter inductors have low impedance at the mains frequency, the local average value of the switched voltage generated by a half-bridge (e.g., v n,a in Fig. 1) 1 is approximately equal to the waveform of the mains voltage of this phase. Therefore, taking the example of phases a and A, the where D 1a and D 2 A denote the relative turn-on times of the low-side transistors of phase a of the primary-side inverter and phase A of the secondary-side inverter, respectively. These expressions can be modified in terms of the phases b, B and c, C, leading to the relations for the duty cycles of the six half-bridges. The method to control the power transfer between the ports ac 1 and dc 1 depends on what ac 1 is connected to. If ac 1 is connected to a three-phase resistive load, it is sufficient to set the three-phase ac voltages using the duty cycles calculated according to (5). If ac 1 is connected to a three-phase grid, a closed-loop control, e.g., the indirect current control described in [31], is used. This controller slightly adjusts D 1,a,b,c (t ) in order to shape the mains-side phase currents according to the given requirements (e.g., sinusoidal with defined amplitude and in phase to the corresponding phase voltage). However, since the modulation scheme described in this paper is related to the operation of the DAB part of the D3ABC, it is irrelevant whether the duty cycles are determined by open-or closed-loop control. The same applies to the ports ac 2 and dc 2 , whereas the power transfer between these two ports is controlled by slightly adjusting D 2,A,B,C . The energy exchange between the dc link capacitors connected to dc 1 and dc 2 is achieved in analogy to a DAB converter, i.e., the square-wave voltage (e.g. v n,a ) at the switching node of a primary-side half-bridge is shifted by a certain HF phase with respect to the square-wave voltage (e.g. v N,A ) at the switching node of the secondary-side half-bridge of the same converter phase. This leads to the formation of the typical transformer current of a DAB converter. The associated power flow between the primary-side and secondary-side dc link capacitors can be described using the local average value of the instantaneous power. For example, applies to phase a. Thereby the half-bridges on the primary and secondary sides are switched with the same switching frequency. Fig. 4 illustrates the considered power transfers by means of a diagram. Fig. 5(a) exemplarily depicts the waveform of the primaryside transformer current in phase a, for operation according to S1 in Table 2 and over two mains periods. Since the switching frequency is much higher than the mains frequency, the  Table 3. transformer current waveform, i Lσ,1a (t ), appears as a continuous band. 2 Fig. 5(b) therefore shows a magnified view of a switching period in the region of the zero crossing of the line current (t = 20 ms), which reveals the characteristic waveform of the transformer current. It is worth noting that Fig. 5(b) is additionally used to define the duty cycles D 1a and D 2 A and the HF phase shift ϕ p,aA . The same picture results for phases b and c, except for a time displacement of ±20 ms/3 = ±6.67 ms. Fig. 6 presents the results of a circuit simulation for operation according to S1 in Table 2 and with synchronized line voltages at ac 1 and ac 2 . In this context, Fig. 6(a) and (b) show the waveforms of the phase voltages and phase currents present at ac 1 and ac 2 as well as the dc voltages and dc currents present at dc 1 and dc 2 . Fig. 6(c) depicts the waveforms of the duty cycles D 1a (t ) and D 2 A (t ) as well as the HF phase shift ϕ p,aA . Direct comparison of v ac,1a in Fig. 6(a) and D 1a (t ) in Fig. 6(c) reveals that, due to the relationship described by (3), D 1a (t ) − 0.5 is practically proportional to v ac,1a (the same is true for D 2 A (t ) − 0.5 and v ac,2A ). Moreover, the modulation scheme 2 The presumable phase shift of 180 • between v ac,1a and i Lσ,1a in Fig. 5(a) is not present in reality. Instead, the shape of the current band is a result of different positive and negative current peak values of i Lσ,1a (t ) due to the DAB converter operation during a mains period. For more details, the reader is referred to Section II in [21]. described in [21] applies a constant HF phase shift, ϕ p,aA , in the steady state. Fig. 6(d) shows the instantaneous powers at the four ports of the D3ABC, which agree with the values for S1 listed in Table 2. It is well known that rectifier or inverter operation in the balanced three-phase system (e.g., power conversion between ac 1 and dc 1 ) results in a constant local average value of the power at the dc link. This explains the waveforms of p ac,1 (t ) and p ac,2 (t ) in this figure, which are practically constant except for switching-frequency fluctuations. Fig. 6(e) reveals the waveforms of the local average values of the powers of the three DAB converter stages, p aA , p bB , and p cC , which, for the investigated mode of operation, are sinusoidal and phase-shifted with respect to each other by ±120 • . Accordingly, the total power of the DAB part of the D3ABC,

B. SYNCHRONIZED LINE VOLTAGES AT AC 1 AND AC 2
is constant. For this reason, no power pulsations with frequencies in the range of the line frequencies occur at the dc link capacitors, which allows the realization of the converter with comparably small dc link capacitors. Fig. 7 presents the results of a circuit simulation for operation according to S2 in Table 2, i.e., for a line frequency of f 2 = 77 Hz at ac 2 . Accordingly, the voltages of corresponding phases of the three-phase system of the primary side [ Fig. 7(a)] and the secondary side [ Fig. 7(b)] are not synchronous anymore. According to (3) and (4), this leads to unequal duty cycles in corresponding converter phases (e.g., primary-side phase a and secondary-side phase A), as shown in the example of phases a and A in Fig. 7(c). The sum of the powers in the three DAB converter stages, p , shown in Fig. 7(e) contains pronounced LF components, in contrast to the simulation with f 1 = f 2 shown in Fig. 6(e). The pronounced LF components in p lead to variations in the dc-link voltages and distortions in the phase currents. Since the phase current controller (implemented as described in [31]) keeps the voltage on the primary-side dc link almost constant, a major part of the power pulsation is transferred to ac 1 and thus to the grid. However, the dc link voltage on the secondary side is not controlled (HF phase shift is kept constant) and therefore the power pulsation is split between the ports dc 2 and ac 2 . This explains the non-constant power waveforms for the three ports ac 1 , dc 2 , and ac 2 shown in Fig. 7(d).

C. OPERATION WITH DIFFERENT LINE FREQUENCIES AT AC 1 AND AC 2
The non-sinusoidal total power, p , plotted in Fig. 7(e) reveals spectral components at f 2 − f 1 = 27 Hz and 2( f 2 − f 1 ) = 54 Hz in addition to the dc component with a power of ≈ 8 kW, as shown in Fig. 8. As described in the introduction, especially the component at f 2 − f 1 is a challenge for filtering and should therefore be eliminated by using a suitable modulation scheme.  Table 2) using the parameters given in Table 3: (a) primary-side voltages and currents, (b) secondary-side voltages and currents, (c) duty cycles and the HF phase shift at phase a, (d) power levels at the four ports, and (e) local average values of the powers of the three DAB converter stages and the resulting total power, p . Apart from switching-frequency fluctuations, the powers at the four ports and the total power of the DAB part show practically constant waveforms, i.e., no LF components are present.

III. ELIMINATION OF LF POWER PULSATION
Based on the consideration that symmetric three-phase systems are present at the primary-side and secondary-side ac ports, the LF components in p exclusively occur in the DAB part of the D3ABC, as discovered in Section II-C. Furthermore, according to (5) and (6), the waveforms of the three-phase line voltages at ac 1 and ac 2 already specify the waveforms of the primary-side and secondary-side duty cycles. Hence, only the HF phase shifts, ϕ p,aA , ϕ p,bB , and ϕ p,cC , remain as degrees of freedom. This also implies that the power flow between the ports ac 1 and dc 1 or between ac 2 and dc 2 has no influence on LF components in the currents of the dc link capacitors. Consequently, the powers at dc 1 and dc 2 can be set to zero without limiting the generality.

A. CONSIDERED CONSTRAINTS
In a first step, three constraints are defined for the functions of the power waveforms of the three DAB converter phases, The first constraint, (9), formulates the suppression of the LF components in the total power, p (t ). Constraint (10) enforces that the waveforms of p aA,bB,cC have the same shape except that they are phase-shifted with respect to each other by 120 • . There, T denotes the effective period of p aA,bB,cC . The aim of (10) is to achieve even loading of the phases. Finally, the third constraint, (11), ensures that the power in each phase never exceeds the maximum possible power, , of the corresponding converter phase. This third constraint also leads to a limit for the total power, The achievable value for P ,max is determined in this Section as part of the development of the modulation scheme. A simple approach which fulfills (9), (10), and (11) is presented in [29]. There, constant and equal power is used in all three phases, p aA = p bB = p cC = const. = P /3. However, this approach results in a maximum power of only P ,max = 2.9 kW, which is significantly less than the rated power of 8 kW that is available for operation from ac 1 to dc 2 , which the converter was designed for [21]. This is, because a single phase of the D3ABC can transfer only comparably low power between the primary and the secondary side if the duty cycles of the same phase have values close to zero or one. Consequently, the development of an improved modulation scheme is based on the idea that the power shortfall of those DAB converter stages, which are operated at a given time with duty cycles close to zero or one, is compensated by an increased power of the remaining converter stages.
In the new approach, the power in each phase is adjusted based on a polynomial function that depends on the primaryside and secondary-side duty cycles, The scaling factor P 0 in (13) was determined in the course of the analysis of the operating modes of the DAB presented in [29] and contains all hardware-specific values, It is to be noted that the indices denoting the converter phases are omitted in (13) to provide a more comprehensible description of the subsequent derivations. Accordingly, the variables p, D 1 , and D 2 are to be replaced by the variables of the DAB converter part to be evaluated, e.g., by p aA , D 1,a , and D 2,A in case of converter phases a-A. As shown in Appendix A, (13) is conceived in such a way that a significant increase of P is achieved (compared to the previous approach presented in [29]) and that the constraints (9) and (10) are met for sinusoidal duty cycles according to (5) and (6), regardless of the values of the seven coefficients, a 0 . . . b 4 . Thus, the coefficients must be selected such that the third constraint (11) is also fulfilled, which is described in the following Subsection.

B. DERIVATION OF THE MODULATION SCHEME
In this Subsection, first, the power transfer characteristic of a single DAB converter phase is investigated to gain a better understanding of the constraints associated with the transferable power. Thereafter, different considerations on possible simplifications are made. The findings obtained in this context reveal that only two coefficients of (13) remain. The expressions for these remaining coefficients are derived in a subsequent step. The maximum power that can be transferred by each phase, P max (D 1 , D 2 ), is calculated with the expressions derived in [29] and summarized in Appendix A. The contour plot presented in Fig. 9(a) illustrates the characteristic of P max (D 1 , D 2 )/P 0 for D 1 , D 2 ∈ [0, 1]. In order to fulfill (11), p must be less than P max (D 1 , D 2 ) in the complete range of D 1 and D 2 , where, for simplicity, same maximum modulation indices are considered on the primary and secondary sides, The dotted blue rectangle in Fig. 9(a) illustrates the boundary of the area defined with (15) and (16) for m max = 0.81, that results for operation according to Table 2. It should be noted that all four considered scenarios, S1 to S4, result in the same m max = 0.81. It is apparent from Fig. 9(a) that P max (D 1 , D 2 ) decreases if the duty cycles differ from 0.5 and reaches zero for duty cycles equal to 0 or 1. Within the dotted blue rectangle, the lowest achievable power is present at the corners. To have a more detailed view of the corners, a cross-sectional drawing is shown in Fig. 9(b) for the dash-dotted diagonal intersection line shown in Fig. 9(a). The dashed orange line refers to the characteristic of the normalized maximum power of a DAB converter phase, P max /P 0 , for D 2 = 1 − D 1 . In view of this characteristic, it may be reasonable to assume that the power at the corners of the duty-cycle ranges defined with (15) and (16), has to be considered to determine the coefficients of (13), to ensure that the D3ABC never exceeds the maximum feasible power. However, at this operating point also the polynomial (13) returns the lowest value within the considered ranges of D 1 and D 2 [in anticipation of the result, the shape of p is plotted as solid red line in Fig. 9(b)]. Since (13) is conceived such that the sum over the three phase powers is constant, i.e., the remaining converter phases compensate for the missing power, the operating point at the corner is not necessarily the most critical. Instead, it is found in the course of the derivation of useful expressions for the coefficients of p that the operating conditions D 1 = 0.5, D 2 = D 2,min,max and D 2 = 0.5, D 1 = D 1,min,max are of major importance. Therefore, Fig. 9(c) shows a corresponding cross-sectional drawing for D 2 = 0.5, i.e., for the dash-dotted horizontal intersection line marked in Fig. 9(a). The power at the edge of the operating range, e.g., D 1 = D 1,min and D 2 = 0.5, is denoted by P e , 3 P e = p (D 1,min , D 2 = 0.5) = p (D 1,max , D 2 = 0.5).
Based on these observations, the number of required coefficients can be reduced and the remaining coefficients determined. With (17) and due to the symmetry of the D3ABC (i.e., the primary and secondary sides can be swapped without changing the circuit), a 1 = b 1 , a 2 = b 2 , and a 4 = b 4 must hold true. Furthermore, the function of p is intended to be symmetric around the operating point D 1 = D 2 = 0.5, since maximum power can be transferred there, which leads to a 1 = b 1 = 0. Finally, to further simplify the problem, only a quadratic polynomial is considered in a first approach, i.e., a 4 = b 4 = 0 applies. With these considerations and simplifications, solely the coefficients a 0 and a 2 need to be determined such that (11) is fulfilled. In the last step, a connection is made between the maximum transferrable power and the remaining coefficients, a 0 and a 2 , to obtain the final expressions for a 0 and a 2 . In this context, it is recalled that (13) is designed such that (10) is fulfilled. As a consequence, the global average values of the powers of the three phase, i.e., evaluated over −∞ ≤ t ≤ +∞, are equal to one third of the total power. As a side note, it is worth noting that the average value of a sum term can be calculated by adding the average values of the individual terms, where T , T 1 , and T 2 refer to the periods of y 1 (t ) + y 2 (t ), y 1 (t ), and y 2 (t ), respectively. In this regard (20) is applied to (13) to establish a relation between P , a 0 , and a 2 , Furthermore, a 0 and a 2 can be expressed as functions of P c and P e , by evaluating (13) at the operating points defined by (18) and (19) and subsequently solving for a 0 and a 2 . If (22) is substituted into (21), results, i.e., only P e defines the average power. Accordingly, P c remains as a degree of freedom. A numerical inspection of (11) shows that any value of P c that satisfies |P c | ≤ 3 Due to the definition (17), the same value for P e results for D 1 = 0.5 and D 2 = D 2,min as well as D 1 = 0.5 and D 2 = D 2,max . P max (D 1,max , D 2,max ) also satisfies (11). However, minimum rms values of the transformer currents result if P e is set equal to the respective maximum power and P c is set to zero, With this, the final result is obtained, The solid red curves shown in Fig. 9(b) and (c) depict the results for (13), i.e., p (D 1 , D 2 ), if (26) is applied. The results of a numerical analysis presented in Appendix B reveal that the obtained function for p (D 1 , D 2 ) is less than or equal to the maximum phase power, P max , (dashed orange line) in the entire range defined by (15) and (16).
Finally, with (24) substituted into (23) the maximum total power, is obtained. Note that P ,max represents the maximum power that can be transmitted between primary side and secondary side through the three DAB converter stages of the D3ABC, using (13) (with a 4 = b 4 = 0) and the maximum modulation indices at the two ac ports as defined in (17). Thereby it is irrelevant whether the power transmitted over the galvanic isolation is supplied by the ac or dc port (e.g., of the primary side) or whether the load being supplied is connected to the ac or dc port (e.g., of the secondary side). The limitation of P ,max is rooted in the power limitation known from DAB converters, due to which the transmitted power above a certain HF phase shift ϕ p does not increase further but decreases as shown in Fig. 5 in [21]. If, for example, P ,max is to be increased for a given converter, either m max must be decreased or P 0 increased. A decrease of m max results in a reduction of the maximum possible ac voltages at the ac ports. An increase of P 0 is achieved, e.g., by decreasing the leakage inductance L σ or the switching frequency f s .
Inserting the values listed for S1, S2, or S3 in Table 2  and Table 3 into (14) and (27) gives a maximum power of P ,max = 8.5 kW, what is substantially higher than the maximum power of P ,max = 2.9 kW achieved with the simple approach described in [29]. This value, P ,max = 8.5 kW, therefore represents the maximum theoretical total power for a specific hardware with given transformer parameters (L σ , n) and given operating conditions (V dc,1 , V dc,2 , f s ). In this context, it is important to emphasize that P ,max represents a theoretical limit and must not be mistaken for the maximum permissible operating power of the converter, which is determined on the basis of the maximum permissible stresses of the designed or selected converter components. Consequently, the component stresses must be considered separately, which is done in Appendix B using a numerical analysis. It is noted that the functions for a 0 and a 2 derived in this Section can be directly used to operate the D3ABC with modulation indices smaller than m max . In this regard, the possible total power, P ,max , increases for smaller modulation indices. The expressions (26) are valid for operation at maximum power. However, the results of a numerical analysis show that the power in the DAB part of the D3ABC can be adjusted by scaling both coefficients at the ratio r p = P /P ,max , a 0 = a 0,max r p , a 2 = a 2,max r p .
With this, currents with nearly minimal rms values result into the switching nodes on primary and secondary side, I 1,rms and I 2,rms , of the D3ABC, as described in Appendix B.
The functions for calculating the HF phase shifts ϕ p,aA (t ), ϕ p,bB (t ), and ϕ p,cC (t ) that correspond to the phase powers, p aA (t ), p bB (t ), and p cC (t ), determined with (13) are provided in Appendix A and in [29]. Fig. 10 illustrates the flow chart of the algorithm used to determine the current operating mode of the DAB and to calculate the corresponding HF phase shift ϕ p (described in Appendix A). Table 4 in Appendix A lists the expressions used for ϕ p,I , ϕ p,II , ϕ p,III , and ϕ p,IV . Fig. 11 shows a pseudocode for a runtime-optimized implementation of the algorithm implemented on the hardware demonstrator's Digital Signal Processor (DSP). The expression for the intermediate variable e 1 used in this implementation has been derived based on (13) together with the coefficients (28). The constant m q = m 2 max defines the maximum modulation index that occurs during operation. The variables D 1 [1.  Table 4. The variable r p denotes the scaling factor for the transferred power and has a value range of −1 ≤ r p ≤ 1 (r p = 1 corresponds to a power transferred from the primary to the secondary side equal to P ,max , moreover, if r p < 0, the power is transferred from the secondary to the primary side). The calculation is performed three times within a for-loop, once for each phase. The three lines highlighted in gray (two square roots and the division by a variable) indicate the most time-consuming calculations for the DSP used. The remaining calculations, i.e., additions, subtractions, multiplications, and divisions by constants have a comparatively short computing time due to the existing Floating-Point Unit (FPU). Using single-precision floating-point variables, the used DSP (TMS320F28335) can achieve a total calculation time that is less than one switching period. Consequently, the HF phase shifts of each phase, ϕ p,aA (t ), ϕ p,bB (t ), and ϕ p,cC (t ), are updated once per switching period.
For completeness, also solutions with a 4 = b 4 = 0, i.e., based on a fourth-order polynomial according to (13), have been considered. The numerical results presented in Appendix B reveal that this enables a further increase of the theoretical power limit, P ,max , from 8.5 kW to 9.8 kW. 4 Apart from this, however, the solution with fourth-order polynomial does not show substantial advantages over the quadratic solution. For this reason and because of the significantly higher complexity of the fourth-order solution, this paper focuses on the quadratic solution.

IV. SIMULATION AND EXPERIMENTAL VERIFICATION
In this Section, the modulation scheme derived above for suppressing LF components in p when operating with f 1 = f 2 is verified using circuit simulations and hardware experiments. According to the explanation given at the beginning of Section III, the power flow between the ports ac 1 and dc 1 or between ac 2 and dc 2 has no effect on the LF components in the currents of the dc link capacitors. Therefore, to simplify the setup, no power is fed into or drawn from the terminals dc 1 and dc 2 . Instead, plain ac-ac operation with power flowing from ac 1 to ac 2 is considered, with a three-phase voltage source, which provides sinusoidal voltages according to (1) (with θ a,b,c ∈ {0 • , 120 • , 240 • }), connected to ac 1 and a threephase load connected to ac 2 .The three-phase load is formed by the star connection of three 5 resistors. Simulation and experiment both use the same converter components, according to Table 3, to allow for a direct comparison of the results.
The implemented control scheme is the same as described in Section II-C, except that instead of the HF phase shift the variable r p is constant. Fig. 12 depicts the result of the circuit simulation for converter operation according to S3 in Table 2, showing the primary-side voltages and currents in Fig. 12(a) and those of the secondary side in Fig. 12(b). Fig. 12(d) presents the waveforms of the instantaneous powers at the four ports of the D3ABC. The local average values of the instantaneous powers at the ports of the D3ABC are approximately constant, except for minor residual LF components. The phase powers of the DAB part, shown in Fig. 12(e), are shaped such that the sum of the three phase powers is almost constant, p = 8 kW. The remaining fluctuations in the power p are due to simplifications in the power calculation (e.g., piecewise linear currents in the inductors are assumed, thus neglecting the feedback effects of the voltages across the filter capacitances C f1 and C f2 ), voltage distortions due to dead-time effects, and time delays caused by the signal processing and the PWM units. Due to these influences, the effective DAB power in the three phases deviates from the calculated power, which results in the small fluctuations of the total power p . It is further apparent that the waveforms of p aA , p bB , and p cC are similar except for a time shift, indicating that condition (10) is also satisfied.  Fig. 12(c) shows the waveforms of the duty cycles and the HF phase shift, which the waveform of p aA is based on. This figure reveals the highly dynamic changes of the HF phase shifts that are required to meet the constraints (9), (10), and (11) defined at the beginning of Section III-A. Fig. 13 shows the hardware demonstrator of the D3ABC and reveals three of the four ports (port ac 2 is at the bottom of the hardware and therefore not visible on this picture). The demonstrator has been originally designed for operation from ac 1 to dc 2 (isolated rectifier operation) considering f 1 = f 2 as described in [21]. The maximum peak current in the leakage inductance for this operation with f 1 = f 2 is calculated to be I Lσ,1,peak ≈ 20 A, which is approximately half of the value that is calculated for operation with f 1 = f 2 as shown in Fig. 20. To avoid saturation of the leakage inductance when operating with f 1 = f 2 , all voltages are reduced by a factor of 1/2 as listed for S4 in Table 2. The reduction of the dc link voltages by 1/2 results according to (14) in a reduction of the power by a factor of 1/4, which leads to P = 2 kW.

B. EXPERIMENTAL VERIFICATION
To make the measurements obtained with the hardware demonstrator directly comparable with the simulation results, the two simulations in Figs. 7 and 12 are repeated with reduced power according to S4 in Table 2. Accordingly, Figs. 14 and 15(c) present both the simulation results and the measurement results in the same way, such that a direct comparison is possible. The simulation results shown in Fig. 14(a) and (b) are obtained when operating with constant HF phase shift, i.e., without the derived modulation scheme. The power in  Table 2

, w/o (a,b) and w/ (c,d) the proposed modulation scheme: (a) and (c) Dc link voltages, phase voltages, and phase currents of phases a/A on primary and secondary side. (b) and (d) Local average values of the powers of the three DAB converter stages and the resulting total power p .
the DAB part of the D3ABC, p , plotted in Fig. 14(b), shows pronounced LF components that, as Fig. 14(a) illustrates, lead to variations in the dc-link voltages and distortions in the phase currents. The simulation results obtained with the derived modulation scheme depicted in Fig. 14(c) and (d) show that the LF components in p almost disappear and therefore the fluctuations of the dc-link voltages are much smaller. Fig. 15 depicts the measured waveforms during a time span of 50 ms. Fig. 15(a) shows the primary-side dc link voltage, phase voltages, and phase currents and Fig. 15(b) depicts secondary-side dc link voltage, phase voltages, and phase currents. Fig. 15(c) shows the dc link voltages, the phase voltages, and the phase currents of phases a/A, i.e., both the primary side and secondary side. Fig. 15(a) reveals a phase shift of 180 • between the phase voltages and the phase currents, indicating rectifier operation at ac 1 . The waveforms in Fig. 15(b) of the output-side phase voltages, measured from the terminals to the star point of the load, are sinusoidal with a frequency of f 2 = 77 Hz and in phase with the currents, indicating inverter operation at ac 2 . The measurement shown in Fig. 15(c) agree well with the simulation results in Fig. 14(c). Specifically, the dc link voltages, v dc,1 and v dc,2 , show almost constant waveforms, indicating that the LF power pulsations are eliminated by the modulation  Fig. 14(c). Specifically, the dc link voltages, v dc,1 and v dc,2 , show almost constant waveforms, indicating that the LF power pulsations are eliminated by the modulation scheme.  , v dc,1 and i link,1 , or the voltages and currents of the three  switching nodes (see v n,a and i 1,a highlighted for phase a). scheme. A direct measurement of the power in the DAB part of the D3ABC, p , would show the elimination of LF power pulsations even better. However, the power p is difficult to measure. Fig. 16 shows two possible measurement methods to determine p . The first method requires the dc link voltage and the current in the dc link, v dc,1 and i link,1 . These measured values, multiplied and averaged over a switching period as in (7), result in p + p ac,1 . Based on this measurement result, the waveform of p can be determined if the waveform of p ac,1 is measured with, for example, a power analyzer. However, i link,1 is not accessible, because this current is distributed over a planar conductor configuration, which realizes the connection between the dc-link capacitance and the semiconductors to keep the commutation loop inductance as small as possible. The second method requires the voltages and the currents at the three switching nodes (e.g., v n,a and i 1,a marked in Fig. 16 in case of phase a). These measured values, multiplied for each phase, averaged over one switching period, and summed up over all three phases, also give p + p ac,1 . These voltages and currents are accessible, but both contain main switching frequency components. For this reason, the measurements of the powers at the switching nodes are not feasible with the available measurement equipment, e.g., the available power analyzer.
In a second experiment, the capability of the presented modulation scheme is further assessed by generating a threephase voltage with time-changing frequency, f 2 , and modulation index, m 2 , at the port ac 2 . An application scenario could be an asynchronous machine with V/F control, i.e., the voltage of the motor is increased proportionally to the frequency, ramping up the asynchronous machine at port ac 2 from standstill. In this context, the voltage sources at port ac 1 remain unchanged. At port ac 2 , the asynchronous machine is emulated by inductors, which are connected in parallel to the load resistors.   Fig. 17(a) is measured with a pure resistive and Fig. 17(b) with a resistive-inductive load connected to ac 2 . During the first 100 ms of the measurement, v ac,2 A = i ac,2 A = 0 apply. Accordingly, a small amplitude results for the primary-side phase current, i ac,1a , since the power drawn from the voltage sources only has to cover the losses of the converter and the reactive power demand of the input filter. After t = 5 ms, the line frequency, f 2 , and the modulation index at port ac 2 are increased at constant rates of 20 Hz/s and 1.07 s −1 , respectively. At the same time, the amplitude of the phase current of the primary-side phase a, i ac,1a , increases proportionally to the output power, which increases quadratically over time. At t ≈ 750 ms, the D3ABC reaches the final output frequency and amplitude of 15 Hz and 80 V, respectively. During the entire process, the primary-and secondary-side dc link voltages, v dc,1 and v dc,2 , remain constant.

V. CONCLUSION
This paper proposes a duty-cycle dependent phase shift modulation scheme to prevent LF power pulsations in the D3ABC. Such LF power pulsations occur, e.g., if the D3ABC is operated with different line frequencies, f 1 = f 2 , at its primary-side and secondary-side ac ports. Compared to a previous study [29], the new approach increases the transmittable power of the DAB part by a factor of 2.9, i.e., from 2.7 kW to 8.5 kW.
The effectiveness of the developed modulation scheme is verified by means of circuit simulations and experimental evaluations. The circuit simulations are conducted for an output power of 8 kW, which is delivered to a three-phase resistive load at the secondary-side three-phase port ac 2 . The rms values of the primary-side and secondary-side phase voltages are V ac,1 = 230 V and V ac,2 = 115 V, respectively, and the line frequencies are f 1 = 50 Hz and f 2 = 77 Hz, respectively. The simulation results confirm constant power in the DAB part, resulting in approximately constant dc link voltages The experimental verification conducted for f 1 = 50 Hz and f 2 = 77 Hz confirms the proper operation of the proposed modulation scheme, as well. Since the realized converter was designed for a power transfer between the ports ac 1 and dc 2 , and power transfer between the ports ac 1 and ac 2 leads to higher currents in the power stage of the D3ABC, the experimental verification has been conducted for a reduced power of 2 kW and the voltages have been halved. The measured voltages and currents agree well with the simulation results.
In a second experiment, the operation with time-varying rms values and frequencies of the voltages at port ac 2 is investigated. A possible application of this is the V/F control of an asynchronous machine. In this operating scenario, the dc link voltages also exhibit constant characteristics. This indicates that the described modulation scheme remains effective even in the case of time-varying modulation indices and/or line frequencies.

A. OPERATING MODES OF THE DAB CONVERTER PART
Since the three converter phases of the D3ABC can be considered separately, only the DAB part of one converter phase is examined in this Section. Accordingly, simplified designations for the voltages at the switching nodes and the current in the DAB converter inductance can be used. For example, if phase a is considered, applies. According to (7), the power transferred in a DAB converter phase depends on the characteristics of v 1 , v 2 , and i 1 . Accordingly, the duty cycles D 1 and D 2 and the HF phase shift ϕ p that are present during a switching period have an impact on the power transferred in a DAB converter phase.
For the evaluation of (7), it is assumed that the inductor current waveform, i 1 (t ), can be approximated by a piecewise  linear function, as shown in Fig. 18. Thus, the integral in (7) is separated into time intervals with constant values for v 1 and v 2 , i.e., intervals during which i 1 (t ) changes linearly, and the determined subexpressions are summed up.
The operation with different input and output frequencies, f 1 = f 2 , leads to different functions for the duty cycles on the primary and the secondary sides, D 1 (t ) = D 2 (t ), cf. (5) and (6). As a consequence, it turns out in the course of the evaluation of (7) that a distinction must be made between a total of six different operating modes, which are illustrated in Fig. 18. However, it is found that the operating modes V and VI are redundant with respect to the transferable power, but lead to transformer currents with increased rms values. Therefore, the presented modulation scheme only uses the operating modes I to IV. Furthermore, maximum positive power is achieved with mode III and minimum negative power with mode IV. Table 4 lists the conditions which must apply for a certain operating mode to be present, as well as the resulting expressions for the HF phase shifts for the various operating modes. Table 5 presents the power limits depending on the considered operating mode. Further details, e.g., the description of an algorithm used to determine the current operating mode, are described in [29].

B. RESULTS OF THE NUMERICAL ANALYSIS
This section describes the implementation of the procedure used for numerical verification of the results in Appendix B1 and discusses the obtained results in Appendix B2.

1) NUMERICAL DERIVATION OF THE MODULATION SCHEME
The numerical procedure is used to numerically determine valid values for the coefficients a 0 , a 1 = b 1 , a 2 = b 2 , and a 4 = b 4 , i.e., values that satisfy condition (11). Regarding the studied operating point, the voltages given for S3 in Table 2 are considered, leading to m 1 = m 2 = 0.81. The component values considered are listed in Table 3. Loads on the dc ports are omitted, i.e., solely ac-ac operation is considered.
In the subsequent computational run, compliance with (11) is checked for each of the 200 × 200 × 200 combinations of coefficients. For this purpose, n D = 100 evenly distributed values are calculated for each duty cycle, D 1 and D 2 , within the ranges defined by (15) and (16), e.g., D 1 ∈ {0.095, 0.103, 0.111, . . ., 0.905}. For each of the n D × n D combinations of duty cycles, C D ∈ {(0.095, 0.095), (0.103, 0.095), (0.111, 0.095), . . ., (0.905, 0.905)}, the value of p that results for the currently considered coefficients is calculated according to (13). This value must be in between the minimum and the maximum power of the D3ABC for each duty-cycle combination of C D (P IV,min and P III,max , respectively, in Table 5). If the power is outside these limits, the corresponding set of coefficients is marked as invalid.
After this computational run, the ranges of invalid coefficients are examined in order to enable a refinement of the resolution of the coefficients. For example, if the results for the boundary regions of a 0 ∈ {−10.0, −9.9, −9.8} and a 0 ∈ {9.8, 9.9, 10} are marked as invalid for any combinations of a 1 and a 2 , the following calculation run is performed for −9.8 ≤ a 0 ≤ 9.8, again for 200 uniformly distributed values. These boundaries are checked and adjusted individually for each coefficient. The above described computational run is repeated until the boundaries do not change between two runs. Table 6 lists the resulting boundaries. For a 4 = 0 the analysis is the same as for a 4 = 0. However, since it turned out during  determined boundaries for a 0 , a 1 , a 2 , and a 4 for  quadratic and fourth-order polynomials for p , cf. (13).
the investigation that a 1 = 0 leads to most valid solutions (an indication of this is also the narrowly defined range for a 1 in Table 6), the analysis for a 4 = 0 was performed for a 1 = 0. The boundaries for a 4 = 0 are also given in Table 6.
Three different criteria are used to further assess suitable values for the coefficients a 0 , a 2 , and a 4 . The first criterion is the square of the rms value of the current into the switching node of a primary-side half-bridge (e.g. i 1,a in case of phase a, cf. Fig. 1), since this is a measure for the conduction losses in the converter. 5 The second criterion is the peak value of the current in L σ , which is proportional to the peak value of the magnetic flux in the core of L σ and is thus a measure for the size of the inductor's magnetic core. 6 The third criterion is the switching losses of the primary-side and secondary-side semiconductors, which are calculated based on the measured losses published in [32] and [33], respectively.
Due to the ac-ac operation of the inverter, the voltages and currents in each phase of the D3ABC change continuously. Therefore, the global time average values of the above evaluation criteria are calculated in a final step, i.e., the average values that result for a duration that approaches infinity, T → ∞. Provided that the ratio between the two ac frequencies, f 1 / f 2 , is an irrational number, 7 this average value of x(D 1 ,D 2 ) can be calculated according to dαdβ.
(30) Using the substitution rule, the double integral from (30) can be rewritten into a double integral with respect to D 1 and D 2 , 5 The rms value of the current into the switching node of a secondaryside half-bridge shows a similar characteristic and is therefore not explicitly shown. 6 At a given total power, the peak currents in the primary-side and secondary-side filter coils, I Lac,1,peak and I Lac,2,peak , are practically independent of the investigated coefficients and were therefore disregarded. 7 The effective period of the superposition of two sinusoidal signals with different frequencies approaches infinity, T → ∞, if the ratio of the two frequencies is irrational. This guarantees that each duty-cycle combination occurs once within the range defined by (15) and (16). For the case considered in this paper, i.e., f 1 = 50 Hz and f 2 = 77 Hz, the effective period is 1 s and thus, considerably higher than the periods of the two line frequencies. Accordingly, (30) approximates the mean values very well for this case.
Here, F D 1 (D 1 ) and F D 2 (D 2 ) can be considered as density functions and the product F D 1 F D 2 , shown in Fig. 19, can be understood as the joint probability density function of the occurrence of the duty-cycle combination (D 1 , D 2 ). Fig. 20 presents the results for the global average values of I 2 1,rms , P sw,1 , and P sw,2 and the global maximum value of I Lσ,1,peak in a converter phase with respect to the total power of the D3ABC. The green areas represent the results calculated by numerical analysis, which are obtained by choosing a quadratic polynomial for p , i.e., a 4 = b 4 = 0. The red dashed curves show the results that are obtained if the coefficients are calculated according to (28). A direct comparison of these two results indicates that the analytically calculated coefficients can be used to achieve practically the minimum rms currents. In addition, near-optimal peak currents in L σ and switching losses are obtained. The maximum transmissible power is P ,max,D 2 = 8.5 kW which, apart from a slight deviation of 20 W (corresponding to 0.2 %), agrees well with the power calculated in Section III-B.

2) DISCUSSION OF CALCULATED COMPONENT STRESSES
The blue areas represent the additional solutions that can be obtained if a fourth-order polynomial is chosen for p . It is mainly noticeable that the maximum transmittable power can then be increased to P ,max,D 4 = 9.8 kW. Apart from this, small reductions of as much as −3 % in peak current values in L σ can be achieved. However, a detailed analysis shows that this comes at the cost of an increase in the current rms values I 1,rms and I 2,rms , e.g., at P = 8 kW both  Table 2 and Table 3, respectively and f 1 = f 2 is assumed. (a) Global time average value of the square of the rms current into a switching node on the primary side. (b) Global maximum value for the peak current in the leakage inductor. (c), (d) Global time average switching losses for a half-bridge on the primary and secondary side, respectively. The black dotted line corresponds to the resulting component stresses for the modulation scheme presented in [29]. The red dashed line corresponds to the values obtained with the modulation scheme presented in this paper. The presented results have been determined for pure ac-ac operation, from ac 1 to ac 2 . Since the converter is considered lossless, P˝is equal to the power transferred from ac 1 to ac 2 . I 2 1,rms T →∞ and I 2 2,rms T →∞ increase by 2 % respectively. Similarly, the switching losses depicted in Fig. 20(c) and (d), can be reduced by 6 % (for P = 3.2 kW) and 3 % (for P = 5.2 kW). However, this improvement is associated with an increase in I 2 1,rms T →∞ and I 2 2,rms T →∞ by 4 % and 2 %, respectively. Due to the limited advantages and the substantially higher effort required to analyze and implement the approach using the fourth-order polynomial for p , it is not considered further in this paper.
The black dotted lines in Fig. 20 refer to the results obtained with the approach proposed in [29], i.e., for p = P /3 = constant, which is equivalent to a 1,2,4 = b 1,2,4 = 0. Accordingly, the solutions calculated with this approach represent a subset of the solutions discussed in this section. Direct comparison shows that even this very simple approach leads to near-optimal results for the chosen criteria. However, this choice of coefficients has the disadvantage of a comparatively low value for the maximum power of P ,max,D 0 = 2.9 kW. Finally, Fig. 21 depicts the values of those coefficients that lead to minimum current rms values for the quadratic approach at given power P . In Fig. 20(a), these are the points located at the bottom edge of the green area. As can be seen from Fig. 21, the values of the coefficients are approximately proportional to the power P . In addition, the values of the coefficients at maximum power, P = 8.5 kW, agree with the values calculated with (26). Based on these results, the linear scaling of the coefficients is proposed according to (28).