Reconfigurable Photovoltaic Emulator for Differential Diffusion Charge Redistribution Solar Modules

Evaluating, validating, testing, and performing research on hardware components that are connected to actual solar photovoltaic systems can be challenging; photovoltaic emulators are a common practical approach. In particular, addressing emulation for the crucial research topics of partial shading and cell mismatch is important. Differential diffusion charge redistribution is a switched-capacitor architecture using differential power processing for performing maximum power point tracking with cell-level granularity using only a single module-level converter. Among the prohibitive challenges is preventing damage to the module-embedded integrated circuits for the corner cases during fault and failure testing of connected hardware components including power converters. Emulators not only benefit research, but also product development and manufacturing of hardware components and power converters. This paper investigates a reconfigurable linear emulator with an analog controller for photovoltaic modules configured for differential diffusion charge redistribution. Cell mismatch and partial shading are shown to be equivalent and that the averaged behavior of these switched-capacitor solar photovoltaic modules can be represented by two separate continuous-time circuits that are coupled by feedback and constraints leading to an emulator design that is demonstrated through a hardware prototype.


I. INTRODUCTION
Solar power is one of the greatest alternative energy resources with photovoltaics (PV) as the most prevalent harvesting platform. However, evaluating, validating, testing, and performing research on hardware components that are connected to actual PV systems can be challenging [1]. Temperature dependency along with cell variation and mismatch, which are time-dependent, often result in poor repeatability, and together with needing large physical space are among the obstacles to using actual solar PV panels/modules [1], [2]. Furthermore, to illuminate PV modules, a high-power controllable light source [2] is typically needed, making the required power supply bulky and expensive [3]; otherwise, one would struggle with the high variability of actual solar illumination [1].
In particular, there are additional challenges with diffusion charge redistribution (DCR) [4] and differential DCR (dDCR) [5] solar PV modules because they contain integrated circuits (ICs). Preventing damage to prototype ICs is an additional concern that arises while performing actual-PV research on converters or inverters while connected to these modules or while trying different control algorithms; the risk is particularly great for the corner cases encountered in fault and failure testing.
Cell mismatch and partial shading are crucial issues in solar PV systems. Reduction of accessible power, non-convexity in maximizing output power, and hotspots are some of the problems that arise due to mismatch and partial shading. In one example, 10% shading of a solar PV module can result in 30% total power loss [6]. Hence, addressing the partial shading and mismatch problems continue to be crucial research topics in solar PV systems-central maximum power point tracking (MPPT) [7], distributed MPPT [8], and differential power This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ processing (DPP) [9]- [18] are among those being investigated. Most of the DPP methods require external energy storage components per PV element including capacitors [9], [11], [12], inductors [13], [14], or transformers [10], [15]- [18].
DCR [4] is a switched-capacitor solution which enables one to perform MPPT with cell-level granularity using only a single module-level converter [19] with dDCR as an architectural extension for DPP. DCR and dDCR architectures rely on the intrinsic diffusion capacitance of the solar PV cells and do not require external energy storage elements. There have been efforts to use charge balancing of cells at the sub-module level, but not the cell level in [20], [21]. These methods use external capacitors for energy storage instead of the intrinsic diffusion capacitance of the solar PV cells. Recently, a modified DCR topology had been used to address cell and illumination mismatches in solar roofs for plug-in hybrid electric vehicles (PHEVs) [6]. In comparison to dDCR, [6] does not perform DPP and has higher conduction losses than a comparable dDCR solar PV module. As with conventional solar PV modules, having a PV emulator for DCR and dDCR not only benefits research, but also testing and validation of hardware components and power converters in product development and manufacturing.
Generally, a PV emulator consists of two important parts: (1) the controller, which includes a PV model reference, and (2) the power stage. There are two types of controllers in the literature: analog and digital controllers; and two types of power stages: switching and linear [22].
Emulator controllers use analog or digital control loops together with analog representations, digital calculations, or digitally-stored tabulations of PV models as references [2]. Analog controllers are typically implemented with operational amplifiers (op-amps). Digital controllers together with their references have been implemented on different computational platforms [2] including dSPACE [3], [23], DSPs [24], [25], microcontrollers [26], FPGAs [27], and ARM processors [28]. Examples of analog representations of PV models as a reference include using an actual PV cell [29], [30], a photosensor [31], an analog circuit [32], and a series-diode stack [30]. Digitally-implemented references are typically more flexible; for example, parameter changes to the PV model like temperature and illumination level can be imposed easily. However, digital implementations have a drawback in that currentvoltage relationships are exponential, making quantization error a potential issue in either or both the analog-to-digital or digital-to-analog converter.
Switching-converter-based PV emulators use a switching power converter that is controlled to replicate the output characteristics of a solar PV module. Different dc-dc topologies are used including buck [3], [23], [25], [27], interleaved buck [29], buck-boost [26], forward [28], and full-bridge [24]. The disadvantages to switching-converter emulators include potential instability from interactions with other power electronics such as MPPT converters due to switching frequency and harmonic intermodulation and higher order converter dynamics.
Linear emulators [22], [33]- [39] do not have instability problems from switching intermodulation and higher order dynamics that are typical of switching-converters. Furthermore, quantization error is not an issue when analog controllers are used. However, analog implementations are not as flexible in setting model parameters (e.g. temperature, illumination, and shading) as emulators that use digital controllers.
A power converter for dDCR solar PV modules was validated and tested using a configurable linear emulator with an analog controller in a previous paper [19]. This new paper in the following sections analyzes and explains in detail the dDCR module emulator and validates the capability of the emulator to replicate the averaged behavior of dDCR solar PV modules.
The main new contributions include: (1) showing that the averaged behavior of switched-capacitor dDCR solar PV modules can be represented by two separate continuous-time circuits that are coupled by feedback and constraints; (2) proving the equivalency of cell mismatch and partial shading; (3) demonstrating a design method for reconfigurable and scalable emulators for dDCR solar PV modules, which is easily capable of simulating mismatched conditions. This paper is organized by first briefly introducing DCR and dDCR solar PV modules, followed by showing that cell mismatch and partial shading are equivalent. Then, we show how the averaged behavior of the dDCR switched-capacitor system can be represented by two separate continuous-time circuits that are coupled by feedback and constraints, which leads to the implementation of the emulator. Finally, hardware results are presented to demonstrate that the emulator replicates the averaged behavior of dDCR solar PV modules.

II. DIFFERENTIAL DIFFUSION CHARGE REDISTRIBUTION FOR SOLAR PHOTOVOLTAIC SYSTEMS
Diffusion charge redistribution balances all the average voltages of the cells in a solar PV module by using the large intrinsic capacitance of solar PV cells as energy storage while charge is dynamically redistributed. Differential DCR is a method to extract the power so that only the mismatch power is processed by the dynamic charge redistribution.

A. PV MODEL
A commonly-used model for PV cells in PV emulator applications is the single-diode model [3]. The I-V relation of the single-diode model shown in Fig. 1(a) can be written [3] as where I is the PV cell current (A), V is the PV cell voltage (V), I ph is the photo-generated current (A), I s is the diode saturation current (A), R s is the equivalent series resistance ( ), R p is the equivalent parallel resistance ( ), α is the diode ideality factor, k is the Boltzmann constant (1.38 × 10 −23 J/K), T is the absolute temperature of the junction (K), and q is the electron charge (1.6 × 10 −19 C).

B. DCR AND dDCR CONCEPTS
DCR is a switched-capacitor solution to the problems from cell mismatch and partial shading in PV systems by using the intrinsic diffusion capacitance of solar PV cells together with integrated semiconductor switches. This technique increases energy extraction and improves MPPT efficiency under mismatch and partial shading [4]. In fact, it makes a solar PV module behave as a supercell [4] and enables us to perform MPPT with cell-level granularity using only a single modulelevel converter [19].
The diode capacitance C d in the single-diode model in Fig. 1(b) represents a significant amount of capacitance [4]. The intrinsic diffusion capacitance C d of a solar PV cell in [4] is as high as 10 μF. These intrinsic capacitances together with semiconductor switches form a switched-capacitor structure, which ultimately balances the average voltages among the solar PV cells. An example 3 × 2 DCR structure is shown in Fig. 1(c). However, this structure has one drawback in that all the power from the right string is necessarily processed through two switches, which are circled in Fig. 1(c); in other words, the current through these switches is not just the mismatch current as it for all the other switches, but rather the entire string current, hence causing a larger insertion loss [19].
To solve this problem, the dDCR architecture has been introduced [5] by adding a second port to the DCR architecture. An example 3 × 2 dDCR structure is shown in Fig. 1(d).
The dDCR architecture preserves DPP by ensuring that only mismatch power is processed by the switches. Since the dDCR architecture is a two-port structure, it needs a two-port converter [19] and the conventional one-port converters like a boost converter cannot be applied to dDCR solar PV modules. Similarly, the one-port PV emulators presented in the literature do not represent the behavior of the two-port dDCR solar PV modules; as an example, a one-port PV emulator cannot be used for evaluating and testing a two-port converter suitable for dDCR solar PV modules. Thus, a two-port PV emulator is investigated in this paper to replicate the averaged behavior of dDCR solar PV modules. Although, the focus of this study is emulating dDCR solar PV modules, the time-averaged analysis of the dDCR switched-capacitor structure introduced in Section III can be used for similar switched-capacitor structures in solar PV systems. Furthermore, the general concepts used for hardware implementation of the investigated linear emulator in this paper can be utilized to design conventional PV emulators.
It should be noted that, an important advantage of dDCR PV solar modules is that for practical implementations, where the losses from interconnects and switch resistances are small, the maximization of output power is convex with respect to: (1) the sum of the output currents, and (2) the proportion of the current from each of the two strings, even under mismatched/partial shading conditions [5]. This makes it possible to perform a simple two-dimensional perturb-and-observe MPPT to find the maximum power point [19]. As a result of this interesting property, the P-V curves of dDCR solar PV modules and also the investigated emulator in this paper always have only one peak in contrast to the possible multipeak P-V curves of conventional PV modules and emulators, even under mismatched/partial shading conditions. This will be validated in Section V.

C. DCR AND dDCR MODULES: PRINCIPLES OF OPERATION
Solar PV modules that use DCR and dDCR in its simplest form consist of ladder structures that form two strings of solar PV cells in series. Cells of each string are individually shorted to particular cells of the adjacent string via semiconductor switches. A DCR or dDCR structure with 2N + 1 solar PV cells consists of 2N + 2 semiconductor switches. Figure 1 shows two examples: a 3 × 2 DCR and dDCR structure, each consisting of 5 PV solar cells and 6 semiconductor switches. The switches are denoted in Figs. 1(c) and 1(d) by their phases: the ϕ a -switches alternately turn ON with the ϕ b -switches at 50% duty cycle. To clarify the principle of operation in DCR and dDCR solar PV modules, the corresponding switched-capacitor structures of a 3 × 2 dDCR architecture during ϕ a and ϕ b are shown in Fig. 2(a) and Fig. 2(b), respectively. Figure 2 shows that during each phase, the diffusion capacitance C d of each solar cell is shorted to the diffusion capacitance C d of a particular solar cell from the adjacent string via two particular semiconductor switches. As a result, the average voltages of the cells become equal, even under partial shading and cell mismatch [19].

III. DIFFERENTIAL-DCR EMULATOR: CONCEPTS AND PRINCIPLES
Typical implementations of diffusion charge redistribution in a solar PV module have open-loop dynamics in that the behavior of the switches is dependent only on a fixed clock; intermodulation effects can be eliminated by synchronizing connected power converters to this clock. Under these conditions, a continuous-time PV emulator can represent the averaged behavior of the dDCR switched-system well.

A. CELL MISMATCH AND PARTIAL SHADING EQUIVALENCY
Partial shading or shading mismatch is when PV cells within a single module are under different levels of solar illumination. In other words, the cells, each represented by Fig. 1(b), have different corresponding photo-generated current I ph . Cell mismatch, on the other hand, occurs when cells are physically different. In other words, the cells have different corresponding α, I s , T , R s , and/or R p in (1). In this section, we show that these two phenomena manifest as electrical equivalents.
Assume that for a given mismatched solar PV cell α, I s , T , R s , and R p have been changed to (α + α), (I s + I s ), (T + T ), (R s + R s ), and (R p + R p ). For this cell, the mismatch appears as This cell mismatch has a corresponding variation in photogenerated current I ph with the same voltage V and current I, which results in So, for each cell mismatch case ( α, I s , T, R s , R p ), there is an equivalent partial shading case ( I ph ), which corresponds to the same cell terminal voltage V and current I.

B. AVERAGED MODEL FOR dDCR SOLAR PV MODULES
In this section, the switched-capacitor analysis presented in [40] is used to model the time-averaged behavior of switched-capacitor dDCR solar PV modules. A dDCR solar PV module consisting of 2N + 1 cells is shown in Fig. 3(a).
Replacing the cells in the dDCR structure with the modified single-diode model, neglecting the resistors, results in Fig. 3(b) and Fig. 3(c) for ϕ a and ϕ b , respectively. In Figs. 3(b) and 3(c), q ϕ x,i denotes the charge flow of the element x during phase ϕ, where i represents the PV cell number or output node. During ϕ a , shown in Fig. 3(b), Kirchhoff's Current Law (KCL) for nodes N i results in for i = 1, . . . , N. For node N i during ϕ a , photo-generated charges q a ph,2i−1 and q a ph,2i enter the node; diode charges q a d,2i−1 and q a d,2i exit the node; and capacitor charges q a c,2i−1 and q a c,2i exit the node. Although (5) is clear for N 1 , it may not be obvious for other nodes unless one observes that for each node the sum of the intermediate charges, for example (q a int,1 + q a int,2 ) for node N 2 , is equal to (q a out,1 + q a out,2 ). It is worth noting that KCL for node N N+1 leads to an equation which differs from (5), because there is no PV cell in the right string connected to this node from the top. KCL for this node gives q a out,1 + q a out,2 = q a ph,2N+1 − q a d,2N+1 − q a c,2N+1 + q a out,2 .
for i = 2, . . . , N + 1. Again, for each node the sum of the intermediate charges, for example (q b int,3 + q b int,2 ) for node N 2 , is equal to (q b out,1 + q b out,2 ). During ϕ b , KCL for node N 1 leads to an equation which differs from (7), because there is no PV cell in the right string connected to this node from the bottom. KCL for this node gives Summing the charge flows in each node from phases ϕ a and ϕ b , (5)- (8), results in Note that, capacitor charge balance in steady state enforces for i = 1, . . . , 2N + 1, which leads to One observes that, (q a out,1 + q b out,1 ) and (q a out,2 + q b out,2 ) are the total charge of the first and second outputs V 1 and V 2 , respectively, over a complete switching period. Also, (q a ph,i + q b ph,i ) and (q a d,i + q b d,i ) are the total charge of the i th current source and the i th diode, respectively, over a complete switching period. The time-averaged currents can be obtained by dividing the charge flows by the switching period T where dDCR enforces equal average cell voltages by transferring electrical charge among the cells. This can be represented by the following DCR constraint where V d,i is the time-averaged voltage of the i th diode. In other words, even when there is a cell mismatch, which means or there is a shading mismatch which means where V and I refer to time-averaged voltages and currents, respectively. However, because cell mismatch is equivalent to shading mismatch, equality of all V d,i means that a variation in diode current can be transformed into a variation in photogenerated current Hence, we can make all I d,i equal and encapsulate all the mismatches in I ph,i . Rewriting (12) gives

C. EMULATOR CONCEPT: FEEDBACK AND CONSTRAINTS APPROACH
We take the time-averaged dDCR currents and voltages and map them to continuous-time currents and voltages in the analog emulator. Furthermore, we would like to simplify the dDCR structure by aggregating the current sources, separating the series-strings, and eliminating the switched-capacitor network while satisfying (14) and (19) using feedback and algebraic constraints. In this section, we show that the emulator in Fig. 4 is a correct simplification. Observe that, for Fig. 3(a), (14) results in This can be modeled by two series-diode stacks as shown in Fig. 4(a). It should be noted that, the average voltage difference of two series-diode stacks is V d /2. In other words, there is a small offset between V 1 and V 2 which can be approximately modeled by a single Schottky diode. For the emulator in Fig. 4(a) we want where

FIG. 5. Emulator implementation: (a) Power Stage; (b) Control Stage.
We use (21) and (22) to map the average currents in (19) to continuous-time currents in the emulator and write Now by comparing (19) and (24) one observes that which gives where I ph,avg is the collective average of the time-averaged photo-generated current of all the cells. The control scheme that enforces (20) and (26) for Fig. 4(a) is shown in Fig. 4(b). In other words, the emulator in Fig. 4 replicates the timeaveraged behavior of the dDCR structure in Fig. 3(a). The parameters needed to program the emulator are I ph,avg and N.

IV. EMULATOR: HARDWARE IMPLEMENTATION
The emulator elaborated in section III can be implemented using v be -multipliers [41], PFETs, op-amps, and difference amplifiers. A realization of the emulator shown in Fig. 4 is illustrated in Fig. 5.

A. POWER STAGE
The power stage of this emulator is linear and consists of closed-loop current sources and v be -multipliers.

1) CURRENT SOURCES
As shown in Fig. 5(a), each series-string uses a PFET in closed-loop as the current source. The current of the PFET is measured via a Hall-effect sensor, which outputs a voltage proportional to the current. An op-amp (A 1 or A 2 ) compares this voltage to a reference voltage coming from the control circuit in Fig. 5(b), creating an appropriate gate voltage for the PFET. The currents of each PFET would be proportional to the respective reference voltages V(I * 1 ) and V(I * 2 ). It should be noted that level shifting is not shown in Fig. 5 for clarity.

2) V BE -MULTIPLIERS
To reduce the number of discrete power devices, two seriesstrings of v be -multipliers denoted by v be-M are used instead of two series-diode stacks. In this way, for each side in Fig. 5(a), three v be -multipliers are used instead of 35 diodes (for a 70+1 cell module). It should be mentioned that the reason for using three v be -multipliers instead of one is the limit on thermal dissipation.
Each v be -multiplier consists of Darlington-connected BJTs and two resistors, which behaves like a power diode with an approximate voltage drop of where 2 is the multiplicity of the Darlington pair and 0.7 V is the approximate voltage drop of a silicon diode. Using v be -multipliers makes the emulator scalable, resizable, and easily reconfigurable by changing the values of R 1 and R 2 . It will be discussed later how cell mismatch can also be easily implemented by changing these resistors. As mentioned previously, there is a small offset between the voltages of the two sides from the extra cell, which can be well-approximated by a single Schottky diode. As mentioned in Section II, the general concepts used for hardware implementation of the investigated linear emulator in this paper can be utilized to design conventional PV emulators. As an example, if we put one current source and one bypass diode across each v be -multiplier, then multi-peak P-V curves can be produced as in a conventional PV emulator [36].

B. CONTROL STAGE
The control circuit in Fig. 5(b) realizes the controller in Fig. 4(b). This means that I * 1 and I * 2 are controlled in a way that (20) and (26) are satisfied.

1) SUBTRACTOR
V L and V R are subtracted using unity-gain difference amplifiers (A 3 , A 4 , and A 5 ), which corresponds to an error voltage. In fact, the positive (V + L and V + R ) and negative (V − L and V − R ) ports of V L and V R are subtracted using A 3 and A 4 , respectively. Then, the outputs of A 3 and A 4 are subtracted via A 5 .

2) INTEGRATOR
After the subtractor stage, the error voltage is integrated by op-amp A 6 , as shown in Fig. 5(b).   FIG. 6. A photograph of the hardware setup.

3) REFERENCE OUTPUT
The output of the integrator is in fact the reference of the first current source V(I * 1 ). Writing the equation for op-amp A 7 leads to where V(I * 2 ) is the reference of the second current source and V(I ph,avg ) is the reference of the average photo-generated current of the cells. Recall that the currents of the PFET current sources are proportional to the reference voltages, which can be written as and V I ph,avg = pI ph,avg (31) where p is a proportionality factor. Substituting (29)-(31) into (28) results in which leads to Now, by comparing (33) and (26) it can be easily obtained that to satisfy (26), it is sufficient to satisfy Thus, R 4 and R 5 can be changed to emulate dDCR solar PV modules of different sizes. Also, I ph,avg , corresponding to the illumination level, can be set by changing V(I ph,avg ) via a potentiometer. This enables the emulator to be scalable, resizable, and easily reconfigurable.

V. HARDWARE RESULTS AND DISCUSSION
A prototype of the dDCR emulator was constructed, evaluated, and tested in hardware.

A. HARDWARE SETUP
To vary output voltages and currents, the emulator was connected to the two-port converter discussed in [19]. A photograph of the system is shown in Fig. 6. In all the tests, the emulator was powered by a 27 V power supply (V bus in Fig. 5(a)) and the load of the two-port converter was a constant 5 A current sink. Automated hardware experiments were performed to change I 1 and I 2 , via the connected two-port converter. The output voltages and currents of the emulator were saved and maps of the emulator output characteristics under unshaded/matched conditions ( Fig. 7(a) and Fig. 7(b)) and three different mismatched conditions (Fig. 7(c) to Fig. 7(h)) were obtained. It should be noted that the raw data is filtered and reduced in Fig. 7. In the prototype, N is large (i.e. 35), so R 4 and R 5 are very nearly equal based on (34) and 10 k resistors were used for R 4 and R 5 . Also, the values of R 1 and R 2 were 127 and 27 , respectively. With these values, the voltage of each v be -multiplier varied between 0 V and approximately 8 V. Therefore, the output voltages of the emulator, V 1 and V 2 , varied between 0 V and approximately 24 V.

1) UNSHADED/MATCHED CONDITIONS
In this test, the behavior of the emulator under unshaded/matched conditions was evaluated. The experimental results are presented in Fig. 7(a) and Fig. 7(b). Figure 7(a) shows the experimental output contours of the emulator where the x-axis is the current ratio I 1 /(I 1 + I 2 ) and the y-axis is the total current of the emulator (I 1 + I 2 ). This result agrees with the simulation results for real switched-capacitor dDCR solar PV modules shown in [5] and shows the convexity of the total output power of the dDCR solar PV module with respect to (I 1 + I 2 ) and I 1 /(I 1 + I 2 ). Also, Trajectory 1 in Fig. 7(a), corresponding to a P-V curve slice at the power-optimal current ratio of 0.6, is plotted in Fig. 7(b). In this figure, the x-axis is V 1 and the y-axis is the total output power of the emulator. The P-V characteristic of the emulator is identical to that of a conventional solar P-V operating with a maximum power point of 100.3 W. Trajectory 2 in Fig. 7(a), corresponding to a P-V curve slice at the suboptimal current ratio of 0.3, is also plotted in Fig. 7(b). As shown, the maximum power point at this current ratio is 99.3 W which is smaller than the one at the power-optimal current ratio.

2) MISMATCHED CONDITIONS
In these tests, the behavior of the emulator under three different mismatched conditions was evaluated.
• Mismatched Condition A: To realize the mismatched condition, R 1 of v be-M5 was changed from 127 to 102 , which reduces the voltage and can, for example, represent partial shading. The experimental results are presented in Fig. 7(c) and Fig. 7(d). As shown, the experimental output contour has changed and the maximum power occurs at a different current ratio; furthermore, the maximum power has reduced. Trajectories 3 and 4, corresponding to a P-V curve slice at the power-optimal current ratio of 0.65 and a P-V curve slice at the suboptimal current ratio of 0.4, are plotted in Fig. 7(d). In this test, the P-V characteristic of the emulator at the power-optimal current ratio is identical to a uniformlyilluminated conventional solar P-V with a maximum power point of 98.4 W instead of 100.3 W. This demonstrates the result of an imposed mismatch on the emulator. Recall that cell mismatches are equivalent to shading mismatches, so this result could be interpreted as the behavior of the emulator under either cell or shading mismatched conditions. Note that this result agrees with the simulation results for real switchedcapacitor dDCR solar PV modules shown in [5] and shows the convexity of the total output power of the dDCR solar PV module with respect to (I 1 + I 2 ) and I 1 /(I 1 + I 2 ), even under mismatched/shading conditions. Also, the maximum power point at the suboptimal current ratio of 0.4 is 96.69 W, which is smaller than that at the power-optimal current ratio.
• Mismatched Condition B: To intensify the mismatched condition, R 1 of v be-M5 was changed from 102 to 73 . The experimental results are presented in Fig. 7(e) and Fig. 7(f). Again, the experimental output contour differs from that for the Unshaded/Matched Conditions and Mismatched Condition A with the maximum power occurring at a different current ratio. Also, the maximum power has further decreased. Trajectories 5 and 6, corresponding to a P-V curve slice at the power-optimal current ratio of 0.35 and a P-V curve slice at the suboptimal current ratio of 0.7, are plotted in Fig. 7(f). In this test, the maximum power point is 93.35 W at the power-optimal current ratio and is 92.96 W at the suboptimal current ratio of 0.6.
• Mismatched Condition C: Mismatched Condition B was intensified by changing R 1 of v be-M2 from 127 to 102 . The experimental results are presented in Fig. 7(g) and Fig. 7(h). Trajectories 7 and 8 shown, corresponding to a P-V curve slice at the power-optimal current ratio of 0.48 and a P-V curve slice at the suboptimal current ratio of 0.8, are plotted in Fig. 7(h). In this test, the maximum power point is 88.92 W at the power-optimal current ratio and is 87.33 W at the suboptimal current ratio of 0.8.
To compare the behavior of the emulator under the four above-mentioned conditions, the P-V curves of the emulator for Trajectories 1, 3, 5, and 7 are collectively plotted in Fig. 8. As expected, the maximum power of the entire emulator reduces by imposing more severe mismatches, yet the curves are convex for maximization.

VI. CONCLUSION
In this paper, the critical concerns in solar PV modules of cell mismatch and partial shading were shown to be equivalent. Then, it was shown that the averaged behavior of switchedcapacitor dDCR solar PV modules can be represented by two separate continuous-time circuits that are coupled by feedback and constraints. From this, a reconfigurable and scalable linear emulator for dDCR solar PV modules was investigated, which not only readily simulates mismatched conditions, but is also easy to implement in hardware. A prototype of the emulator was built and the capability of the emulator to replicate the averaged behavior of dDCR solar PV modules was demonstrated. The modeling and circuit strategies described in this paper are potentially useful in the design and analysis of continuous-time emulators for switched-capacitor circuits.