Topology, Design, and Characteristics of a Modular, Dynamic 100 kA Surge Current Source With Adjustable Current Shape

To guarantee sufficient surge current fault protection for power electronic converters, power semiconductors have to be tested under appropriate surge current conditions. Standard maximum surge current values include the permissible fault current amplitude, or the I2t-value; however, they might not be sufficient to describe a power semiconductor's performance under all potential fault conditions. Surge current sources based on passive components are state-of-the-art, but are limited to usually only one specific current waveform. This article describes the topology and the design of a new modular and highly dynamic surge current source for power semiconductor tests with adjustable current waveforms. The new modular converter concept is introduced, with two potential operation modes: High current mode (HCM) and dynamic current mode (DCM). The requirements for the surge current tester are defined, and the electrical and mechanical design are described, including the modulation scheme and control. Experimental investigations prove the function of the current source with peak currents up to 100 kA (HCM) and the realization of highly dynamic load current trajectories with peak currents up to 50 kA (DCM). The output current ripple is exceptionally small with a theoretical value of below 1%.


I. INTRODUCTION A. MOTIVATION
Power semiconductors are the key components of power electronics.They determine topology, design, and characteristics of converters and applications.For high power applications, diodes and thyristors are particularly important.Diodes play an important role in rectifiers and, as inverse diodes, also in voltage source converters (VSC) with IGBTs, IGCTs, or, e.g., SiC-MOSFETs.Thyristors are applied in high power converters such as high-voltage direct-current, medium voltage drives (e.g., LCI, cycloconverters), or high current rectifiers (e.g., electrolysis) and as protective devices (e.g., crowbar, bypass switch) in medium voltage converters, modular multilevel converters or doubly-fed induction machines (e.g., [1] and [2]).
One important device characteristic of power semiconductors is the overcurrent capability, which plays a major role in the design of a converter regarding fault events.The overcurrent ratings of diodes and thyristors are quantified using two values: the maximum surge current I TSM and the I 2 t-value.If the device surge currents do not exceed these values, the device manufacturer guarantees that the power semiconductors are not destroyed.
Both the maximum surge current I TSM and the I 2 t-value are defined for a half-sinusoidal current pulse with a pulse duration T P = 10 ms [3].These parameters are related to each other for a given sinusoidal current waveform as shown in the following equation [4]: While these specifications are suitable for power semiconductors in line-commutated converters, the current stress of diodes in VSC or thyristors as protective device (e.g., in crowbars in the rotor of doubly fed induction machines [5]) differ significantly from a half-sine current shape with a pulse duration T P = 10 ms.
For press-pack thyristors or diodes, a typical immediate failure mechanism associated with destructive surge currents is the melting of the silicon structure itself.This is triggered by current filamentation at localized hot spots caused by a thermal runaway effect based on the high intrinsic conductivity of silicon at high temperatures: the device becomes thermally unstable [6], [7], [8].
Surge current failures of diodes or thyristors in modules are typically caused by the electro-thermal stress of the module structure or relatively small chip areas.Depending on the location of the heat generation and the local conditions for heat dissipation, damage occurs at different points.It is known that for very short pulses with large amplitudes, the heat generated in the semiconductor cannot be dissipated and the semiconducting material melts.For pulses with longer duration and lower amplitude, the device failure typically occurs at the connection between chip and aluminum wire [9].
These different failure mechanisms imply that both the duration and the shape of the current pulse play a role in the overload capability of power semiconductors.A characterization with a half-sinusoidal current pulse with fixed pulse duration T P of 10 ms is a good indicator, but not sufficient for many applications.For this reason, many devices are tested in specific circuit configurations where the surge current's shape, amplitude, and duration are tailored to the application.The development, design, and realization of such test configurations is time consuming and expensive.To reduce this high expense for special circuit configurations, a pulse current source with adjustable current shape is required that can realize application-specific surge current waveforms.

B. REQUIREMENTS
Surge current capability is interesting for conventional power electronic devices like diodes and thyristors made from silicon, as well as, for example, IGBTs for automotive applications [10].It is also an important parameter for emerging semiconductor technologies, such as SiC-MOSFETs and SiCdiodes.The nominal maximum peak current of thyristors reaches into the range above 90 kA (see, e.g., [11], [12], and [13]), while the peak currents of, e.g., the body diode of a SiC-MOSFET is significantly smaller (e.g., 4.7 kA for a 2200 V, 750 A SiC-MOSFET [14]).Therefore, it is necessary to control the output current over a wide amplitude range.
As discussed, the current waveform heavily depends on the application and the operating conditions.In order to cover a wide range of applications, the current source must be able to realize the desired current waveform with high accuracy.This means fast current changes and a low current ripple through the device under test (DUT) are required.Thus, an accurate and fast control scheme for the adjustable current is necessary.

C. STATE-OF-THE-ART
The standard solutions for generating high-amplitude pulse currents are based on the usage of passive components, either as a resonant circuit or via capacitor discharge into a resistive load.Currents up to the MA-range are achievable, for example, in applications for lightning simulation [15] or railgun applications [16].This concept can be extended to repetitive pulse current sources based on recuperation of the residual energy left after each current pulse, e.g., [17] and [18].However, these solutions can only generate fixed current waveforms with specific frequencies and time constants.
As an alternative, Verevkin et al. [19] present a current source that can be programmed in terms of the output current waveform.The authors of [19] propose a massive parallelization of 9360 MOSFET power amplifiers.This analog approach leads to very high power losses in its power transistors (6.14 MW average during a 120 kA half-sine current pulse), which greatly limits the pulse duration (10 ms) and repetition rate (one pulse per minute).The maximum current amplitude is also highly dependent on the chosen waveform (120 kA for half-sine wave, 16 kA for trapezoidal wave).

D. CONTRIBUTIONS OF THIS ARTICLE
As discussed earlier, state-of-the-art surge current sources are limited in either current amplitude or flexibility of the desired waveform.Therefore, the authors aim to develop a surge current source that overcomes these drawbacks.The current source should meet the target parameters as listed in Table 1.
In order to meet all requirements, the authors developed a surge current source with two modes of operation.The high current mode (HCM) focuses on achieving a maximum output current of 100 kA through parallel connection of 32 halfbridges (HBs).In the increasing current slope, this approach maximizes the di DUT /dt, however, during decreasing current slopes, the di DUT /dt becomes dependent on the specific characteristics of the DUT.
To control the current during negative current slopes, the authors propose a parallel connection of 16 full bridges, which is called the dynamic current mode (DCM).This limits the maximum peak current to 50 kA.The absolute value for di DUT /dt is lower, but it is fully controlled during the entire current pulse.See also Table 2, Figs. 1 and 2.
The rest of this article is organized as follows.Section II presents the chosen topology as well as the electrical and mechanical design rules.The design for control hardware and software is given in Section III.Section IV presents the experimental verification of the correct operation of the apparatus.

II. DESIGN OF THE CURRENT SOURCE A. MODULAR CONCEPT
Adjustable current waveforms with amplitudes up to 100 kA, an extraordinarily low current ripple (e.g., I ripple,DUT < 1%) and low losses encourage a modular topology of parallel connected cells with staggered switching.
Figs. 1 and 2 show the chosen topology for one cell and a block diagram of the modular converter.Each cell consists of a dc-link capacitor C DC and two HBs with an output inductor L out each.For reasons of safety, a dc-link voltage in the low voltage domain (below 1500 V dc) is required.An  advisable selection for power semiconductors should focus on 1.7 kV IGBTs.Based on availability and price, the high power (1700 V, 1800 A) HB IGBT-modules FF1800R17IP5 from Infineon are chosen as power semiconductors (datasheet: [20]).HB modules have the added benefit of a physically small circuit and thus potentially low stray inductance.It should be noted that other types of IGBT switches could also be a viable alternative.
The cells can be configured to operate as two separate HBs or one full bridge.The current source consists of 16 cells.Eight cells, connected to each other by mutual copper bars, are arranged on each side (Fig. 2).Both halves are connected close to the DUT.This structure is very advantageous for mechanical reasons, mainly to reduce the occurring magnetic forces.
Fig. 3 shows an equivalent circuit model of the output circuit, including the DUT.The output circuit is characterized by the pulsed output voltage v out provided by the parallel connected cells, the inductance L eff , and the equivalent circuit of the DUT.
If the cells are connected in HB configuration, the HBs of each cell work independently from each other with equal or different duty cycles d y,x .This operation mode is referred to as HCM.The maximum output current amplitude is given by the parallel connection of 32 HB modules.The HB output voltage v HB,y,x (with x, y ∈ N and ) is either zero or corresponds to the dc-link voltage v C,x : v HB,y,x = {0, v C,x }.Thus, a rising or constant output current i DUT = f (t ) can be adjusted and controlled.However, the minimum output voltage of v out = 0 is the reason that a falling output current i DUT = f (t ) is determined by the inductance of the output circuit and the DUT characteristics (resistance, voltage drop).
If the cells are configured as full bridges the cell output voltage features three levels v FB,x = {−v C,x , 0, v C,x }.The option of positive and negative output voltages enables a control of rising, constant, or falling output currents i DUT = f (t ).Therefore, this configuration is called DCM.The maximum output current amplitude in DCM is given by the parallel connection of 16 full bridge cells and corresponds to half that of the HCM.

B. ELECTRICAL DESIGN CONSIDERATIONS
The electrical design considerations include the dimensioning of the dc-link capacitance C DC per cell and the cell output inductance L out per HB, as well as the switching frequency f C , while taking into consideration the properties of chosen semiconductor switches.As a result, the electrical behavior and limits of the surge current source can be defined.
The required output inductance is estimated based on the switching frequency and maximum permissible switch current (including ripple).A low switching frequency would be beneficial in terms of switching losses, however, a high switching frequency leads to a lower current ripple and/or a lower inductance L out .As a compromise, a switching frequency of f C = 3 kHz per HB is chosen.Interleaved switching results in an effective switching frequency of f S = 96 kHz.For N C cells in HCM (2 • N C HBs, respectively) the permissible ripple current per HB, I ripple,max , depends on the maximum peak output current I pk := max(i DUT ), and the maximum permissible repetitive switching current I CRM per switch The ripple current I ripple is defined as shown in Fig. 4. As can be seen from ( 2) both ripple and DUT-current contribute to the IGBT current.In order to maximize peak pulse current I pk , the ripple current has to be kept at a minimum (within the constraints set by other parameters).The actual ripple current in HCM for the HB y,x can be calculated by the voltage across the corresponding inductor L out during the time interval 0 ≤ t ≤ d x,y T C , with being derived from Figs. 1 and 4. Approximating both v C,x and v HB,y,x to be constant during one period T C , the numerator in (3) can be simplified to (1 − d y,x )v C,x .The integral can also be simplified as a multiplication.This leads to (4).The ripple current in HCM for HB y,x is dependent on various factors, including the capacitor voltage v C,x , the duty cycle of the HB d y,x , the switching frequency f C , and the output inductance L out .
To limit the ripple current, the following considerations are made.The switching frequency is limited by the thermal dimensioning of the IGBT.Both duty cycle d y,x (t ) and capacitor voltage v C,x (t ) are dependent on the DUT.The remaining way to limit ripple current, and thus increase the maximum DUT-current is by increasing the inductance L out .However, this presents a trade-off, as increasing the output inductance results in a decrease in the maximum di/dt and therefore limits the dynamic performance of the surge current source, while also increasing the mechanical dimensions.The current di/dt-limits imposed by the hardware -depending on dc-link voltage v C,x and output inductance L out -are listed in Table 2.
Fig. 5 depicts the maximum permissible current I pk,max versus duty cycle and capacitor voltage for a chosen output inductance of 50 μH.It also highlights the permissible curve for a 100 kA pulse.The 50 μH inductance does not permit every potential operation point.To protect the HB IGBTs, the test setup's controller does not permit operation outside of the depicted safe operating area (SOA).
Power semiconductor devices (such as diodes or thyristors) with a maximum surge current in the region around 100 kA usually have a forward threshold voltage of approximately V f,DUT ≈ 1 V or lower and an on-state resistance significantly lower than r DUT ≈ 1 m , as shown in, e.g., [21], [22], and [23].
In the following analysis, a forward threshold voltage of 1 V and a worst-case resistance of the entire system (DUT + test setup) of ESR 0 ≈ 2 m , as well as a capacitor charging voltage of 1.2 kV (charging prior to the current pulse) are assumed.
Under those conditions the curves for maximum peak currents I pk versus pulse duration T p (single pulse) for a sinusoidal, a rectangular, and a capacitor discharge current waveform are shown in Fig. 6.Alternatively, a pulse train of multiple current pulses is possible, albeit with a lower peak current per pulse, depending on the desired number of consecutive current pulses.
Under the assumptions made earlier, the amount of energy required for one 100 kA, 10 ms sinusoidal current pulse is approximately 100 kJ.For 16 cells, this results in a required cell capacitance of C C = 9 mF.The amount of stored energy is therefore W C ≈ 104 kJ.In practice, the capacitance per cell can also be a trade-off between stored energy and, e.g., physical size of the type of capacitor that is used.

C. MECHANICAL DESIGN CONSIDERATIONS
One main factor to consider for the mechanical design is the forces acting upon the conductors caused by the high peak current.Emphasis should be put on reducing occurring forces first, and reinforcing mechanical elements second.
Ampère's Force Law describes the dependence of the magnetic force F m between two thin, parallel conductors on their currents i 1 and i 2 , their distance r and the permeability μ 0 (with μ r ≈ 1 in air), per length l of the conductors.Three relevant conclusions can be drawn from ( 5): 1) The length l of conductors running high currents parallel to each other should be kept as short as possible.
2) The distance r between said conductors can be increased to decrease the force.
3) The absolute values of i 1 and i 2 being equal, the force is proportional to the peak current squared.The other extreme case would be conductors with no parallel current paths with a resulting mutual force of zero.This principle is adopted in the connection of the DUT to the copper bars connecting all cells.Fig. 7 shows a sketch of the DUT connection inside its enclosure.The current is fed into the DUT from two sides, each connection conducting half of the current amplitude.This way the full current I DUT is only present in the DUT itself.By halving the current, the force acting on each connection is divided by four.
The copper bars are mounted on two opposing sides of the test setup.One side can be seen in Fig. 9.The forces between both sides can be neglected due to their large distance apart.The forces between the two connections to the DUT enclosure can also be neglected, as they do not share a parallel current path.
As a result, only the forces within each of the copper bar connections are of interest.These should not be reduced by an increased distance between the conductors, since this would increase stray inductance and thus have a negative impact on the system's dynamics.Fig. 8 shows a schematic representation of the copper bars.The sketch displays the dimensions and spacing of the copper bar, as well as the direction of the forces in both HCM and DCM.
It should be noted that for DCM only two of four copper bars are conducting the current pulse.However, since the maximum current in DCM is half the maximum current in HCM this results in the same maximum current per copper bar independent from the operation mode used.The forces on the copper bars are simulated for both the entire length of the conductors of 1855 mm and for the maximum distance of 80 mm between the insulating clamps holding the conductors in place, as shown in Fig. 9.For these simulations, the free program FEMM is used, see [24].Relevant simulation results are also listed in Table 3.
The force on the entire copper bar is relevant for the insulating clamps, as they hold the copper bar construction together.In addition, the forces on the 24 clamps have been estimated using the German standard DIN EN 60865-1 [25].This results in a force of under 600 N per pair of copper bars and clamp.Since each clamp holds two pairs of copper bars, as seen in Fig. 8(b), the resulting force is less than 1.2 kN per clamp.Each clamp is held together by three M10 screws with a property class 8.8 -resulting in a nominal pretension force of (24.7...31) kN, depending on coefficient of friction [26].It is therefore at least an order of magnitude higher than the magnetic forces caused by the current pulse.
Fig. 9 shows a photograph of the complete surge current source.On the left side of the picture, the control platform (CP) can be seen attached to the wall, denoted as (a).On the bottom right (d), the (nickel-plated) copper bars are visible as well as the (white) clamps responsible for holding the conductors in place during the current pulses.Behind the copper bars the inductors (c) can be seen in the undercarriage of the setup.The cells (b) are sitting above.
As a final remark, the potential for a catastrophic DUTfailure has to be considered.To protect the system against heat, pressure, and UV radiation created by arcing and to ensure a fast turn-OFF of the entire current source in case of a DUT explosion, multiple safety features are implemented.These include a shrapnel-proof barrier around the DUT as well as a sound and shrapnel proof wall between the occupied control room and the unoccupied laboratory room (containing the apparatus), an overpressure vent, an active ventilation system, and an arc detection that triggers an emergency turn-OFF of the apparatus within one microsecond.

III. CONTROL DESIGN A. CP DESIGN
The control of the surge current source is orchestrated with a rapid prototyping CP based on a Xilinx Zynq 7015 System on a chip that was developed in-house.This chip features an Artix-7 FPGA and two ARM Cortex A9 processors with a clock frequency of 766 MHz [27].
The system utilizes one CPU core as a deterministic realtime core, running the FreeRTOS operating system, while the other CPU core is utilized for asynchronous processes running Linux.Both cores operate in an asymmetric multiprocessing system, communicating via RAM-based first-in, first-out (FIFO) buffers.The platform also includes an open-source data modification and visualization tool called LabAnalyser [28].The real-time core data tracer can transfer up to 400 Mbit/s of data to LabAnalyser via Linux.All the data can be displayed in real-time.
This control hardware and software framework are the basis of the control hardware for the surge current source.

B. IO REQUIREMENTS
As previously mentioned, the current source consists of 32 HBs that are used to control the current conducted through the DUT.Pairs of two HBs share the same dc-link.The necessary amount of sensor values as well as control signals is: -Sensor Values x Delta Sigma Clock To accommodate the large number of necessary inputs and outputs (I/Os), a distributed control approach was implemented using two CP, such as to double the number of available I/Os and CPUs.A common clock is utilized to parallelize the CPs and to ensure a shared time base.
Fast communication between the platforms is achieved by two 5 Gbit/s SFP ports, which allow for writing to a FIFO memory on the on-chip memory of the other CP.This scheme enables rapid sharing of sensor values, with a latency of less than 1.5 μs.The complete distributed control architecture, including the corresponding bandwidth of each bus, is depicted in Fig. 10.

C. DATA PROCESSING
One of the main objectives was to evenly distribute the CPU and pin utilization between the two CPs.Thus, both  As all 32 HBs shall be switched interleaved, the control cycle of the second CP is shifted by half a control cycle (see Fig. 11).
To digitize the analog sensor values, Sigma/Delta ( ) converters are used.The bit-stream of the converters is transferred via fiber-optics to the FPGSs of the CPs.In the FPGA, a SINC3/SINC1 filter-stage is used to decimate the bitstream.The modulation, a fast limit detection for the currents and voltages, the error handling and observing the CPU timing are implemented on the FPGA.
The timeline of one control cycle is depicted in Fig. 12 and is valid for both CPs.Each CP has a control cycle of 2 • T s , but the combination of both allows for one control action every T s .

D. MODULATION
Since the cells are in a buck converter mode, modulation techniques known for this purpose can be used.One technique is hysteresis control (HC), which involves constantly comparing the output current to upper and lower thresholds placed symmetrically around the desired current (see Fig. 13 top).This maximizes the dynamic range of the apparatus and results in a variable switching frequency.However, it requires a current measurement with a high bandwidth to accurately maintain the boundaries, and does not allow for phase shifting of the output currents to reduce the current ripple through the DUT.
Another technique, known as interleaved current mode control (CMC) [29], is similar to HC but results in a constant switching frequency.It reduces the output current if it reaches an upper threshold and increases it after a fixed time interval (see Fig. 13 middle).The switching times of the cells can be interleaved to greatly reduce ripple current through the DUT.However, this technique is only suitable for HCM.

TABLE 4. Comparison of Modulation Techniques for DC-DC-Converters
A third technique, interleaved Pulsewidth modulation (PWM), does not include current control or overcurrent protection as part of the modulation process.Instead, an overlaid digital current control and fast overcurrent protection are required.The output of the current control is a voltage, which then is synthesized by a pulse width modulator, using interleaved carrier signals in order to reduce current ripple through the DUT (see Fig. 13 bottom).
Table 4 summarizes the main characteristics of the modulation methods.Considering the requirements for flexibility regarding adjustable current trajectories, low current ripple, and suitability for both DCM and HCM, PWM was chosen as the most suitable modulation scheme.It offers the additional advantage of a fixed switching frequency, which simplifies the thermal design of the commutation cell.
Assuming PWM, the current ripple in the DUT I ripple,DUT depends on the circuit configuration (HCM: HB, DCM: full bridge), the duty cycle, and the capacitor voltage of the surge current source [30].With the given output inductance of 50 µH and the switching frequency of 3 kHz per IGBT, the resulting current ripple is depicted in Fig. 14 for both operation modes.The maximum current ripple is about 60 A in HCM and 30 A for the DCM.This equals 0.6‰ of the respective maximum current.

E. CONTROL ALGORITHM
The PWM requires an overlaid control algorithm.The authors propose a highly dynamic control scheme consisting of a feedforward controller, a current controller for the DUT-current, and a balancing controller.Since an asymmetric interleaved PWM is used, the control has to be executed with frequency of in order to achieve the maximum of the apparatus.

1) BASIC STRUCTURE
The controller design allows for two different methods of controlling the current: r Method I: Individual current control for each cell r Method II: Control of the resulting DUT-current Symmetrical cell currents are the essential advantage of the individual cell current control enabling a minimal DUTcurrent ripple and a similar thermal stress on the cells.However, this scheme has the disadvantage of a large time constant in the controlled system.To individually control each current, the mean value of each cell's output current must be measured and regulated.Assuming a switching frequency of the semiconductors of f C = 3 kHz, the maximum current sampling frequency for asynchronous modulation is 6 kHz per HB.
The second method is controlling the DUT-current.This is based on two assumptions: First, the cell parameters are equal for all cells and second, transient cell current imbalances might appear if they do not significantly unbalance IGBT or diode junction temperatures.
The effective switching frequency of the DUT-current is 96 kHz, which is the same as the SINC decimation frequency -converted sensor values.This means that the digitized DUT-current will not contain the switching ripple.One of the primary benefits of controlling the DUT-current using a system with a high sampling frequency of 96 kHz is the ability to determine control errors at a much faster rate than the previous method.However, this approach has the potential to result in unbalanced currents due to variance in inductors and different dissipative losses in steady state.To mitigate these issues, it is necessary to implement a balancing controller and to prevent current steps that could exceed the SOA of the used IGBTs.
Both methods were simulated using MATLAB, SIMULINK, PLECS.To demonstrate the dynamic behavior, a simple PI-controller using the symmetrical optimum [31] is used.
The dead time effects of the current control arise due to three components: a conversion/filter time T df , a calculation time T dc , and a modulation time T dm .Furthermore, the effective inductance for HCM and DCM L eff as well as the effective resistive losses R eff and the effective forward voltage of the IGBTs v IGBT,eff are defined.
The parameters used to calculate the controller gains are listed in Table 5.The table also shows the different rise t r and settling times t s .The rise time is defined as the time interval in which the sensor value reaches the target value for the first time.The settling time is the time interval in which the sensor value reaches a 5% band around the target value.
The different dynamic behavior is demonstrated by the step responses for Method I -DCM and II -DCM in Fig. 15.Fig. 16 shows the selected control structure with the best results, based on Method II.

2) FEED-FORWARD CONTROL
The output voltage v out for both HB (HCM) and VB (DCM) can be described using the target DUT-current i * DUT by (7) with the DUT resistance R DUT , the DUT inductance L DUT , and the threshold voltage drop across the DUT v f,DUT .The  corresponding duty cycle can be calculated via Using the known parameters (Table 5) as well as the trajectory of the target DUT-current i * DUT (t ), ( 7) shall be evaluated in real-time.Therefore, it is necessary to filter the trajectory to comply with the following boundaries, where the i * DUT is the change of DUT-current during one sampling interval T s .The first boundary assures that the converter can provide enough voltage to follow the current rise of the trajectory.Furthermore, the maximum peak current of every IGBT should not be exceeded.
As the currents of the IGBTs do not have to be equally balanced during transients it is further necessary to assure that the next switching IGBT can carry the current change in the next time step.
Using these three equations to filter the target current trajectory, (7) can be used to forward the necessary voltage.To assure that the current including the ripple (4) does not exceed I CRM the duty cycle is limited (12) in HCM and (13) The step response using the presented feed-forward structure is shown in black in Fig. 15.It can be observed that the settling time corresponds to the rise time.

3) BALANCING CONTROL
In order to maintain a balanced load distribution, it is essential to implement a balancing controller.The use of a proportional controller, which sets the mean value of all currents as the target value for each individual cell, proves to be adequate for this purpose.However, the design of this controller involves trade-offs between its regulation dynamics and the ripple current of the DUT.As the sum of balancing currents is always zero, the balancing process will not adversely affect the DUT current.Furthermore, the presence of switching ripple in the cell currents at a frequency of f c necessitates the implementation of a filter to calculate the ripple-free current value.A moving average (notch) filter with a window width of N C = 16 is an appropriate solution as it effectively eliminates the ripple.The delay introduced by this filter is acceptable as the dynamics of the imbalance occur at a slower rate than the required DUT current controller performance.
An active balancing of the capacitor voltages v C,x , with x = [1, 16], is not required for two major reasons.First, since the cells are of equal design and have equal parameters, and the currents are actively balanced, the resulting imbalance in the capacitor voltages is not significant; as shown in Section IV.Second, the dc links of the individual cells are connected for collective charging -however they are decoupled, each by resistors of 1 k per connection.Therefore, the parasitic currents caused by voltage imbalances are limited to negligible amplitudes.

IV. EXPERIMENTAL TEST RESULTS
Experimental investigations of the adjustable current source were carried out for a short circuit load and a thyristor (SCR) as DUT in both DCM and HCM.
The first series of test pulses was performed with a short circuit load.This is a demanding circuit configuration for the controller, since there is minimal dampening in the circuit.The second series of test pulses was performed with a thyristor as a load, which is a realistic example for future operation of the surge current source.
A half-sine current waveform is used as a benchmark in the following section, since conventional pulse current testers for I 2 t-tests on power semiconductors realize this current waveform.In addition, a current step waveform is used to show the high dynamics of the system.Subsequently, one example of a dynamic, freely configurable current waveform is presented to demonstrate the ability of the current source to realize arbitrary current trajectories.
The DUT current can be measured directly, e.g., with a Rogowski coil.However, the CP also calculates it as the sum of all cell currents according to (14) or (15), depending on the operation mode.

A. SHORT CIRCUIT LOAD
The short circuit load is especially important in HCM, as there is only little dampening in the circuit and the HCM cannot generate a negative output voltage.Fig. 17 displays multiple half-sine current pulses i DUT with peak currents of 20 to 100 kA and the corresponding set current trajectory i * DUT .The waveforms show a high accuracy for the rising slopes of the current pulse.However, there is significant deviation between set and measured currents for the falling slope.The reason for this is that the minimum output voltage is approximately zero for t > 6 ms.Obviously, the fall of the currents is determined mainly by the load parameters like resistance and stray inductance.The set trajectories for the falling currents are physically not realistic for HCM.
The ripple current is an important characteristic of the current source.It can be obtained for the individual HBs from Fig. 18(a) which shows a zoom of the rising current slopes  of all HB currents.It can, however, not be measured directly.As seen in Fig. 14, the output current ripple is expected to be in the order of < 1‰ of the maximum load current.It is therefore not measurable by a Rogowski coil with a nominal current in the range of more than 100 kA.Fig. 19 shows the capacitor voltages v C,x corresponding to the 100 kA pulse for the first 6 ms of the current pulse.A voltage ripple is clearly visible superimposed on the general discharge behavior during the current pulse.During the pulse, the capacitor voltages drift apart and show a maximum deviation of about 10% at t = 6 ms.This is considered irrelevant for the operation of the surge current source.
The ripple current can also not be calculated with sufficient accuracy from the cell currents because of bandwidth constraints in the signals measured by the CP.However, it is possible to calculate a deviation of the current i DUT measured  by the CP from the set current i * DUT (16).The result is depicted in Fig. 18(b).The absolute value of the deviation increases at the start of the current pulse and decreases for t > t r , as is expected according to Table 5 and Fig. 15.    the same parameters in DCM.In HCM, it is limited by the load resistance (as well as the surge current source's parasitic resistance).
The maximum current amplitude is the same in HCM and DCM, enabling a side-by-side comparison between both modes.The maximum of 40 kA is chosen for the comparison with the simulation (Fig. 15) and measurement (Fig. 24) of the step response with feed-forward deactivated -the resulting current does not exceed the 50 kA maximum.
Figs. 22 and 23 show the corresponding cell capacitor voltages v C,x for the 40 kA pulse in both HCM and DCM.The comparison of both figures highlights the fact that in DCM a recuperation of residual energy is possible.Both capacitance and average current are approximately equal for the cells.Therefore, the capacitor voltages are indirectly balanced.Minor deviations are observable, but not significant.
Fig. 24 shows a current step response with feed-forward deactivated.This corresponds to DCM-II in Fig. 15.The measured value for rise time t r = 0.44 ms matches the simulated value of t r = 0.38 ms with adequate accuracy.The measured settling time t s = 1.79 ms, however, deviates significantly from the simulated value of t s = 0.8 ms.This is caused by parasitic components, which are not perfectly emulated by the simulation.The observed differences are considered to have little relevance on the overall performance, especially since they do not appear with feed-forward control activated.

B. THYRISTOR LOAD
The second series of test pulses was performed with the (7500 V, 2100 A) SCR T1901N as a load [32].During the measurements, the SCR was kept in an on-state with a continuous gate current of I G ≈ 500 mA.Measurements were performed both in DCM and HCM.One noticeable exception is a current dip in the 50 kA curve at around 6.5 to 7 ms.This current dip is caused by a rapid increase of the DUT's on-state voltage v DUT .Fig. 26 shows this behavior in more detail.The current dip corresponds to a voltage spike of the SCR which indicates an overheating event of the power semiconductor.Analysis and explanation of the on-state overvoltage of the SCR are out of the scope of this article.However, an overvoltage of the DUT during high current stress is not unusual.Thus, the behavior of the current source regarding the on-state overvoltage is important.Figs. 25, 26, and 28 show that a sudden increase of the load voltage causes a deviation between the set trajectory and the DUT-current.However, the current controller is able to limit the deviation and to prevent a lasting deviation.The capacitor v C,x corresponding to the 50 kA current pulse are depicted in Fig. 27.They show no noteworthy peculiarities.The recuperation typical for DCM is clearly visible.
The comparison of the DUT current trajectory in HCM with short circuit and SCR load is depicted in Fig. 28.This figure illustrates the dependency of the falling load current on the load parameters in HCM.In contrast, DCM enables a freely adjustable falling current shape.Thus, DCM is preferable if the current drop must be faster than given by DUT parameters.Fig. 29 shows an example of an arbitrary, dynamic current waveform.The current trajectory traces the profile line of the Frauenkirche in Dresden.The authors chose this to demonstrate the dynamic characteristics of the surge current source in DCM, since the waveform contains both regions of a current slope up to di DUT /dt ≈ 60A/μs including rapid sign changes, as well as short, sub-ms current spikes (e.g., at 9.6 ms).

V. CONCLUSION
This article presents the methodology for the design and construction of a 100 kA surge current source for power semiconductor surge current tests.The current source is able to generate user-specified current trajectories over a wide operating range.The details written about the design process encompass both the electrical and mechanical components, as well as the control hardware and software that enable precise control of the output current with minimal ripple (<1‰).Experimental results verify the correct functionality of the new pulsed current source and illustrate its superior characteristics compared with state-of-the-art current sources.Other potential use cases for the current source include testing on electromechanical switches, connectors, and cables; for example, in the fields of industrial or automotive (electric vehicles) applications.

APPENDIX
The measuring instruments used to gather data for the diagrams depicted in this document are listed in Table 6.
Table 7 lists controller and cell parameters defined for the experiments within this article.configurations and loads.It should be noted that these parameters can differ greatly between experiments as they are influenced by the load itself as well as the connection between test setup and load.

FIGURE 1 .
FIGURE 1. Electrical schematic of a cell.(a) Connections of semiconductors, dc-link, and output inductances within a cell.(b) Connection of the outputs for HCM.(c) Connection of the outputs for DCM.

FIGURE 2 .
FIGURE 2. Block diagram showing the modular concept of the surge current source.The four connection points into the DUT enclosure are denoted as 1-4.

FIGURE 3 .
FIGURE 3. Simplified equivalent circuit for surge current source and DUT.

FIGURE 4 .
FIGURE 4. Definition of parameter I ripple in comparison to the average current I AVG .Display of one period T C = 1/f C with duty cycle d y,x • T C being highlighted as well as the slope di/dt of the rising current.

FIGURE 5 .FIGURE 6 .
FIGURE 5. Maximum DUT-current as a function of capacitor voltage and duty cycle considering the current limit of 3.6 kA per IGBT in HCM.As an example, the blue line depicts the measured capacitor voltage versus duty cycle trajectory for a 100 kA, 10 ms half-sine current pulse with a short-circuit load.

FIGURE 7 .
FIGURE 7. DUT (example: Diode) with two currents forming the total current I DUT .Note: The currents flow into the enclosure on opposite sides.

FIGURE 8 .
FIGURE 8. (a) Mechanical arrangement of the copper bars connecting the cells together and to the DUT (cross-section view, not to scale).(b) Qualitative display of the resulting forces in HCM.(c) Qualitative display of the resulting forces in DCM.

FIGURE 9 .
FIGURE 9. Photograph of the complete test setup.Highlighted parts: (a) Control platform, (b) one of the 16 cells, (c) two inductors belonging to one cell, and (d) copper bars and insulating clamps on one side of the setup.

FIGURE 10 .
FIGURE 10.Structure of the distributed CP for the surge current source.

FIGURE 11 .
FIGURE 11.Phase shifted control cycles of the two CPs, the control task of the second (red) control cycle is delayed by T s in comparison to the first control (blue).

FIGURE 12 .
FIGURE 12. Timeline of one control cycle.

FIGURE 13 .
FIGURE 13.Modulation techniques for dc-dc-converters.Top: HC.Middle: Interleaved CMC for three cells.Bottom: Interleaved PWM with three cells.

FIGURE 14 .
FIGURE 14.Current ripple through the DUT dependent on cell capacitor voltage and the duty cycle considering an equal duty cycle and capacitor voltage for all cells in HCM (left) and DCM (right).

FIGURE 15 .
FIGURE 15.Simulated step response (t = 0 ms) and disturbance response (t = 3 ms) of the control for DUT-current control (green), separated control of all cell currents (red), and separated control of all cell currents with feed-forward control activated (black).

FIGURE 16 .
FIGURE 16.Control structure with feed-forward control, balancing control, and control of the DUT-current.

Figs. 20 and 21
Figs. 20 and 21 depict multiple current pulses with peak currents ranging from 10 kA 40 kA for HCM and DCM, respectively.Both figures show rectangular current pulses with duration of 5 which test the apparatus' step response.In both Figs.20 and 21, the rise time t r of about 0.38 ms can be observed, as shown in Table5.The current slope is, in these examples, not limited by the capacitor voltages v C,x , with x =[1,16], and the output inductance L out of the HBs, but by the controller.The falling current slope is limited by

FIGURE 28 .
FIGURE 28.Comparison of target current trajectory i * DUT and DUT-current measured by Rogowski coils for a short circuit load and a thyristor as load, half-sine waveform, HCM; V C,x (t = 0) ≈ (400 . . .600) V, I pk ≈ 50 kA.

Fig. 25
displays several measurements of half-sine currents i DUT , as measured by the CP, with amplitudes in the range of I pk ≈ (5 . . .50) kA.The corresponding set current trajectories i * DUT are shown as well, but are barely visible due to being covered by the measured waveforms.

FIGURE 29 .
FIGURE 29.Example of a dynamic current waveform: DUT-current (measured by the control system) tracing a profile of the Frauenkirche in Dresden.Source of photograph [33].Thyristor as load, DCM; V C,x (t = 0) ≈ 300 V, I pk ≈ 25 kA.

TABLE 5 Controller Design Parameters of the
Table 8 lists experimentally estimated parasitic parameters of the test setup for different