Shipboard Control System Supported by Energy Storage Sizing to Meet the MIL-STD-1399 Limits for Pulsed Power Loads

This article addresses the new pulsed power load requirements for shipboard power systems introduced in the 2018 revision of the Military Standard 1399 Section 300, Part 1. With the number of pulsed loads increasing onboard modern ships, the ac distribution bus is susceptible to voltage and frequency abnormalities due to the limited inertia of the synchronous generators powering the ship. In this article, the strict limits imposed by the Military Standard 1399 are met with a system-level solution and a novel sizing method for the energy storage system (ESS). A targeted control system ensures that the power delivered by the ac bus has smooth transients, within the limits set by the military standard, thus reducing the stress on the shipboard power distribution system and the generators. A novel ESS sizing algorithm is proposed to identify the minimum number of supercapacitors for a given set of control parameters. The proposed control system is simulated and experimentally validated on a laboratory testbed built with silicon carbide (SiC) power converters managed by field programmable gate array (FPGA) control boards.


I. INTRODUCTION
The increased use of pulsed power loads (PPLs), such as sonars, radars, directed energy weapons, and communications' equipment onboard modern ships today, as well as those under development, increases the stress on the power distribution system and the electrical generators during operational transients. As PPLs require large amounts of current in short intervals of time, the synchronous generators used as sources on a ship's electrical distribution system respond by slowing down or accelerating causing voltage and frequency abnormalities. In response to this issue, the MIL-STD-1399 section 300 (MIL-STD-1399-300), Part 1 [1] was updated in 2018 to include new requirements for PPLs serviced by shipboard power systems. According to this military standard, "A pulsed load is user equipment that demands infrequent or repetitive power input that could be supplemented by energy storage" [1]. Energy storage systems (ESSs), such as batteries and supercapacitors (SCs), are typically used in support of PPLs with the appropriate control system that helps draw the required energy and restore it after the PPLs have discharged.

A. LITERATURE REVIEW
A variety of control strategies to regulate the power flow onboard ships in the presence of PPLs has been reported in the past 20 years, and in this section, we discuss [2] to [13] as relevant examples. Power quality problems arising from high-power pulsed loads are investigated in [2] where the energy stored in the generator and power converter are utilized to reduce voltage sags using a system-level model implemented in Simulink without experimental validation. In [3], an energy-storing capacitor interfaced by a buck converter is used and the benefits of the generalized profile-based control are demonstrated in comparison to limit-based control [4] and trapezoidal-based control [5]. The profile-based controller proposed in [3], however, is quite complex and aimed at solving a problem specific to the buck converter utilized in the power conversion system. A thorough review of the hybridization of sustainable energy sources, such as fuel cells, is presented in [6] with emphasis on PPLs. Although the use of SCs in hybrid energy sources is demonstrated to reduce the current that must be supplied by the batteries, this method would not allow to meet the limits in [1] because the PPL is located on the same bus as the ESS. Similarly, in [7], a solution is proposed to mitigate the effects of ac pulsed loads on a hybrid microgrid; however, the response of the control system cannot meet strict limits, such as those in [1]. If the PPL is located on the ac bus, although the ESS can reduce the pulse of power after the initial transient, this action is not fast enough to meet the limits specified in [1].
Many papers investigated power systems in which the PPL is connected to the shipboard medium voltage dc distribution bus. The authors of these papers propose decentralized control strategies, such as model predictive control [8], optimal control based on the Lyapunov function [9], or fuzzy logic controllers [10], to ensure optimal power sharing among the distributed resources on the shipboard dc bus. These papers present improvements with respect to typical proportionalintegral (PI)-based controllers; however, their results are not compared with the specifications in [1], which apply to the shipboard ac distribution system. Dual active bridges (DABs) are used in papers, such as [8] and [11], where complex control algorithms are used successfully to reduce the effect of the pulsed load on the shipboard power distribution system; however, their goals do not include meeting the strict requirements in [1]. It should be noted that the current-shaping control algorithm proposed to reduce the stress on the shipboard distribution bus presented in [11] could be a feasible solution, because its objective is to charge the ESS interfacing the pulsed load as fast as possible but in a controlled fashion. The focus in [12] is on how to restore energy in the ESS after the PPL event and the proposed cooperative control system includes several distributed resources onboard a ship. Recently, the optimum design of the passive components on a dc/dc converter used as buffer between the ESS and the PPLs was addressed in [13].

B. NOVEL CONTRIBUTION AND ARTICLE ORGANIZATION
The above summary points to a significant gap in literature with respect to addressing the requirements in the revised MIL-STD-1399 Section 300, Part 1 [1], which was published in 2018. Power converters onboard ships must meet all the requirements in [1], including meeting the limits it imposes for a PPL on the ac distribution bus. To the best of authors' knowledge, existing literature does not discuss this important standard, nor it proposes experimentally validated solutions to comply with its PPL limits. Further, previous literature does not present energy storage sizing methods linked to the proposed control system. We began to fill this literature gap with a previous conference paper [14] that presents a clear description of the new pulsed power requirements in [1] and a novel system-level solution to satisfy such requirements. This article expands and completes the work in [14] with a novel ESS design method linked to the novel control strategy proposed to limit the effect of PPL on the shipboard ac distribution bus. Further, new experimental results from a scaled testbed featuring a silicon carbide (SiC) dc/dc converter and grid-following voltage source inverter (VSI) are presented. If the pulsed load is connected directly on the ac bus, no control strategy can detect and reject the disturbance quickly enough to meet the requirements in [1]. The solution we propose is connecting the pulsed load to a dc bus regulated by a dc/dc converter drawing power from an ESS. Thanks to a novel controller based on the measured dc power, the dc bus receives scheduled power from a three-phase VSI, which is connected to the ac shipboard distribution bus where the generators are connected.
The rest of this article is organized as follows. The pulsed load requirements in the revised MIL-STD-1399-300 are discussed in Section II. Section III includes the proposed system architecture and control systems, which ensure that the limits in [1] are met on the ac bus. Modeling and simulation results are presented in Section IV. A novel ESS design method linked to a key parameter of the novel control system is presented in Section V. The experimental proof of concept for the control system is included in Section VI with measurements performed on a scaled laboratory prototype significantly improved with respect to the one used in [14], featuring a current-mode voltage control system for the dc/dc converter and using SiC devices and field programmable gate array (FPGA) control boards. Finally, Section VII concludes this article.

II. PPL SPECIFICATIONS IN MIL-STD-1399-300
High power for short durations of time is required by equipments, such as the railgun, the electromagnetic catapult used on the Ford-class aircraft carriers, directed energy weapons (lasers), as well as advanced radars and sonars [3], [15]. Pulsed loads are defined by the 2018 revision of MIL-STD-1399 Section 300, Part 1 [1] as either infrequent, if they occur "no more than once every 120 seconds," or repetitive, such as the dynamic real power waveform shown in Fig. 1 with a bold continuous line. In this article, we discuss how to deliver power for repetitive PPLs.
The pulsed load requirements apply to loads with a maximum instantaneous power greater than 100 kW and less than 2 MW, and "shall meet the pulsed power deviation limit in the time domain, the pulsed power magnitude/frequency limits in the frequency domain, and the power total signal distortion limit" [1]. The pulsed power behavior in the time domain is shown in Fig. 1. The standard specifies that "three phase pulsed real power deviation from the average real power level …be less than ±50 kW over a 1-second interval centered on the event" [1]. Fig. 1 is one example of a PPL and also shows the allowed limits of the power profile that can be drawn by user equipment connected to the ac bus point of common coupling (PCC) on a ship. The gray shaded regions show the moments in which the step change in power is too large, such that it exceeds ±50 kW from the 1-s centered rolling average.
The limits that are applied to the PPL are defined as follows. First, the load profile is measured, then at each time step, 1 2 second of the pulsed power before that time to 1 2 second after that time is averaged to create the line labeled "Centered 1-s Avg" in Fig. 1 for a moment in time. This curve is also indicated as "rolling average" in the military standard. Since 1 2 second of data after the moment being analyzed is needed to find the centered average, this cannot be done in real time without delay. If 50 kW is added/subtracted from this rolling average, it creates the "deviation limit," as defined in [1]. Since the average depends on the behavior of the pulsed load, the deviation limits will depend on the shape of the pulsed load. In Fig. 1, the pulsed load profile consists of step functions and the limits are linear. As will be shown in the simulated results, the shape of the limits is no longer linear when the pulsed load is not created by a collection of step functions.

III. SYSTEM ARCHITECTURE AND CONTROLLER
The power electronics system presented in this article, shown in Fig. 2, is intended to service PPLs connected to the dc bus while still meeting the requirements in [1] at the PCC on the ac bus. The novel portion of the controller is shown below the schematic of the dc bus and produces the q-axis current reference i q e ref .
The system includes two power converters: a bidirectional boost converter interfacing an ESS and a three-phase VSI, both connected to the dc bus where the pulsed load is located. The bidirectional boost converter controls the dc bus voltage, whereas the VSI controls the current feeding the dc bus from the ac bus. The VSI is connected to the ac bus through an LCL filter and is controlled in grid-following mode where the current is regulated.

A. DC/DC CONVERTER CONTROL
The bidirectional boost converter is constructed with two switching devices and two antiparallel diodes in the classical totem-pole configuration, as shown in Fig. 2. This dc/dc converter regulates the dc bus voltage V bus using the double PI control system shown in Fig. 3. The outer loop generates an error based on the difference between the measured dc bus voltage and the reference dc bus voltage. This error is fed to a PI controller, whose output is the reference current for the inner control loop. The inductor current, I DC , is measured, filtered, and compared with the reference current to produce the current error, which is then passed into another PI controller generating the converter duty cycle D.
A deficiency in stored energy on the dc bus will result in commanding the converter to push more energy from the ESS to the dc bus, and a surplus of energy stored on the dc bus will result in commanding the converter to reverse the power flow and charge the ESS. Overall, the controller in Fig. 3 regulates the dc bus voltage by varying the ESS energy flow.

B. VSI CONVERTER CONTROL
The active and reactive powers drawn from the ac source are realized with a controller implemented in the synchronous reference frame. The control architecture is detailed in the bottom right-hand side of Fig. 2. The three-phase measured inverter currents and source voltages are transformed using the following transformation [17]: f 0 e refer to the three-phase source voltages or inverter currents in the abc stationary frame and qd0 synchronous frame, respectively, with the subscript "e" indicating variables in the synchronous qd0 reference frame. The q-axis current controls the inverter active power while the d-axis current controls the inverter reactive power. This affects the P (real power) and Q (reactive power) drawn from the ac source. The angle θ is generated by the phase-locked loop (PLL) and is used by the VSI to synchronize its output current with the ac bus at the PCC In Fig. 2, v d e is the source voltage transformed to the synchronous reference frame. The PLL proportional and integral gains are K p and K i , respectively. The PLL drives v d e to zero so θ will be the angle of a cosine in phase with the phase A source voltage.
The synchronous frame d-axis current command for the inverter i e d ref controls the reactive power at the inverter output and is set to zero for this project; however, it could also be scheduled by a reactive power controller to be nonzero if it is desired to control the power factor at the source [18]. The synchronous frame q-axis current command for the inverter,   i e q ref , schedules the inverter active power and is controlled so that only slower transitions of the fundamental frequency of current are drawn from the ac source. This is the novel part of the proposed controller and is the key to providing the current pulses from the ESS, through the bidirectional boost converter, and smoothing the transients on the ac bus at the PCC. Neglecting the zero-axis component, the active power in the synchronous frame is [17] where P e qdref is the active power in the synchronous frame, and the minus sign is used because the power flow is positive out of the inverter. In (3), v d e is controlled to zero by the PLL, thus the active power equation can be simplified and then set equal to the filtered pulsed power where P ppl_filtered is the filtered pulsed power on the dc bus and In Fig. 2, v e qnom is the nominal source voltage on the q-axis in the synchronous frame. The filtering is done using a lowpass filter, designed with α = π rad/s (which is 1 2 Hz), which can be adjusted higher or lower to tune how quickly the source is allowed to respond. This parameter α is used in the novel energy storage sizing strategy presented in Section V. From (4), the q-axis current reference i e q ref is computed as follows: If the PPL is a resistor and it is placed onto the ac bus, then the power drawn by the proposed system will change instantly when the pulsed load turns on exceeding the dP/dt limits specified by [1]. On the other hand, if such a load is connected to the dc bus, the source will be decoupled from the instantaneous power flow change. The inverter between the dc bus and the ac bus can be programmed to support a dc PPL except for the fast transition, which is serviced by the ESS on the dc side. In this configuration, the user equipment can be designed to support the pulsed load and meet [1] at the same time. As a result of this decoupling of the pulsed load from the ac bus, the ESS can be sized only for a small portion of the active power required by the PPL transient, as shown in Fig. 5. Adjusting the low-pass filter corner frequency changes the power demand on the ESS.

IV. MODELING AND SIMULATIONS
A physics-based model to study the system depicted in Fig. 2 was developed and simulated using MATLAB and Simulink. The model was derived with an ideal ESS, an ac source, a dc/dc converter, a three-phase VSI, and resistive loads. The control system is coded in Verilog for the experimental lab demonstration. The ac source comprises an ideal threephase voltage source in series with a 0.5 mH inductance and 0.0 1 of resistance per phase to simulate the cables between the ac source and the PCC. MIL-STD-1399-300 Type I power, 440 V rms , 60 Hz was used in the model and simulations. A constant three-phase linear, balanced load is connected at the PCC. The three-phase load consists of a 12.8 /phase resistance in series with a 25.5 mH/phase inductance. The  PPL is connected to the dc bus and draws an active power profile, as represented in Fig. 1, from MIL-STD-1399-300.
The resistance values used in the simulation for each step of the pulsed load waveform are listed in Table 1.
The three-phase VSI is modeled with ideal switches, state space representation of the output filter, and multisampled space vector modulation, as described in [16]. The filter inductance is 440 μH per phase and the capacitance is 20 μF per phase. The dc bus is regulated at nominal 800 V by a bidirectional boost converter fed by an ideal ESS of 400V nominal voltage. The bidirectional boost inductance is 2 mH and the converter switching frequency is 12 kHz. Fig. 4 shows the simulated PPL waveform and the ±50 kW limit lines from the 1-s centered rolling average. This figure reproduces well the plot from [1] copied in Fig. 1, validating the simulation input PPL and rolling average algorithm as  described in the military standard [1], which are used in the simulations to follow.
The results of a 15-s simulation, created using the PPL in [1] are shown in Figs. 5 and 6. The plots in Fig. 5 demonstrate that the active power drawn from the source at the PCC is clearly within the boundaries set by [1] with the PPL as described in Table 1 and plotted in Fig. 4. Adjusting the low-pass filter frequency will move the curve further within the boundaries, if desired. Making the low-pass filter cutoff frequency α as high as possible will reduce the ESS size. The plots in Fig. 6 show separately the load power (top) and the active power drawn from the source (middle), together with the power provided by the ESS (bottom). The bottom plot in Fig. 6 demonstrates how the ESS supplies transient power, thus removing the sharp edges from the load transients on the ac bus. This waveform also indicates that the ESS can be small because it only provides power during the transients.
The simulation results presented in this section validate the functionality of the proposed control system and demonstrate that, with the pulsed load placed on the dc bus and the lowpass filter with α = π rad/s, the simulated active power at the PCC meets the requirements in MIIL-STD-1399-300 [1].

V. NOVEL ESS SIZING AND TRADEOFF ANALYSIS
Sizing the ESS is an integral part of the power conversion system design, proposed in this article. SCs can be used for the ESS and their size must be selected in tandem with the design of the low-pass filter discussed in the previous section. A novel SC sizing procedure is presented and then utilized for a tradeoff study to analyze the impact that different low-pass filter cutoff frequencies, α, have on the size, volume, and other characteristics of the ESS.

A. PROPOSED SC SIZING STRATEGY
The SC sizing algorithm, providing a deepening on the boundary conditions affecting the above design choices, is presented in Fig. 7. We start on the dc side, and we compute steps backward. Input parameters are α, V SC , and V bus along with i DC (t) from the preceding section. For each individual SC, the parameters I SC single , V SC single , and C single are chosen, and the total capacitance is computed C = n par · C single /n ser (7) where n ser is the number of SC connected in series and n par is the number of SC strings in parallel. This latter parameter is set to 2 at the beginning of the sizing procedure, while n ser depends on how many SCs in series are required to reach the nominal voltage V SC (which is n ser .V SC single < V bus ): Of course, being the scope of the procedure to provide the suitable sizing, C single is subject to change/adapt at the end of the procedure, when all the conditions are step-by-step implemented.
If the time interval of the sampling is known ( t), then the following steps are needed to assess a few additional parameters on the dc side. The proposed sizing procedure includes the following stages.
1) Identify consecutive time intervals in the PPL power profile when SC is discharging or charging, by looking at the polarity of i DC (t), with "+" used when the ESS is discharging and "−" used when the ESS is charging. 2) Compute the dc bus power P bus (t) = V bus (t)·i DC (t) and also the energy transfer in each time interval: 3) Identify the maximum P bus (t) within the 15 s PPL load cycle, to pinpoint the period when the maximum cumulative discharge energy E dis ( t j ) and maximum cumulative charge energy E ch ( t i ) occur. The duration of these time intervals is also computed by j/or i t j/or i . 4) A preliminary SC model is used with the rated parameters V single SC , I single SC , and C single . 5) We perform a preliminary analysis of a) the peak power, b) how much energy must be stored in the ESS, and c) when the most challenging conditions, affecting the SC sizing, happen (in terms of n par ). Next, we focus on what must be guaranteed on the SC side to support the dc bus. The following steps consider the SC side, on the other side of the bidirectional boost converter, for which we assume its efficiency η dc/dc to be known. 6) We, thus, need to report the output P bus (t) to the SC side, and the power at the SC-side, P SC (t), is computed as We assess the energy transfer in/out from the SC side in the same way (for both modes) in each t E SC ( t ) = E bus ( t ) η dc/dc in dis. mode. (11) To support whatever initial charging and/or discharging mode being required (and this boundary condition, of course, affects the sizing), the voltage V SC at time t = 0 is set in (15) as the voltage corresponding to the average energy computed in (14) using the maximum energy stored in the ESS E max = n ser .n par .C single V single SC 2 2 (12) and the minimum energy set as the energy when the voltage is at ½ of the full charge Once Vsc(t = 0) is known, then we can compute the amount of charge needed in the SC bank, at t = 0, and then, by knowing how much energy shall be transferred to/from the dc side (from point 2) at each time t, we can assess E SC (t), the state of charge, ∀ t. Particularly, for t = 0, we have (16) and then 8) Therefore, 9) once P SC (t) and V SC (t) are known, also i SC (t) can be calculated. 10) Next, the maximum and minimum charge for SC is evaluated; we now compute the most challenging time, energy, charge, and power values at the SC side, useful for determining the final number of parallel strings and/or the more suitable C single value (19) where P t string = n ser .P SC single , E SC (t)= E max SC (t ) − E min SC (t ) and E a SC is the usable energy from each SC. 11) The final check is on the minimum state of charge, allegedly achieved during the cycle: E SC min (t), which is computed as min(E SC (t)) and it has to be greater than the minimum state of charge on the SC side (E SC max -E SC a ); if this condition is not satisfied, then the capacitance C is increased, by operating on C single value (as usual by taking into account its tolerance and derating factors) so that a 10% margin (or whatever value is considered reasonable, with respect to the minimum threshold β) is guaranteed. When compliant C is found, then the procedure stops.

B. TRADEOFF ANALYSIS: ESS SIZE VERSUS LOW-PASS FILTER
The 15-s PPL profile from [1] was used for this study, and the SC bank was sized to guarantee that the SC charging and discharging could allow compliance with the strict rule of keeping the ac bus power profile within the upper and lower bound limits, as shown in the example of Fig. 5. Fig. 8 shows the tradeoff between having smaller α and an increased peak power to manage and, at the same time, on the same plot on the secondary y-axis, the value of nonrestored energy (NRE), whose definition is that amount which is not recovered in the SC at the end of the 15-s cycle, after all the discharging/charging transfers, and it is computed as where E dis j, SC ≥ 0, and E ch i, SC < 0, and N dis and N ch are the number of (discharging/charging) intervals occurring during the 15-s PPL cycle. The higher the peak power to deliver to the dc side, the higher the NRE. All the reported configurations show the tradeoff to be evaluated in the sizing stage.
In Fig. 9, the needed usable capacity serves as a reference to understand how much the percentage of NRE over the usable (n ser .E a SC ) is and the points belonging to the curve have different α values (thus, overall capacitance, which is reported once and for all in Fig. 8). For instance, point P (coordinates 58 Wh, 24%) represents what happens when α = 0.7 (C = 16.9 F) with respect to these two operating factors; hence, the higher the usable energy, the more the energy content of the SC is deployed. Therefore, deploying more the energy content of SC produces the need to use an external source to charge the SCs more often, and this is highlighted in Fig. 10.  On the primary y-axis, the overall volume (in liter) of each sizing solution is compared in terms of occupied space and number of 15-s cycles allowed to be performed before the SC bank recharge needs to occur. The choice, for instance, can be driven by looking at the volume needed and its constraints: according to the procedure listed in the previous section, in this particular case, the number of strings in parallel is 2 and for series is 4, to ensure the required service, nevertheless the reference value for SC (C single ) changes from 2.11 F (when α = 0.7) to 6.98 F (when α = 0.2). It is worth noticing that if one of the constrains (or substantial boundary conditions) changes, for instance, if we wanted to keep C single equal for all the configurations, then the 10% margin β would change accordingly and further considerations could be added to the analysis.
The 3-D plot in Fig. 11 reports the value of the specific power, the rate between the maximum delivered power over the overall capacitance of the SC bank (C), identified with respect to the relative point whose coordinates represent the delivered peak power according to the chosen α (for α ranging from 0.2 up to 0.7, step 0.1). Again, smaller α values help to deliver less specific active power per Farad of overall capacitance. But of course, this is achieved by using a larger ESS volume (thus, higher costs), potentially, with more strings in parallel (n par ), depending on the adopted strategy on C single and β value.
In our case, we kept V single SC , I single SC fixed, then the minimum value on C single for each α has been sought to satisfy the 10% margin β. This is possible when the specifics of the capacitor allow the ratio to be checked from Fig. 11. If not, then the chosen SC model must be changed in step 4 and adjusted/rounded, according to what the market offers.
The boundary conditions play an important role; hence, subcases can be identified: for instance, V SC (t = 0) can be chosen differently, n ser can become an additional parameter to choose, I SC can change with C single , etc. These further developments are now neglected because, according to the current assumptions, they do not apply. Nevertheless, the matter deserves to be further investigated and their role will be considered in future works.

VI. EXPERIMENTAL RESULTS
A laboratory prototype of the system architecture shown in Fig. 2 was assembled using SiC-based power converters to operate at the Type I 200 V rms voltage level, as defined in [1]. This is an entirely new prototype compared with the one used in [16], which used silicon devices. It is a scaled-down system compared with the power level addressed in MIL-STD-1399. The experimental setup is drawn in Fig. 12 with details of the resistive loads used to simulate the PPL. A photograph of the laboratory prototype is depicted in Fig. 13, and the experimental parameters are listed in Table 2. The two power converters were built using SiC Infineon development boards [19], which include 1200V SiC Trench MOSFETs [20].
The control system was implemented on two FPGA control boards: one to control the power flow from the ac bus to the    Fig. 2, and another to control the bidirectional boost converter interfacing the ESS, as shown in Fig. 3. Two Diligent ARTY-A7 FPGA development boards [21] were utilized in this laboratory setup and were programmed using some Verilog code together with some modules created from Simulink using the HDL-Coder software. A block diagram depicting the communications between the two FPGA boards, the hardware and the user interface, is shown in Fig. 14. The dc-dc converter FPGA is the focal point of this laboratory experiment because it controls the power flow through the system and is the point of user interface for system control.  In the laboratory experiment, the load is pulsed once with the resistance values shown in Table 2. The resulting power produced from the VSI is shown in Fig. 15. Initially, the VSI is commanded to provide zero power, regardless of the dc load. The rise in power at t = 2.5 s is caused by the VSI shifting from zero power to power-correcting mode. In powercorrecting mode, the VSI is controlled to supply the entirety of the dc load. The pulse from 4.5 to 6.5 s maintains the VSI in power-correcting mode while stepping the load from low to high and subsequently high to low. As a result, the system satisfies the pulsed load limits in [1] while operating at Type-1 voltage.
Since the operating power level in the laboratory testing is lower than the minimum level of 100 kW PPL defined in MIL-STD-1399-300 [1], the limit lines shown in Fig. 15 are scaled in proportion to the step load from the laboratory. To create the limit lines first, the rolling average curve is created for each power waveform by averaging the experimental power curve at each time step using 0.5 s of the pulsed power curve before that time to 0.5 s after that time. Since 0.5 s of data after the moment being analyzed is needed to find the centered average, this cannot be done in real time. The average is obtained by recording and then postprocessing the measured data. The limit lines for a scaled-up power level are added to the power curve by multiplying the power curve by 107, which makes the change in load equivalent to 150 kW and then adding the ±50 kW limits. Note that the power curve obtained from averaging is not shown in Fig. 15. Thus, for a dc pulsed load of 150 kW, the ±50 kW limit lines would appear, as shown Fig. 15.
The experimental measurements in Fig. 16 include the pulsed load current on the dc bus (bottom plot), the dc bus voltage (middle), and the bidirectional boost inductor current (top). The plots illustrate the transient response of the system to the pulsed load. Two small dips are visible on the dc bus voltage, which are within ±3% of 350 V, which is the reference dc bus voltage. This demonstrates that the bidirectional boost converter controller is working as expected. The bidirectional boost converter inductor current i DC shows how energy is drawn from the battery to smooth out the transient on the ac bus. For this experiment, the low-pass filter parameter was α = π rad/s, and the goal to meet the PPL limits in [1] was met with the minimum battery size. Larger ESS could be used with lower filter cutoff frequency to further reduce the transient on the ac distribution bus. This concept is discussed in detail in Section V.
The power plots in Fig. 17 are obtained using the experimental currents and voltages. Note how the VSI power changes slowly because the ESS takes the sharp edges of the load. This demonstrates the successful implementation of the novel dc bus controller discussed in Section III. Also, note that the negative VSI power plot indicates that power flows from the ac bus to the dc bus, because the current i inv is positive out from the VSI to the ac source, as show in Fig. 2. At the beginning of the experiment, the VSI is supplying energy to the dc bus to charge the ESS.
The ac source currents for all three phases are shown in Fig. 18 demonstrating that the source supplies current slowly, ramping up to the maximum power required by the pulsed load, thus meeting the limits in [1].  All the measured data were processed through a lowpass filter with a corner frequency of 50 Hz to extract the low-frequency dynamics of the system and reject the highfrequency components due to the switching of the power electronics. This particularly applies to the boost inductor current.

VII. CONCLUSION
This article presents a novel control system, where the choice on α is integrated into the best fit ESS sizing method to meet the PPL limits in MIL-STD-1399 Section 300, Part 1 [1]. The solution includes connecting the PPL to the dc bus regulated by an ESS power converter and using a three-phase VSI to control the ac source power to meet the prescribed limits. The synchronous reference frame active and reactive power control and a novel strategy to control the transient on the ac bus are presented. A physics-based model was implemented in MATLAB/Simulink to demonstrate that the active power, supplied by the ac source power, is indeed controlled to fit within the given limits. In addition, the α-parameter has inspired a novel sizing method that selects the minimum number of SC and the capacitance single value to comply with those limits, starting from i DC (t) values and from the analysis of the features of the charging/discharging intervals. To the best of authors' knowledge, this is the first time that a similar procedure is proposed and formulated, comprehensively.
A scaled-down laboratory prototype was built with a SiC bidirectional boost converter to regulate the dc bus and a SiC three-phase grid-following VSI to interface with the ac bus. The controllers were implemented on two FPGA development boards communicating with each other and with the user interface through a virtual I/O. The experimental measurements on the laboratory setup with Type I 200 V rms voltage successfully validate the simulations and demonstrate that the proposed system meets the PPL limits of the standard [1].