Simplified analytical model for estimation of switching loss of cascode GaN HEMTs in totem-pole PFC converters

A practical analytical model to calculate the switching loss of cascode gallium nitride high electron mobility transistors (GaN HEMTs) is proposed. To facilitate analysis and application, the transmission delays introduced by Si MOSFET and interconnection inductances are ignored in modeling. Meanwhile, the nonlinear junction capacitances of the device and circuit stray inductances are also incorporated to increase the accuracy of the model. The turn-on and turn-off switching processes are described in detail and the simplified equations can be easily solved by using mathematical tools. Based on the analytical model, loss evaluation of totem-pole PFC converter is introduced briefly. Finally, the accuracy of the model is validated by comparing the calculated loss and converter's efficiency with experiment results. Peak efficiency of 99.26% is achieved for a 3.6 kW single phase CCM Totem-Pole PFC AC/DC converter switching at 50 kHz based on 650 V cascode GaN HEMTs.


Introduction1
Wide bandgap power semiconductor devices, especially GaN HEMTs, are showing superior material properties. Compared with traditional silicon-based devices, the higher electric breakdown field, higher electron mobility, and larger energy gap of GaN enable them to be applied in higher switching frequency, with less switching loss, and lower on-resistance. In recent years, a large number of GaN devices have been manufactured and used in a variety of applications. The employment of GaN devices will significantly expedite the improvements in power converters performances [1][2][3][4][5] .
To estimate the converter total power loss and improve the conversion efficiency under hardswitching conditions, several circuit simulation models have been proposed in Refs. [6][7]. Unfortunately, building these simulation models is quite time-consuming, and the simulation results are not always directly applicable to converter design. Compared with simulation models, analytical modeling is a useful approach to achieving a design with optimal performance. Analytical switching loss models use several mathematical equations to describe each mode during turn-on and turn-off. Piecewise linear method and equivalent circuit are often used to simplify the calculation process.
The most popular analytical switching loss models are the piecewise linear model presented in Refs. [8][9]. Typically, the model can roughly describe the switching process and estimates the switching loss due to its simplicity and good performance, so it is referred to as the conventional model. However, the main drawback is that it neglects the parasitic inductances and the nonlinearity of the junction capacitances, for which the estimation of switching loss is nearly in the same magnitude as the experimental result. More comprehensive analytical switching loss models that include such parasitical parameters are presented in Refs. [10][11][12]. The nonlinear junction capacitances and the parasitic inductance are taken into consideration, especially the common source inductance is included. These analytical switching loss models are applied to the high-frequency low-voltage buck converter and the results match the experiment results very well.
However, all of these analytical switching loss models are devised to estimate the power loss of Si MOSFET. Limited by manufacturing technique, most of the GaN devices available today are lateral heterojunction field-effect transistors (HFETs) on a commercial level, also known as HEMTs. A layer of high-mobility electrons called "two-dimensional electron gas" (2DEG) that benefits from the unique structure forms a native channel between the source and drain of the device. Because of the native 2DEG channel, the fundamental GaN HEMTs are inherently depletion-mode devices. Several methods have been used to fabricate enhancement-mode GaN HEMTs [13][14][15] , and analytical circuit models of E-mode devices that combine the circuit parameters are developed [16][17][18] .
A normally-off GaN device can also be fabricated by cascode structure, requiring packaging of the high-voltage depletion-mode GaN HEMT with a low-voltage enhancement-mode Si MOSFET [19][20][21] . To understand the static and dynamic behavior of cascode GaN HEMTs static and dynamic behavior, an analytical loss model of high voltage GaN HEMT in cascode configuration has been proposed in Ref. [22]. The novel analytical model considers the package and PCB parasitic inductances, as well as the nonlinearity of the junction capacitors and the transconductance of the cascode GaN HEMTs. Even the package bonding and terminal lead parasitic inductors are all taken into considerations, which is shown in Fig. 1. The model is easy to understand and provides a deep insight into the switching process. But the model is too complicated as it needs a special proprietary tool for parameter extraction in the package, which is very difficult to perform for many researchers and engineers. In this paper, a simplified analytical loss model is used to calculate the switching losses of the cascode GaN HEMTs. In order to guarantee the superior precision of the cascode GaN HEMTs, all parasitic inductors and capacitors are taken into account except for the parameters in the package. It should be noted that the model requires only data available in the datasheet provided by manufacturers. The basis of the model is given in Section 2. The transition process is analyzed in Section 3. Section 4 presents the simulation and experimental validation of the model. Eventually, Section 5 is devoted to drawing conclusions.

Basis of the model
A totem-pole PFC converter based on cascade GaN HEMTs is illustrated in Fig. 2. Two kinds of stray inductances are taken into account in a totem-pole PFC converter, including the device terminal lead and printed circuit board (PCB) traces parasitic inductances. It is reasonable to neglect the package interconnection inductances, because the bonding inductances are small enough based on the current packaging technology and it is hard to extract for the vast majority of designers. Fig. 3 shows the equivalent circuit of the totem-pole PFC converter for cascode GaN HEMTs with consideration of the parasitic inductances and capacitances. L D , L G , and L S represent the sum of the terminal lead and PCB traces loop parasitic inductances. Particularly the L S is called the common source inductance, which is inductance that is common to the power and driver loop. These parameters can be easily obtained through measurement or simulation results.
can be obtained from the drain-source current IDS versus the gate-source voltage V gs curve as shown in Fig. 4a. Coefficients a 1 , a 2 and a 3 can be extracted directly from the slope of the piecewise linear fitting curve. The behavior of cascode GaN HEMTs as a current source controlled by the gate voltage is described by (2) The expressions of the junction capacitance can be also obtained by the same method as above, including C ISS , C RSS and C OSS data available in device datasheets in Fig. 4b where coefficients b 1 , b 2 , b 3 and V 1 , V 2 , V 3 can be respectively obtained from the slope and the intercept of the piecewise linear fitting curve.
According to the test method of the device, C gs , C gd and C ds can be given by It is noteworthy that nonlinear parameter models complicate mathematic calculation. So the transistor parameters are calculated off-line and look-up table method is used to reduce the computation complexity.

Analysis of hard-switching transients
The modeling approach of cascode GaN HEMTs is based on the silicon-based MOSFETs analytical loss models proposed in Refs. [7][8][9]. Moreover both the transconductance and the nonlinearity of junction capacitance are considered, and the bottom switch reverse recovery process is analyzed in detail. The turn-on transient process could be divided into four stages as follow: 1) delay period, 2) drain-source current rising and bottom switch reverse recovery, 3) drain-source voltage falling, 4) ringing stages. And the turn-off transient process could be divided into three stages: 1) delay period, 2) drain-source current decreasing and voltage rising, 3) remaining charging, a detailed analysis of this circuit describes in the following sections as follow.

Turn-on transition
The Equivalent circuits for hard-switching turn-on transition are shown in Fig. 5. Before the cascode GaN HEMTs turn on, the dc-link voltage V dc is applied to the cascode GaN HEMTs, and the inductor current I l flows through freewheeling diode D b . The initial conditions of cascode GaN HEMTs for the electrical variable before turn-on transition are (1) Stage I: Delay period. After the gate voltage V g is applied, the gate current charges the transistor input capacitors C gs and C gd . The transistor drain current is zero and the drain-source voltage is equal to the dc-link voltage. From the circuit in Fig. 5 Stage I, the following equations are obtained The current i g can be obtained from equations (6)- (8), and this current is used to calculate the initial current for the following stage. As the channel is not activated, there is no power loss during this period except the loss of the gate driver. The delay period is the time required for V gs to reach V th from 0 V.
(2) Stage II: Drain-source current rising. The transistor channel starts conducting and will be directly controlled by the gate voltage V gs . The junction capacitors C gd and C ds are discharged slowly by channel current. It should be note that the drain-source voltage V ds decreases in this stage because of the voltage drop across L s and L d induced by channel current rising as shown in the following equation  The drain-source current consists of two parts: the channel current and the junctions capacitors discharge current. When i Ld reaches the inductor current I l , this period ends and the bottom switch reverse recovery period begins.
(3) Stage III: Reverse recovery current spike and drain-source voltage falling.
Since the bottom cascode structure switch contains a low-voltage Si MOSFET, the reverse recovery losses are inevitable. In this period, the bottom switch is unable to go from freewheeling mode to reverse blocking state rapidly until a large amount of charge has been removed. The top cascode GaN HEMTs current i Ld rises to the maximum with the charge of reverse recovery current, so the top switch current spikes goes high with the same magnitude of the bottom switch.
There're some assumptions before analyses of the bottom switch reverse recovery loss: 1) the total reverse recovery current I rrm is positively correlated with the initial current I l which flows through the bottom switch; 2) the reverse recovery current rising slope magnitude ∆i Ld / ∆t is equal to the initial rise rate of the top switch. Consequently, the simplified reverse recovery process is shown in Fig. 6 When the reverse blocking ends, a part of the current i Ld provides the inductor current I l , and the others charge the junctions capacitors of the bottom switch. This subperiod ends until the current that flows through the top switch decreases to I l . The equivalent circuit is shown in Fig. 5 Stage III, and key equations are given by (4) Stage IV: Ringing period. The ending sign of Stage III is that i Ld = I l , with no restrictions on the value of V ds . In other words, there are two cases for V ds at the end of Stage III in fact. The first case is that the top switch drain-source voltage decreases to 0 V before the i Ld decreases to I l . The other case is that the top switch drain-source voltage does not decrease to 0 V before the i Ld decreases to I l . The equations in this stage are as same as the second subperiod of Stage III. During this stage, the top switch is fully turned on until the following conditions are satisfied

Turn-off transition
The turns-off behavior is similar to the turn-on transition as shown in Fig. 7 but no reverse recovery losses in Stage III. Before the cascode GaN HEMTs turn off, the gate voltage is equal to V g , and the inductor current I l flows through cascode GaN HEMTs. There are three stages during turn-off transition in total, and a brief analysis as follows. After the gate pulse voltage transition from V g to 0 V, the junction capacitor C gs and C gd begin to discharge. In this stage, the gate voltage is given by The delay period ends when the equation below is satisfied   l m gs th (2) Stage II: Drain-source current decreasing and voltage rising.
When the channel saturation current is less than the inductor current I l , the bottom switch junction capacitor is discharged by the rest of the I l . The equivalent circuit is shown in Fig. 7 This period ends when the top switch channel current reaches 0 A.

Model implementation
The efficient numerical algorithm that includes switching losses, conduction losses, and passive component losses. The lead inductances and loop inductances could be extracted by measurement or finite element analysis. To ensure the accuracy of the results, the model takes junction capacitances and transconductance into account. Moreover, the nonlinearities of the parameters are modeled by piecewise fitting curves provided by the device datasheets and updated after every step.
Specifically, after deriving the state equations corresponding to all stages, the "ode45" differential equation solver was used in MATLAB to get the expression of V ds (t) and i ch (t) for each subperiod. The final values of one subperiod are treated as the initial conditions for the next subperiod and the duration of each mode can be obtained with the given initial conditions. Because of the sinusoidal inductor current, the transition equations are derived from the simplified equivalent circuits and the total switching losses are calculated using the incremental method of the cycle-by-cycle accumulation in half line period. As shown in Fig. 8, the losses are accumulated for 500 iterations. That is because under the grid frequency of 50 Hz and the switching frequency of 50 kHz, there are exactly 500 iterations within half line period. The remaining power losses, including inductor losses and device conduction losses, are also calculated according to the inductor current.

Simulation and experimental results
In this section, the simulation and experimental results are presented to verify the simplified loss model for cascode GaN HEMTs in totem-pole PFC converter.

Measurement setup
The test converter consists of a symmetric cascode GaN half-bridge with an isolated gate driver, and the photograph is shown in Fig. 9. The bonding stray inductors and the parasitic capacitors inside the package both are neglected to simplify the switching loss calculation, which makes the model more concise and practical. In order to verify the accuracy of loss estimation, A 3.6 kW totem-pole PFC experimental prototype is built using TPH3207WS in a TO-247 package. The converter is running at a switching frequency of 50 kHz with an 800 μH @0A PFC inductor, whose specifications and parameters are listed in Tab. 1.
2.5 GHz oscilloscope (MDO3024) from Tektronix is used for measurement. The line frequency AC voltage is measured with a high voltage differential probe (Tektronix P5200A), and the drain-source voltage is measured directly at the corresponding transistor pin with a high voltage probe (Tektronix P5120). The line frequency and drain-source current is measured using a AC/DC current probe (Agilent N2782A) with 50 MHz bandwidth and 50 A peak current measurement capability.

Simulation and experimental results
The test converter operate with a 230 V rms input voltage and a 3 600 W output power. Fig. 10 shows the key waveforms measured during the full load operation at high line input. Important intermediate quantities for analytical loss estimation are computed for switching loss. The operating conditions are V s = 230 V rms , V dc = 400 V and P out = 3 600 W, and the simulation and experimental waveforms match closely in turn on/off speed, current spike and voltage slope as shown in Fig. 11 and Fig. 12. As plotted in Fig. 11, there exist significant distinctions between the measured and simulated current ringing after the transistor is fully turned on. Since the transistor voltage is already equal to zero, there is no additional loss. The time delay between gate voltage and drainsource voltage in the experimental waveforms is also remarkable. The cascode GaN device is fabricated by packaging the high-voltage depletion-mode GaN HEMT with a low-voltage enhancement-mode silicon MOSFET. The cascode device is indirectly controlled by the low voltage MOSFET. Compared with the enhancement-mode GaN HEMTs, the cascode devices have a larger delay from applying the gate voltage to the operation of the high-voltage transistor in nature.
Furthermore, based on the operation principle of the converter, the switching loss calculation requires at least half line cycle accumulation. Meanwhile, the effects of inductor current sinusoidal changes and current ripple that contribute to switching losses are taken into consideration. The estimated totem-pole PFC converter loss is calculated and compared to the experimentally measured loss in Fig. 13, which proves that it is feasible to approximate the switching loss according to the device datasheets. The trend followed by experimental data is clearly reproduced by the model. Peak efficiency of 99.26% is achieved for a 3.6 kW single phase CCM Totem-Pole PFC AC/DC converter switching at 50 kHz based on 650 V cascode GaN HEMTs. Fig. 14 shows the detailed breakdown of losses provided by the proposed method based on the totem-pole PFC converter prototype. The contribution of switching losses to the total losses is above 16% at full load condition. It can be seen that the proportion of the conduction loss is increasing rapidly than the switching loss.

Conclusions
This study presents a simplified switching loss model of cascode GaN HEMTs, which only requires parameters provided by device datasheets. The hard switching process analysis considering the impact of the stray inductances and the nonlinear junction capacitance is illustrated in detail and the implementation method is introduced based Totem-pole PFC converter. In comparison with the established cascode structure analytical models, this paper showed how those models must be redefined in order to simplify calculation process. It is shown that the estimation of losses for hard-switching converters can be achieved with the consideration of the non-ideal parameters. Finally, experiment results validate the correctness of the model in a 3.6 kW single phase CCM Totem-pole PFC converter with peak efficiency of 99.26%.