L${}_{\text{2}}$min${}^{\text{2/2s}}$: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs

While it becomes more challenging to improve the energy efficiency of incremental delta-sigma data converters (IDCs) from the analog circuit design perspective, we propose two novel linear reconstruction filters for IDCs to enhance their performance in a digital way, including the L<inline-formula><tex-math notation="LaTeX">${}_{\mathbf{2}}$</tex-math></inline-formula>min<inline-formula><tex-math notation="LaTeX">${}^{\mathbf{2}}$</tex-math></inline-formula> filter and its symmetric version, the L<inline-formula><tex-math notation="LaTeX">${}_{\mathbf{2}}$</tex-math></inline-formula>min<inline-formula><tex-math notation="LaTeX">${}^{\mathbf{2s}}$</tex-math></inline-formula> filter. Compared to the classical linear reconstruction filters, such as the cascade-of-integrators (CoI) and cascaded integrator-comb (CIC) filter (an implementation of <italic>sinc</italic> filter), the proposed filters can achieve efficient quantization and thermal noise suppression, with the lowest thermal noise penalty factor of 1.2 among the high-order linear reconstruction filters. In this paper, we present analytical, numerical, and experimental results to demonstrate the superior performance of the filters for first-order and second-order IDC output reconstruction. The proposed filters are hardware-friendly and example digital implementations in a standard complementary metal-oxide-semiconductor (CMOS) and field-programmable gate array (FPGA) platforms are included in this paper.


I. INTRODUCTION
E MPOWERING various industries, such as telecommuni- cation, healthcare, automotive, etc., analog-to-digital converters (ADCs) have played a crucial role in bridging the gap between the physical world and the digital realm [1], enabling the processing, storage, and manipulation of real-world data digitally.Recent advances, such as sensor fusion, have raised high demands for data and, consequently, high-performance ADCs.In pursuit of this goal, various new quantization schemes have been reported.The recent pioneers in this field include unlimited sampling [2], [3] and one-bit quantization [3], [4], [5], [6], [7], [8], [9], which utilize advanced signal processing theories and powerful signal processing tools for signal Bo Wang and Jens Schneider are with the College of Science and Engineering, Hamad Bin Khalifa University, Doha 34110, Qatar (e-mail: bwang@hbku.edu.qa).
Man-Kay Law is with the State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics and FST-ECE, University of Macau, Macau 999078, China.
recovery.However, substantial computational resources are required (e.g., 0.3 ms computation time in a typical CPU [9]).Among the classical quantization schemes, delta-sigma (ΔΣ) ADC also relies on signal processing to reconstruct the input using the quantized one-bit or multi-bit output [1], [10].However, its signal reconstruction process is more hardware-friendly to be integrated into standalone ADC chips.Meanwhile, compared to the emerging one-bit quantization scheme using time-varying thresholds drawn from a predefined distribution [3], [4], [5], [6], [7], [8], [9], the loop filter in a ΔΣ ADC can effectively generate uniform distancing time-varying thresholds, which recursively makes the threshold closer to the input signal, thus accurate signal recovery becomes possible using simple digital processing.
One ΔΣ ADC variant is called incremental ΔΣ ADC (IDC), which is popular for applications requiring sample-to-sample conversion, i.e., Nyquist-rate conversion [11].As shown in Fig. 1, a typical IDC consists of a ΔΣ modulator, a reconstruction filter, and a decimation operation [12], [13].Its working principle is similar to the conventional free-running ΔΣ ADC.The main difference is the extra modulator and reconstruction filter reset operation after every OSR cycle (i.e., oversampling ratio) to eliminate any memory effect.This unique feature allows IDC to perform sample-to-sample conversion, akin to a Nyquist-rate converter, while also benefiting from the oversampling and quantization noise-shaping capabilities of a freerunning ΔΣ ADC [1].
To improve the IDC performance, such as achieving higher resolution with lower energy consumption, prior research has primarily focused on optimizing the ΔΣ modulator.This includes utilizing new analog integrator topologies to reduce system power [14], employing multi-step conversion for greater quantization noise suppression [15], [16], [17], utilizing timedomain quantizers to leverage the process scaling benefits [18], etc.However, the reconstruction filter has not received the same level of attention.This is why statements such as "a one-bit first-order modulator requires 2 k samples to achieve k-bit resolution" occasionally appear in the literature, which is false if a digital filter other than a simple counter is used to process the modulator output [11].For instance, for a one-bit first-order modulator in Fig. 2, achieving 10-bit resolution would require 1024 samples if a counter is used for input reconstruction.However, by adopting an optimal reconstruction filter [19], only 98 samples are needed to achieve the same mean squared error (MSE) equivalent to 10-bit resolution [12].Therefore, designing effective reconstruction filters is an alternative way to improve IDC performance deserves more research focus.

A. Prior Art of IDC Reconstruction Filter
There are two categories of IDC reconstruction filters: linear ones and nonlinear algorithmic ones.When evaluating these filters, three metrics are primarily considered: quantization noise suppression, random noise suppression, and hardware complexity.Below is a brief overview of the existing reconstruction filters with their performance discussed based on these evaluation metrics.
The first class comprises linear ones, such as the widely used cascade-of-integrators (CoI) filter and sinc filter operating in transient mode [20], i.e., with periodic reset.Although these filters have appealing implementation simplicity, they cannot fully utilize the information encoded in the ΔΣ modulator output.As a result, compared to an ideal filter, they suffer from signal-toquantization-noise ratio (SQNR) losses ranging from a few to a few tens of decibels after reconstruction [12].A recently modified CoI filter [21] performs slightly better by incorporating a lossy digital integrator stage.However, its on-chip implementation is costly due to the requirement of fixed-point multiplication operations.Increasing the order of CoI or sinc filter can enhance quantization noise suppression but leads to a degradation in their ability to suppress random noise, such as thermal noise [11].Therefore, it becomes challenging for CoI and sinc filter to achieve effective quantization and thermal noise suppression simultaneously.Steensgard et al. [22] derive an SNR-optimized IDC reconstruction filter, which ended up with irregular filter weights, making it challenging to implement on-chip.
The second class comprises nonlinear algorithmic ones, such as the optimal filter [19], surrogate constraint algorithm [23], dynamic rational cycle decoding [24], direction projection algorithm [25], recursive filter [26], block-based decoder [27], etc.Although good quantization noise suppression can be achieved, they are all algorithmic without straightforward hardware implementations.Additionally, their high memory and computational overhead render them unpopular in actual IDC design, which prefers employing simple digital logic to build the output filter on-chip [28].Furthermore, these algorithmic filters' random noise suppression capabilities are still questionable.For instance, Kavusi et al.'s optimal filter [19] cannot process modulator output with random noise present.Server-side signal reconstruction approaches, such as phase retrieval [5], covariance recovery [6], etc., can also be potentially applied to IDCs.This paper mainly focuses on linear reconstruction filters that can be implemented on standalone ADC chips, and a full review of the literature on server-side signal reconstruction is out of the scope of this work.Instead, we would like to refer the readers to, e.g., [2], [6] and the references therein for their operation principles.

B. Technical Contributions and Results Overview
This paper proposes two novel linear digital filters for IDC output reconstruction.Compared to the prior arts, the proposed filters can achieve efficient quantization and thermal noise suppression simultaneously and are hardware-friendly to be implemented in ADC chips.Specifically, 1. theory-wise, we optimized an L 2 -norm function to minimize the output reconstruction error of a first-order IDC, resulting in a new filter kernel L 2 min 2 .Besides its high quantization noise suppression capability, its thermal noise penalty factor is only 1.2 (see Section III-C), the lowest among all existing high-order ( 2) linear filters.
In this paper, we further utilize this filter kernel to build a symmetric filter L 2 min 2s that can achieve periodic noise suppression (e.g., power line noise).The analysis and numerical results show that our proposed filters can perform better than the popular CoI and sinc filters, especially for thermal-noise-limited first-order and second-order IDC output reconstruction.For instance, to achieve the same thermal noise level, using the proposed filter can reduce the IDC energy consumption by 11%, 28%, and 33% compared to that of using a CoI 2 /sinc 2 , sinc 3 , and CoI 3 filter, respectively.All numerical simulation and implementation scripts of our proposed filters are open-source1 ; 2. hardware-wise, we present a full-custom digital design to implement the proposed filter kernels, with bittruncation applied to minimize their digital overhead.We also present synthesis implementations for FPGA and ASIC targets.The performance of the proposed reconstruction filter is also experimentally verified using the output of a second-order IDC silicon chip prototype [29].

C. Organization and Notations
Section II revisits the generic first-order IDC operation.We then present the derivation, analysis, and verification of the proposed L 2 min 2 filter and its symmetric version, the L 2 min 2s filter, in Section III and IV, respectively.This is followed by an example design using the proposed filters in Section V. Their digital implementations are detailed in Section VI, with a performance summary in Section VII and a conclusion in Section VIII.
Notation: Throughout this paper, we use n to denote the discrete sample timestep at a sampling frequency of f s ; N is the total number of samples used in one conversion (i.e., OSR).d [n] is the quantized modulator digital output at timestep n, with a quantization error ε [n].σ ε denotes the standard deviation of {ε [n], n = 1, . . ., N}, and σ q is the ADC quantization noise.
w n is the filter weight of d[n] when used to produce a reconstructed input v in , with the true input v in .The peak-to-peak resolution of the ADC is denoted as k or k-bit, with U max representing the ADC's maximum stable input range.l is the number of quantization levels of the modulator.L represents the order of a sinc L filter with D denoting its decimation ratio.(2M − 1) denotes the kernel length of an L 2 min 2s filter.In numerical computations, • is the ceiling function.

II. THE BASIC OPERATION OF IDC
In this section, we lay the basis for deriving our proposed filter by reviewing the time-domain operation of a first-order incremental ΔΣ modulator.Note that time-domain instead of frequency-domain analysis is usually preferred for IDCs [11].Fig. 2 shows a generic bipolar modulator using a one-bit quantizer.Assuming the input v in ∈ [−1, 1] is constant within one conversion [13], with the comparison threshold of its quantizer being 0 and the output d[n] ∈ {−1, 1}.The integrator is reset at the beginning of each conversion (i.e., u 1 [0] = 0).Particularly, d[0] = 0 is used to avoid the feedback operation during the first integration cycle [30].For a discrete-time integrator (the conclusion of this paper also holds for continuous-time ones), its output u 1 [n] at the n th clock cycle is After simplifying this recursive relationship, where s n is the running sum of Because the quantizer compares u 1 [n] with 0, the digital output of the modulator is The encoded output d[n] for any v in can be derived following (2) and (3).For example, with v in = 0.437, Fig. 3(a) shows the relative values of n • v in and s n at different cycles.As depicted in Fig. 3(b), the sequence s n+1 (not s n due to a delay) forms an envelope to closely track the input ramp n • v in [12].The tracking error ε A digital reconstruction filter then estimates the input by computing the inner (dot) product between the modulator output d[n] and the filter's fixed-width weighting function w n , that is As the ΔΣ modulator is nonlinear, its quantization error varies with the input.A filter that can minimize both the peak quantization error and the overall MSE (i.e., average accuracy [31]) across the whole input  range is often preferred.Currently, the most popular filters for IDC output reconstruction are CoI and sinc filters.

A. Filter Kernel Derivation
As described above, mathematically, the discrete outputs (n, s n+1 ) track the input ramp (n, nv in ) during modulation.If (n, s n+1 ) are known (i.e., reproduced using the modulator output), we can estimate the input v in by minimizing the MSE between the tracking envelope and the input ramp.We thus use linear least squares regression to minimize the cost function with respect to v in .ξ is a convex quadratic function, and its minimum can be obtained by Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
From this, we obtain the following input estimation v in after substituting s n+1 and d[0] = 0 to (5).
To derive the co-factor/weight w n for each modulator output bit d[n], we regroup the numerator of ( 6), by observing that From ( 6) and (7), Therefore, the weight w n of the n th digital bit d[n] used for input reconstruction is The complete reconstruction filter, given by the normalized weighting function w n / w n , has a concavely smoothdecaying shape.We call this filter L 2 min2 because it is derived by minimizing an L 2 -norm, and its weights have a second-order dependency on the bit index n.Fig. 4 shows the normalized weighting function, together with the CoI filters consisting of one and two integrators (i.e., CoI 1 , CoI 2 ) for comparison.Higher-order IDCs can be analyzed in the same fashion to obtain their L 2 -optimal filters.For a given modulator, we derive the time-domain expression of its quantizer input, which can be used to formulate the cost function similar to (4) to obtain the corresponding filter weights.The filter weight of high-order IDC will have a high-order dependency on the bit index.For example, the L 2 -optimal filter of a generic second-order modulator is which is costly to be implemented in digital circuits.Therefore, in this paper, we just focus on analyzing the performance of the L 2 min 2 filter expressed in (9).Meanwhile, only the generic modulator topologies are presented for conciseness, but the proposed filters are applicable to other modulator topologies/variants such as the cascade of integrators with feed-forward (CIFF) architecture, modulator with finite impulse response (FIR) feedback, modulator with signal scaling, etc.

B. Quantization Noise Suppression Capability of L 2 min 2
To start, we apply the derived L 2 min 2 filter to process the output of a first-order one-bit incremental modulator shown in Fig. 2. For analysis purposes only, assuming infinite operation like a typical ΔΣ modulator [11], its output satisfies where ε(z) is the z-domain quantization error of the onebit quantizer within the ΔΣ-loop.Assuming a constant v in within one conversion (varying inputs discussed later), the timedomain form of ( 10) is By applying the derived L 2 min 2 filter weights, the reconstructed digital output is which contains the input and a linear sum of the quantization errors ε . ., N} is independent, zero mean, and uniformly distributed between ±1 during one conversion [11], its variance is σ 2 ε = 4/12.Therefore, the standard deviation of the quantization error in D o is Considering only quantization noise, to achieve k-bit p-p (peakto-peak) resolution within the stable input range ±U max , the required conversion cycle N using the L 2 min 2 filter can be derived with the 3-sigma rule 2 such that Fig. 5. Quantization error q of different constant v in after being reconstructed by L 2 min 2 (one-bit first-order modulator, N = 1024, q normalized to 10-bit lsb with Umax = 2/3, integrator gain set to 0.75).
From ( 14) and ( 15), Therefore, for IDCs with a target resolution k > 4, using L 2 min 2 requires much fewer clock cycles compared to using a digital counter for output reconstruction, i.e., 2 k /U max cycles, indicating its strong quantization noise suppression capability.Due to the inherent non-uniform code length of a first-order modulator [30], it has several dead zone regions with large quantization error peaks limiting the absolute conversion precision.These error spikes cannot be mitigated using a multilevel quantizer or an ideal reconstruction filter [19].Injecting a random dither signal (e.g., uniform dither, Gaussian dither) before the quantizer can address this issue [11], [32].Dithering can also make ε close to a uniform distribution for DC or slowly time-varying inputs, thus keeping the above-made assumption about ε valid.If a uniform dither signal U [−1/3, 1/3] is added to the quantizer, σ 2 ε increases to (4 + 2/3) /12 and the allowed input range U max reduces to about 2/3 to avoid quantizer overloading.To achieve k-bit p-p resolution, ( 16) is modified to As shown in Fig. 5, the quantization error peaks are successfully mitigated by dithering.The analytical derivation (17) agrees well with the numerical simulation, e.g., 12.6-bit peak-to-peak resolution log 2 [U max /(3 • σ q )] is achieved with N = 1024 and U max = 2/3.The achievable k and crest-factor corrected SQNR at different OSR are shown in Fig. 6, together with that of using CoI 1 and CoI 2 as a performance benchmark 3 .
Without loss of generality, L 2 min 2 is applicable for varying inputs.With an OSR of 1024 as an example, Fig. 7 presents the simulated output power spectral density (PSD) of a −3.5 dBFS (i.e., v in = 2/3) sinusoidal input after reconstruction by L 2 min 2 , and the SQNR as a function of the sine-wave amplitude for a generic first-order incremental ΔΣ modulator with uniform dithering.The achieved ∼83 dB peak SQNR agrees with our analytical estimation of 20 • log 10 v in / √ 2/σ q , with σ q expressed in ( 14).
3 consider CoI filter with the same and higher-by-one order of the modulator.

C. Thermal Noise Suppression Capability of L 2 min 2
In a practical ΔΣ modulator, an unbiased noise component would effectively add to the input, such as the thermal noise with a variance of σ 2 g .A moving averaging filter can effectively suppress the noise to σ 2 g /N after averaging N samples.Any other filter with non-uniform filter weights cannot achieve this level of noise suppression [12].Usually, the term thermal noise penalty factor β t is used to represent the increased noise compared to that of using a simple moving average filter, whose β t is one [22].For a linear filter with weighting function {w n } N n=1 , its β t is expressed as Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
The corresponding β t for the classical linear filters are wellknown.For L 2 min 2 , it can be calculated via Therefore, the equivalent input-referred noise (IRN) of an IDC after being filtered by L 2 min 2 is which is lower than that of using a CoI 2 (i.e., β t = 1.33).In other words, without any circuit or system modifications, to achieve the same output thermal noise level, using L 2 min 2 can directly reduce 11% of IDC energy consumption compared to that of using a CoI 2 .This is the second advantage of L 2 min 2 besides its good quantization noise suppression capability, especially when applied to thermal-noise-limited converters.
To summarize, for first-order IDC output reconstruction, L 2 min 2 outperforms both in quantization and/or thermal noise suppression compared to the popular CoI 1 and CoI 2 filters.For second-order IDC (listed in Appendix B, Table II), L 2 min 2 achieves a comparable quantization noise suppression as that of CoI 2 and CoI 3 but excels for its lower β t .
IV. PROPOSED L 2 MIN 2s RECONSTRUCTION FILTER Despite the advantages of L 2 min 2 , it has the shortcoming of being unable to reject periodic noise (e.g., line frequency disturbance) due to its asymmetric weighting function.The existing popular IDC reconstruction filter with periodic noise rejection capability is the moving average filter, which is also called sinc L filter with L representing the order [33].In the following, we present a new filter L 2 min 2s with efficient quantization noise, thermal noise, and periodic noise suppression.

A. Symmetric Filter Kernel of L 2 min 2s
Based on the L 2 min 2 kernel discussed in Section III, we now develop a filter L 2 min 2s with a symmetric impulse response.To construct such a new kernel with 2M − 1 points (i.e., an odd number and now the IDC's OSR is 2M − 1), w n in ( 9) is firstly left-shifted by 1-point, mirrored around the y-axis, and then right-shifted by M -points, with the analytical form of the symmetric filter expressed as where w n = 0 for n 2M .The normalized weighing function of L 2 min 2s is shown in Fig. 8, together with the first-order (same as CoI 1 ), second-order, and third-order sinc filters for direct comparison.The thermal noise penalty β t of L 2 min 2s is still 1.2, which is smaller than that of the sinc 2 (i.e., 1.33) and sinc 3 (i.e., 1.67).This is the first advantage of L 2 min 2s .Fig. 8. Normalized weighting function of the first, second, third-order sinc filter and the L 2 min 2s filter (a length of 49-point as an example, A 2 is a 25-

B. Frequency Response of L 2 min 2s
One of the most important features of a symmetric filter is the number and locations of its frequency notches.For the wellknown sinc L filter, its z-domain transfer function is where D is the filter decimation ratio.It provides frequency notches at the integer multiples of f s /D, i.e., jf s /D with j ∈ {1, 2, . . ., D − 1} and f s is the bitstream data rate.The required bitstream length is D • L − (L − 1) to produce a valid reconstructed output [34].Therefore, for a given f s and D to place the first notch f s /D at the desired frequency, e.g., 50 Hz or 60 Hz, the IDC conversion speed becomes slower when a higher-order sinc filter is adopted.This tradeoff between frequency notch location, stopband attenuation, and conversion speed is a major drawback of sinc filters.For the proposed L 2 min 2s filter described by (21), its z-domain transfer function is As detailed in Appendix A, it creates (2M − 2) frequency notches between 0 and f s , with its first notch frequency at about 3/(4M ) • f s .Fig. 9 shows its frequency response, together with that of the sinc 1,2,3 filters for comparison.L 2 min 2s has a moderate roll-off at 40 dB/decade, and its number of frequency notches is 2 and 3 times that of the sinc 2 and sinc 3 filter with the same kernel length, respectively.This is the second advantage of L 2 min 2s .

C. Quantization Noise Suppression Capability of L 2 min 2s
L 2 min 2s can be applied to reconstruct first-order IDC outputs, and its quantization noise suppression capability outperforms that of the sinc 1 and sinc 2 filters (listed in Appendix B, Table II).Here we focus on analyzing its performance when applied to the popular second-order IDC with a pure differential noise transfer function [11], as shown in Fig. 10.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Following a similar analysis presented in Section III-B, the second-order IDC output satisfies Assuming a constant v in , the time-domain form of ( 24) is By applying the L 2 min 2s filter weights, the reconstructed digital output is n=1 is independent, uniformly distributed, and has zero mean (the validation of this assumption will be revisited later), the standard deviation of the quantization error in D o2 is For a one-bit quantizer with σ 2 ε = 4/12, following the 3-sigma rule, (29) must hold to achieve k-bit resolution (considering only quantization noise) within the stable input range ±U max , Therefore,  Similarly, for modulator using an l-level multi-bit quantizer, we have σ 2 ε = 4/ 12 • (l − 1) 2 , thus It is worth repeating that the total number of required conversion cycles and the filter length is (2M − 1).For example, with l = 2 and U max = 2/3, it requires about 1000 cycles to achieve 16-bit resolution using L 2 min 2s to reconstruct the second-order IDC output.

1) Numerical Verification:
To verify our analysis, an input sweep between ±U max is applied to the modulator in Fig. 10.The quantization errors after being filtered by L 2 min 2s are shown in Fig. 11.With a one-bit quantizer, the quantization error is greater than the allowed 0.5 LSB when the inputs are close to ±U max .It means the required conversion cycle is underestimated by (30).The main reason is that ε becomes highly correlated at larger v in .By applying a 5-sigma rule, (30) can be corrected to match with the simulation results (i.e., change 3 √ 3 in (30) to 5 √ 3).With a multi-bit quantizer, the assumptions about ε hold and the numerical results agree well with the estimation by (31) (slightly conservative), and the worst-case errors are below 0.5 LSB.The quantization error peaks shown in the plots will disappear in actual implementations, with the circuit noise performing as an effective dithering signal.Using a one-bit second-order IDC as an example, the achievable k and crest-factor corrected SQNR using L 2 min 2s is shown in Fig. 12, together with that of sinc 2 and sinc 3 for comparison 4 .Although the quantization noise suppression capability of sinc 3 is slightly better than that of L 2 min 2s , its high β t of 1.67 is a significant drawback.Practically, various techniques can be used together with the filter to suppress quantization noise.Thus, most high-resolution IDCs are designed to be thermalnoise-limited [1].Therefore, owing to its good quantization noise suppression and low β t , L 2 min 2s is an excellent option for second-order IDC output reconstruction when periodic noise suppression is mandatory, where sinc 2 and sinc filters are usually employed.This is the third advantage of L 2 min 2s .
Without loss of generality, Fig. 13 presents the simulation results using L 2 min 2s for varying inputs with an OSR of 1024 as an example.It shows the output power spectral density of a −3.5 dBFS sinusoidal input and the SQNR as a function of the sine-wave amplitude after reconstruction by L 2 min 2s for a generic second-order incremental ΔΣ modulator.The achieved ∼100 dB peak SQNR also agrees with our analytical estimation of 20 • log 10 v in / √ 2/σ q , with σ q defined in (28).2) Experimental Verification: We verified the performance of L 2 min 2s by using it to reconstruct the output of a secondorder IDC chip prototype designed in [29].As shown in Fig. 14, L 2 min 2s outperforms sinc 2 at a low OSR when quantization noise dominates, and it outperforms both sinc 2 and sinc 3 at a high OSR when thermal noise dominates, which agrees with the analysis above.Specifically, to achieve the same output thermal noise level, the IDC can save approximately 28% of energy when using L 2 min 2s instead of sinc 3 for output reconstruction.
To summarize, when periodic noise suppression is necessary, owing to the low thermal noise penalty, more frequency notches, and strong quantization noise suppression capability, the symmetric L 2 min 2s filter excels for both first-order and second-order IDC output reconstruction, especially for highresolution thermal-noise-limited ones.

V. DESIGN EXAMPLE USING THE PROPOSED FILTERS
As analyzed above, using different filters for IDC output reconstruction can significantly affect its performance.The proposed L 2 min 2 filter and its symmetric version L 2 min 2s exhibit both good thermal noise and quantization suppression properties and are excellent candidates for first-order and second-order IDC output reconstruction.The flow of designing an IDC using the proposed filters is straightforward.For example, to achieve 17-bit peak-to-peak thermal-noise-limited resolution for an input range of ±0.6 V with a 1.2 V reference voltage, a sampling Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.clock frequency f s of 40 kHz, and a periodic frequency noise at 50 Hz (i.e., 1/800 • f s ), the design proceeds as follows.

2) Number of conversion cycles: a multi-bit second-order
modulator is used for such a high-resolution IDC.Considering the requirement of periodic noise suppression, we will use L 2 min 2s .In this example, we choose l = 9 considering the DAC implementation and matching complexity.From Table II in Appendix B, the required number of conversion cycles is 3.2 • (2 18.1 /0.5/ 8) 1/2 = 848.3) Periodic noise suppression: we place the first notch 3/(4M ) • f s of L 2 min 2s at 50 Hz, thus M should be 600.The total number of conversion cycles is 1200, which is enough for quantization noise suppression as calculated above.Next, we can verify the exact zero locations using Matlab (see Appendix A) and fine-tune the conversion cycles.From the numerical verification, an OSR of 1145 can best suppress the line noise.4) Thermal noise design: after knowing the thermal noise budget (= 0.8 • 2.56 pV 2 ), the total conversion cycles, and considering the filter's thermal noise penalty (i.e., 1.2), the IDC's input-referred thermal noise budget is σ 2 IRN = 2.06 pV 2 • 1145/1.2≈ 2 nV 2 .The modulator can then be designed after a system-level verification, e.g., using our open-source modulator simulation script.

VI. DIGITAL IMPLEMENTATION
The proposed linear filters are hardware-friendly to be implemented on-chip.In this section, we present two examples to design the L 2 min 2 and L 2 min 2s filter for one-bit input.FPGA and ASIC implementation results will also be discussed.Other implementations will also work if the filter kernel function (9) or ( 21) is satisfied.

A. Implementation of L 2 min 2
An example realization of the N -point filter weighting function (9) for L 2 min 2 with one-bit input is shown in Fig. 15.It requires a ripple counter, a subtractor, an adder, and an ANDgate.Initially, the ripple counter is reset to 0, while the subtractor is reset to w N = N (N + 1)/2.The weight generator updates its output w n at f s (the input data rate).The adder is gated by d[n] and is updated only when the input bit is "1".Notice that the adder operates at the falling edge of f s thus preparing the correct weight w n .Similar to Hogenauer [20], we use the worst-case register growth to calculate the bitwidth requirement of each building block, which is log 2 (N + 1) for the ripple counter, log 2 N 2 + N − 1 for the subtractor, and (3 log 2 N − 1) for the adder.Practically, truncation can be applied to the subtractor and adder to reduce the number of registers (i.e., truncating w n ).For example, refer to (17), a resolution of 12.6bit can be achieved with an N of 1024 using L 2 min 2 for output reconstruction.Ideally, the ripple counter, subtractor, and adder bitwidths are 11, 20, and 29, respectively.As shown in Fig. 16, the resolution loss is only 0.06-bit after truncating the subtractor and adder by 4 bit (i.e., from 20 to 16 bit).Based on the numerical simulation results, truncating the subtractor bitwidth by 20% of its theoretical value has negligible influences on the IDC performance.

B. Implementation of L 2 min 2s
The (2M − 1)-point filter kernel of (21) for L 2 min 2s with one-bit input can be implemented by re-using the architecture of Fig. 15, with the modified design shown in Fig. 17.Initially, the ripple counter output is reset (via rst c ) to M and configured as a down counter.The S/A block performs as an adder with its initial output reset to 0. After operating for M clock cycles, the counter output will be 0. Its output is then reset to 1 and configured as an up-counter.The S/A is reconfigured as a subtractor.The filter then operates for another M clock cycle (the last weight w 2M = 0) to finish one IDC sample reconstruction.Finally, the filter is reset for the next conversion.The required bitwidths for the counter, S/A block, and the adder are log 2 (M + 1) , log 2 M 2 + M − 1 , and 3 log 2 M , respectively.Similarly, bit truncation of the S/A and adder block can be applied.The conclusion drawn above still holds that truncating the S/A bitwidth (and thus the adder) by 20% of its theoretical value does not affect the IDC performance.
The above design examples are for one-bit input, for multi-bit d[n] (e.g., B-bit), a B × log 2 M 2 + M − 1 bit multiplier can be used to compute d[n] • w n , whose hardware overhead becomes slightly higher.Efficient implementation of ( 9) and (21) for multi-bit input deserves further investigation.

C. Synthesis Results
Apart from the fully customized digital design, the proposed linear filters can also be handily synthesized for FPGA and ASIC targets.For instance, the L 2 min 2 and L 2 min 2s filters without register bitwidth truncation are synthesized herein for one-bit input and operate for 1024 cycles.FPGA synthesis was performed using Vivado for an Artix-7 device, xc7a12tcpg238-3.ASIC synthesis was performed using Synopsys design compiler targeting a commercial standard cell library in 180 nm CMOS technology with a 1.8V supply.Running at an example 1 MHz input data rate, the worst-case power dissipation is simulated using the cadence Spectre platform with d[n] ≡ 1 (i.e., all bits are one to keep the filter busy, which will not occur in actual conversion unless the modulator and, thus, the quantizer is overloaded; the purpose here is to estimate the upper limit of the filter's power consumption).For performance benchmarks, the synthesis results of L 2 min 2 and L 2 min 2s are shown in Fig. 18, together with the popular highorder CoI and sinc filters (using CIC architecture working in one-shot mode, and with a differential delay of one in the comb stage [20]).As expected, CoI 2 occupies a smaller area and consumes less power due to its simple topology.However, it is less used due to its thermal noise penalty and lack of frequency notches.The proposed filters show high area efficiency with comparable power consumption but excel for their low Fig. 18.Hardware complexity of L 2 min 2 and L 2 min 2s implemented in (a) an Artix-7 FPGA and (b) a 180 nm process ASIC target (FPGA power consumption is not shown as the estimation is not accurate for small digital designs.#LUTs: number of the look-up tables, #FF: number of flip-flops).β t .In IDC designs, the power and area of the digital filter are often negligible compared to that consumed by the analog integrators.

VII. SUMMARY AND DISCUSSION
To summarize, two linear reconstruction filters for IDC are proposed, with analytical, numerical, and experimental results presented to demonstrate their overall superior performance for first-order and second-order incremental ΔΣ modulators in terms of quantization noise suppression, thermal noise suppression, and hardware complexity.Table I also compares other key metrics of the proposed L 2 min 2s filter, such as the frequency notch, stop-band roll-off, etc., with the popular linear filters.Specifically, the advantages of employing the proposed reconstruction filters include the following.(1) It has a low thermal noise penalty of 1.2, the smallest among the existing high-order linear filters.To achieve the same output thermal noise level after reconstruction, using L 2 min 2/2s can reduce the IDC energy consumption by 11%, 28%, and 33% compared to that of using a CoI 2 /sinc 2 , sinc 3 , and CoI 3 filter, respectively.
(2) In addition, when periodic noise suppression is needed, the L 2 min 2s filter can provide more frequency notches than other high-order sinc filters, thus suppressing periodic noise (e.g., designing the first notch of the filter to be the same as the periodic noise frequency) without greatly sacrificing the IDC's sampling rate.For example, at an OSR of 512, compared to the Steensgaard's approach [22], the L 2 min 2s filter can achieve about 40 dB higher SNR when applied to a generic second-order modulator.In this paper, for conciseness, only the generic modulator topologies are analyzed in detail, but the proposed filters are applicable to other modulator topologies/variants as indicated in Appendix B, Table II  can be verified using our open-source numerical scripts.

VIII. CONCLUSION
Two efficient linear reconstruction filters, L 2 min 2 and L 2 min 2s , are presented in this article.The filter kernel is derived based on the L 2 -norm to achieve a globally minimized IDC output reconstruction error.It exhibits the lowest thermal noise penalty compared with the classical high-order linear filters while providing a strong quantization noise suppression capability.Implementation of the filters is hardware friendly.Overall, L 2 min 2 and L 2 min 2s are excellent candidates for firstand second-order modulator output reconstruction, especially for thermal-noise-limited ones.Methodologies presented in this paper can also be used to derive filters for higher-order IDCs.Some efforts are still required to extend our method, including implementing the proposed linear filters for multi-bit inputs with minimal hardware resources and extending the filter implementation for free-running ΔΣ ADCs.

APPENDIX A
This appendix provides the derivation of the number and location of the zeros in the transfer function of the proposed L 2 min 2s filter.For a (2M − 1)-point symmetric filter described by (21), its z-domain transfer function is (without including the filter normalization term 1/ and Multiplying both sides by z −1 yields By subtracting (a4) from (a3), we obtain Finally, From (a6), H(z) has three poles at z = 1 (i.e., f = 0) of the z-plane.Its zeros are the roots of H(z) = 0, with According to the fundamental theorem of algebra, (a7) has (2M + 1) roots, meaning (a6) provides (2M + 1) zeros in the frequency domain.Assuming M is large and M + 1 ≈ M holds, (a7) is modified to The first root of (a8) is and the rest 2M roots are Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.1/2 * Umax is the normalized input range w.r.t.its reference and is a dimensionless number.† Except for sinc 1 , the rest are derived under a uniform dithering of U {−1/3, 1/3} with Umax 2/3.5-sigma rule applied as explained in Section III-C, with Umax 2/3.Fitted expression, same performance as CoI 2 due to the large nonlinearity after reconstruction.Derivations are valid for l 9 with Umax 2/3 (if a 2-bit quantizer with l = 5 is used, Umax 1/2).
which are all on the unit circle of the z-plane (i.e., |z| = 1).By applying Euler's formula to (a10), we arrive at z = exp ±j arccos 1 2M + 2πk Therefore, besides the zero at f = 0 indicated by (a9), two more zeros at f = 0 will be produced as in (a11) (following the assumption of a large M ).Therefore, the three zeros and three poles cancel and |H(1)| = 1 holds after normalization (i.e., no DC signal attenuation).The frequencies of the other (2M − 2) zeros indicated by (a11) are at and where f s is the filter input data rate.The frequency of the first zero can be found by (a13) with k = (M − 1), which is 3/ (4M ) • f s .Note that (a12) and (a13) are close estimations of the zero locations.After deriving the weighting function w n as described in Section IV-A, the provided Matlab script 5 can be utilized to produce the pole-zero plots and frequency response during design, thus finding the exact zero frequencies of the filter.

APPENDIX B
For clarity, analysis of the L 2 min 2 filter applied to a secondorder modulator and the L 2 min 2s filter applied to a first-order modulator is not included in the body of the paper, which can be derived following the same procedures presented in Sections III-B and IV-C, respectively.In this appendix, we derive and 5 download from github.com/bowanghbku/L2min2-Filter/tabulate the number of clock cycles (i.e., OSR) required to achieve k-bit peak-to-peak resolution within U max (considering only quantization noise) for the popular one-bit first-order, onebit second-order, and multi-bit second-order incremental ΔΣ modulators reconstructed by different linear filters.The analytical expressions in Table II agree well with the numerical simulations and can be utilized for theoretical calculation during design.The analytical expressions hold for both constant and varying input signals.Practically, changes in modulator parameters can cause a difference.System-level simulations or experimental measurements should be used to verify the calculated OSR during design.

Manuscript received 22
December 2022; revised 28 May 2023 and 7 August 2023; accepted 7 August 2023.Date of current version 19 September 2023.This work was supported by the Qatar National Research Fund under Grant NPRP13S-0122-200135.The associate editor coordinating the review of this manuscript and approving it for publication was Prof. Mojtaba Soltanalian.(Corresponding author: Bo Wang.)

Fig. 2 .
Fig.2.Generic model of a first-order incremental ΔΣ modulator with a delaying integrator and a one-bit quantizer.

Fig. 4 .
Fig. 4. Normalized weighting function (impulse response) of the proposed L 2 min 2 filter and the popular CoI filters, with N = 50 as an example.

Fig. 6 .
Fig.6.Considering only quantization noise: peak-to-peak resolution (left) and crest-factor corrected SQNR (right) of the one-bit first-order IDC at different OSR (uniform dithering added excepted when using CoI 1 ).

Fig. 12 .
Fig. 12. Considering only quantization noise: peak-to-peak resolution (left) and crest-factor corrected SQNR (right) of the one-bit second-order IDC at different OSRs.

Fig. 14 .
Fig. 14.Measured second-order IDC output error reconstructed by different linear filters; (a) at a low OSR when quantization noise dominates; and (b) at a high OSR when thermal noise dominates.

Fig. 15 .
Fig. 15.Example implementation of the L 2 min 2 filter with one-bit input.

Fig. 17 .
Fig. 17.Example implementation of the L 2 min 2s filter with one-bit input.
, andAuthorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE I PERFORMANCE
SUMMARY OF DIFFERENT LINEAR RECONSTRUCTION FILTERS FOR IDCS

TABLE II NUMBER
OF CYCLES (OSR) TO ACHIEVE k-BIT PEAK-TO-PEAK RESOLUTION WITHIN U * max FOR DIFFERENT MODULATOR TOPOLOGY AND RECONSTRUCTION FILTER COMBINATIONS