Adaptable Frequency Counter With Phase Filtering for Resonance Frequency Monitoring in Nanomechanical Sensing

Nanomechanical sensors based on detecting and tracking resonance frequency shifts are to be used in many applications. Various open- and closed-loop tracking schemes, all offering a trade-off between speed and precision, have been studied both theoretically and experimentally. In this work, we advocate the use of a frequency counter (FC) as a frequency shift monitor in conjunction with a self-sustaining oscillator (SSO) nanoelectromechanical system (NEMS) configuration. We derive a theoretical model for characterizing the speed and precision of frequency measurements with state-of-the-art FCs. Based on the understanding provided by this model, we introduce novel enhancements to FCs that result in a trade-off characteristics which is on a par with the other tracking schemes. We describe a low-cost field-programmable-gate array (FPGA)-based implementation for the proposed FC and use it with the SSO-NEMS device in order to study its frequency tracking performance. We compare the proposed approach with the phase-locked-loop-based scheme both in theory and experimentally. Our results show that similar or better performance can be achieved at a substantially lower cost and improved ease of use. We obtain almost perfect correspondence between the theoretical model predictions and the experimental measurements.


I. INTRODUCTION
F REQUENCY counters are a standard equipment to char- acterize the frequency fluctuations of oscillators and clocks, especially in estimating the well-established timedomain measure of frequency stability, namely the Allan Deviation (AD) [1], [2].The averaging of instantaneous frequency over a certain observation (gate) time, which forms the basis for calculating AD, is naturally performed with a stan-dard frequency counter (FC).In this work, we propose using an improved FC with high resolution and accuracy [3] as a frequency shift monitor for an oscillatory signal that is generated by a self-sustaining oscillator (SSO)-nanoelectromechanical system (NEMS) device, as opposed to simply using it as a tool for characterizing its raw frequency stability in the presence of thermomechanical and detection noise.The goal is to detect small frequency shifts due to events of interest, arising, e.g., from the interaction of the nanomechanical resonator with a mass, temperature, or force stimulus, as fast and precise as possible.We develop a theoretical model for characterizing the FC measurements, and show that the averaging (gate) time of a standard counter can be used to balance the trade-off between the speed of detection and measurement precision.Based on the understanding provided by this model, we propose a novel counter architecture where the simple averaging of frequency over a gate time that spans across multiple signal cycles is replaced by a digital filter with adjustable bandwidth that operates on the resampled timestamps of the signal edges.The filtered timestamps are subsequently mapped to frequency measurements.We show that it is crucial to perform the filtering before the conversion of the timestamps to frequency values, especially in cases where transduction noise is dominant.While the proposed counter is not suitable for directly estimating the raw AD of the signal source anymore, it offers better trade-off characteristics as a frequency shift monitor.Conceptually, the output of the FC could be used to synthesize a cleaner oscillatory signal that tracks the frequency shifts of interest but with subdued unwanted frequency fluctuations.We characterize the precision of the counter output by computing the AD of this conceptually synthesized signal.Furthermore, we address an issue that relates to input signal dictated sampling rate in FCs.Our approach introduces a robust resampling technique that results in a consistent, fixed sampling frequency.This facilitates subsequent digital signal processing (DSP) on the output of the FC, enhancing its versatility and application scope as compared with standard FC designs.This method marks an improvement over conventional implementations as documented in [3], [4], and [5].
The standard and well-established technique for tracking the frequency changes of an oscillatory signal source is a phase-locked loop (PLL), where the signal generated by a clean controlled-oscillator (CO) is phase-and frequency locked to the noisy signal source with a closed-loop feedback system [6].The feedback loop is designed so that the CO tracks the frequency shifts of interest while suppressing rapid fluctuations due to noise, with the loop bandwidth serving as the control knob for trading off tracking speed versus precision.The precision of the PLL output is characterized by computing the AD of the CO signal.In a PLL implementation, in addition to the CO, a phase difference (between the signal source and the CO output) detector is needed to generate the error signal in the feedback loop.In the context of NEMSbased sensors, PLLs are usually realized using a lock-in amplifier-based setup [7], [8], [9].Instead of locking a CO to the sensor signal to track its frequency, we recommend a new design using an FC to directly measure the resonance frequency of the sensor.The sensor itself is excited by narrow pulses with low energy and oscillates freely [9].We use a reciprocal FC in a continuous measurement mode where the counter hardware is not reset between measurements.This technique was first used in the HP 5371 frequency analyser [4].It greatly increases the number of samples.The use of continuous time interval measurements makes it easier to study the dynamic frequency behavior of a signal.
We compare the proposed self-sustaining oscillator (SSO) with FC scheme to the PLL approach both in theory and experiment, and show that similar or better performance can be achieved with respect to frequency resolution and stability of operation.We describe a low-cost field-programmablegate array (FPGA)-based implementation of the proposed FC.While the DSP in a lock-in amplifier can also be implemented on an FPGA, considerably more resources are needed to implement the CO, the phase demodulators, and the rest of the PLL functionality.Furthermore, only a low-Q bandpass filter is used to condition the signal for the FC.Thus, the proposed FC-based scheme offers similar or better performance but at a substantially lower-cost and improved ease-of-use.

II. THEORY A. Interpolating Reciprocal FC With Continuous Timestamping
We consider a state-of-the-art counter, namely an interpolating reciprocal counter with continuous timestamping [3], [5].In order to understand the speed and precision properties of such a counter used as a frequency shift monitor, we develop a simple model that captures its characteristics.Let f s (t) denote the instantaneous frequency (measured in units of Hz) of the signal source, which includes any fluctuations due to noise as well as shifts due to events of interest.We define φ(t) = f s (t) dt as the signal phase (unitless, equal to phase in radians divided by 2π ).In the FC, timestamps for the boundaries of full signal cycles, i.e., at the rising signal edges, are generated using a high-frequency, high-precision internal clock and an interpolator.That is, time t n where φ(t n ) = n (n is an integer) is measured with a clock counter for full clock cycles and an interpolator between two clock edges that precede and succeed a signal edge [5].
In the typical setting where an FC is used to characterize the frequency stability of a high-quality signal source, the resolution of the timestamps may be limited by the clock frequency and the quality of the interpolating circuitry.In the application, we consider here, the signal source exhibits relatively large frequency fluctuations, resulting in deviations in the timestamps that are much larger than this resolution limit.In the model, we thus assume that timestamps t n can be measured precisely.In a reciprocal counter, the frequency of the source is estimated from the timestamps for one signal cycle with Thus, f c (t n ) represents the average of the instantaneous frequency f s (t) over one signal cycle between t n−1 and t n .The highest rate at which an FC can generate an output is limited by the signal frequency (or twice the signal frequency if falling signal edges are also used with a 50% duty cycle).With (1), the gate time of the counter is set to the cycle time of the signal source.A frequency estimate with gate time of k cycles can be computed with If a sudden frequency shift occurs in the signal source between t n−1 and t n , its effect will be fully reflected in the frequency estimate in (1) at t n+1 (within two cycles), whereas it will be at t n+k (within k + 1 cycles) for the one in (2).However, the precision of the estimate in (2) is higher since rapid frequency fluctuations are suppressed due to the inherent averaging over k cycles instead of just one.Thus, gate time can be used as a control knob for trading off response speed versus precision in an FC that is used as a frequency shift monitor.
The averaging inherent in (2) corresponds to a simple moving average filter (MAVGF).Instead, any filter that may offer a better response speed versus noise filtering characteristics can be used.In order to pursue this idea, we first need to better understand how frequency fluctuations affect the frequency estimates computed with an FC.For a constant nominal signal frequency f o , we consider where α(t) represents the time (phase) noise of the source.Ideally, the instantaneous frequency f s (t) and the fractional frequency y s (t) can be computed from φ(t) with a timederivative as follows: where α(t) represents the fractional frequency noise.
Let us now derive the fractional frequency estimate for a reciprocal counter.Based on (3), the timestamps t n satisfy is the nominal cycle time of the signal.We substitute this expression for t n in (1) to derive the following: for the fractional frequency estimate computed in a reciprocal counter.The operation ((α(t n ) − α(t n−1 ))/T o ) in ( 5) above corresponds to the (discrete-time) derivative of α(t) over one cycle.Ideally, as in (4), the conversion of phase to frequency is a linear transformation.However, in a reciprocal counter, this conversion involves a nonlinear operation, as seen in (5).
If z (fractional frequency noise) denotes the time derivative of α(t), the (ideal) linear transformation to fractional frequency can be represented by 1+z as in (4), whereas it is given by the nonlinear function (1/(1 − z)) in (5) for a reciprocal counter.The power series expansion indicates that the two transformations are (approximately) equal only when z is small.Detection noise (generated in the transduction of mechanical motion into an electrical signal) in a NEMS device results in white phase noise [7], [8], [9].This corresponds to a frequency fluctuation spectrum that increases with frequency.Thus, z may contain strong high-frequency components.In this case, the quadratic z 2 term in the power series expansion needs to be taken into account to accurately characterize the fluctuations in the frequency estimated by a reciprocal counter.The high-frequency spectral components in z mix with each other through z 2 to produce low-frequency fluctuations, known as intermodulation noise.In order to prevent or minimize the degrading impact of this nonlinear phenomenon on the accuracy of the frequency estimates computed by an FC, a low-pass digital filter can be applied to the timestamps t n , and hence to phase noise samples α(t n ), before the timestamps are converted to frequency estimates.Ideally when phase to frequency conversion is linear, a (linear) filter may be applied to the phase, or equivalently, to the frequency data, since the ordering of linear transformations does not change the final outcome.In the case of a reciprocal FC, the low-frequency intermodulation noise generated inherently in the conversion of timestamps to frequency estimates cannot be removed with subsequent low-pass filtering.While timestamp-to-frequency conversion always generates intermodulation noise, its effect will be minimal if high-frequency fluctuations are suppressed first, before the conversion, with a digital filter.The bandwidth and the characteristics of this filter can be chosen to trade off speed versus precision when the proposed counter is used as a frequency shift monitor.

B. Sampling Rate and Decimation
In a reciprocal counter, the sampling rate at the output is determined directly by the frequency of the input signal, given by f rate = f s /k, where k is the number of cycles counted within one gate time.This input dependency results in problems when subsequent DSP is performed on the sampled FC output.For instance, if any sort of filtering is performed, a change in the input signal frequency will consequently alter the sampling rate, thereby affecting the dynamics of the filter.To mitigate this issue, the input signal-dependent sampling rate should be converted into a fixed one.
One approach to achieving a fixed sampling rate is to implement continuous event-triggered timestamp counting as proposed in [5].This involves using a dedicated counter that generates trigger events at regular intervals of T int , which determines the sampling rate.However, the samples cannot be taken precisely at multiples of T int .Instead, they are generated at the next rising edge of the input signal.As a result, there is an inherent uncertainty in the sampling time, up to one period of the input signal.The impact of this uncertainty on the overall measurement varies depending on the number of signal periods encompassed within one interval.When there are numerous signal periods, the uncertainty has a lesser effect.However, if there are only a few signal periods, the irregular sampling interval introduces errors that can affect the accuracy of the measurement.
Although the sampling rate f s /k is directly linked to the input frequency f s , the sampling instants always align with the internal clock (with frequency f CLK ) edges of the FC.The sampling rate can be transformed up to f CLK by simply interpolating the acquired data through the use of a zero-order hold.However, this introduces high-frequency harmonics due to the abrupt transitions between the samples.To address this, a lowpass filter (LPF) can be applied to attenuate the harmonics.The combined process of low-pass filtering and decimation (to a fixed fraction of f CLK ) after the zero-order hold can be efficiently achieved using a cascaded integrator-comb filter (CIC), as described in [10].Fig. 1(a) depicts the second-order CIC filter employed in this study, featuring two integrator sections and two comb sections.The comb sections introduce a delay of N = 2.The downsampler, with a value of R = 2 13 , is positioned between the integration and comb sections.Thus, the sampling rate of the final output is given by f new = f CLK /R, independent of the input frequency f s .Fig. 1(b) shows the transfer function of the CIC filter after decimation.Notably, it does not exhibit a distinct separation between the passband and stopband, thus necessitating further filtering with Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.a finite impulse response (FIR) or infinite impulse response (IIR) filter.
The speed of the response to a frequency jump is intrinsically limited by the input signal frequency as described in (1).When the data is resampled using the CIC filter, it results in additional filtering.This additional filtering could potentially slow down the response, particularly if the new sampling frequency ( f new ) is less than the original sampling rate ( f rate ).However, the range of frequency steps that this method can handle is theoretically unlimited.It is capable of tracking frequency steps of any magnitude, making it exceptionally suitable for gathering data from devices that require monitoring across a broad range of frequencies.

C. Allan Deviation
AD σ y (τ ) is a widely used and well-established method for characterizing frequency fluctuations [7], [11], [12].For AD, the frequency values need to be normalized, resulting in a fractional frequency AD is the square root of the Allan Variance, which can be computed from sampled frequency data using the following equation: Here, y i represents the ith sample of the averaged frequency over the averaging time τ .It is calculated as Thus, the averaging operation above has to be part of the frequency measurement and data acquisition process.An FC naturally performs this operation when it is used to characterize the raw frequency fluctuations of its input signal.On the other hand, ( 8) is routinely used in practice on measured frequency data, also in cases where an FC is not used and/or the averaging operation is not inherently included in the measurement process.Such use is justified only when the sampling rate is sufficiently large when compared with the system bandwidth, i.e., the smallest time τ that determines the sampling interval is small enough.In this case, the frequency that is being measured is (almost) constant over the sampling interval (smallest τ ) resulting in Averaging when τ is equal to an integer m multiple of the sampling interval is performed by simply averaging m consecutive samples of the acquired raw data.When an FC is employed as a frequency shift monitor, as we propose in this work, in contrast with its use in characterizing the frequency fluctuations of its input signal, AD should be computed for the conceptually synthesized oscillatory signal based on the counter output.Thus, the averaging in (9) needs to be performed in addition to the inherent averaging performed by the counter itself.While the inherent averaging of the counter is over a time interval determined by its gate time specification, the average in ( 9) is computed for all τ that is of interest in the AD characterization.
The Allan Variance can alternatively be computed in the frequency domain if the power spectral density of fractional frequency fluctuations, denoted by S y (ω), is known.The equation for this computation, shown below, includes the frequency domain equivalent of the averaging operation in (9), should thus be used on S y (ω) which was measured or computed without inherent averaging.For white frequency fluctuations, where S y (ω) is constant, (11) simplifies to Hence, in systems limited by thermal white noise, the resulting AD exhibits a σ y ∝ 1/ √ τ dependence on the averaging time τ .
This study focuses on two primary noise sources, thermomechanical noise and detection noise.Thermomechanical noise is regarded as the fundamental noise source in NEMS resonators, resulting from the random movement of resonator molecules.On the other hand, detection noise arises from the transduction of the resonator's mechanical motion into an electrical signal, as well as from electronic components involved in the detection process.
The power spectral density of frequency noise, S ω (ω), can be computed as a superposition of the power spectral densities of thermomechanical and detection phase noise, multiplied by Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
their corresponding transfer functions (magnitude squared) as derived in [7] and [9].This yields the spectral density of fractional frequency noise required for computing the AD where K = (S θ d /S θ th ) 1/2 is the ratio between the thermal and detection noise and H θ th and H θ d are the transfer function of the thermomechanical and detection noise to the frequency output, respectively.For the SSO frequency tracking scheme, the transfer functions are given by [9] where H r is a single-pole LPF with the time constant of the resonator.H L has low-pass characteristics and represents the bandwidth limiting (noise filtering) mechanisms in the frequency detection device.The theoretical computation of AD is performed with the frequency domain approach in (11), where the spectral density of fractional frequency noise is first computed using a frequency domain model of the SSO and the FC, as in ( 13) and ( 14), that includes intermodulation noise generated in the timestamp to frequency conversion.

III. METHODS
We describe the experimental setup for the comparison of the two methods, the proposed FC and the PLL frequency detector (PLLFD), for frequency shift monitoring of an oscillator.Our measure of assessment for precision is the AD.Central to our investigation is the SSO, as detailed in [9], driven by narrow pulses and oscillating freely.The pulse duration and timing is automatically adjusted to attain the desired resonance frequency within a closed-loop setup involving the resonator and the pulse generation mechanisms.Notably, the frequency measurement and detection operate outside of this loop.Our study involves resonance frequency measurements using the proposed FC and the established PLLFD, as depicted in Fig. 2(b).We compute the AD in two experimental conditions, using the FC output and the PLLFD output.For the FC, we explore filter configurations, cut-off frequencies, and timestamp versus frequency filtering.

A. NEMS Resonator Setup
In this study, we utilized a NEMS resonator consisting of a square 50-nm thick silicon nitride membrane measuring 1018 µm on each side, as introduced in [9] and shown in Fig. 2(a).To achieve electrical transduction, we incorporated two 5 µm-wide gold (Au) electrodes spanning over the resonator.The membrane was placed within a static magnetic field of approximately 0.8 T, generated by a Halbach array composed of neodymium magnets.The orientation of the traces was perpendicular to the magnetic field.By capitalizing on the resulting Lorentz force, one metal trace is served for the purpose of driving the resonator with an ac current and the second electrode for detecting its motion through the magnetomotively induced voltage.
To amplify the detected signal from the metal trace, we employed a custom-made, low-noise differential pre-amplifier with a gain factor of 10 4 .The NEMS was operated in vacuum with a pressure of 8.2 • 10 −6 mbar.The NEMS resonator had a resonance frequency of f r = 119 kHz and a quality factor of Q = 57.5 k.Consequently, the response time of the NEMS resonator is calculated with τ r = 2Q/ω r , is 154 ms.

B. Self-Sustaining Oscillator
The resonator utilized in this study operates as an SSO (implemented in PHILL from Invisible-Light Labs GmbH), Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.as described in [9] and depicted in Fig. 2(b).The transduced output of the NEMS resonator is connected to a preamplifier (PA).The amplified signal is then directed to a bandpass filter (BPF) (with gain 1 and bandwidth 5 or 20 kHz for different measurements).The BPF inside the SSO loop is not needed to improve the SSO performance, and in some cases, it is not necessary.However, it gives the system the ability of mode selection by suppressing the buildup of unwanted modes.On the other hand, the BPF bandwidth limits the system response speed.Therefore, it is important to ensure that the bandwidth of the BPF is large enough in order to prevent it from becoming a limiting factor in the system's overall response speed.In the context of this work, where the NEMS is employed as an infrared detector with a thermal response time constant (τ resp ) ranging from 50 to 200 ms, a BPF bandwidth exceeding 1 kHz is deemed adequate.The output of the bandpass filter is linked to a comparator (COMP) with a 50 mV hysteresis, which transforms the sinusoidal signal into a rectangular waveform, triggering the pulse generation mechanism that drives the NEMS resonator.The pulse generation mechanism is comprised of two components: one generates a pulse with a width of T w , while the other delays the pulse generated at the feedback output by a time of T d .Since the NEMS resonator can only tolerate low currents, the generated pulse needs to be attenuated (ATT) by a factor of 10 5 before being applied to the NEMS.
Frequency detection is accomplished using two different methods, the PLLFD and our proposed FC.In principle, the PLLFD and FC can be connected anywhere in the SSO loop.Before the data is acquired by both frequency detectors, antialias filtering has to be performed.The anti-aliasing filter will limit the noise going into the frequency detector and will take part in the H L filtering term of (14).It will also prevent noise folding which would degrade the resulting AD as shown in [9].For the PLLFD, this anti-aliasing function is served by the LPF in its phase detector, and the PLLFD is out of convenience connected after the PA.On the other hand, to avoid aliasing in the FC, the signal must first pass through a bandpass filter with a bandwidth less than half of the input signal frequency, which also coincides with the maximum sampling rate of the FC.For devices similar to the one used in this work, BPF bandwidths below 50 kHz will fullfill the criteria.To eliminate the need for two bandpass filters (one in the SSO loop and one at the input of the FC), the FC can be connected at any position in between the bandpass filter and the resonator, and the in-loop BPF will act as an anti-aliasing filter.Thus, the FC is connected to the output of the bandpass filter.
With the proposed technique, tracking the resonance frequency of a device does not require the construction of a complex control system.Knowledge of the readout method, a rough estimation of the resonance frequency and the response speed of the device are sufficient to find an oscillation and track its frequency.The devices utilized in this study are characterized by the resonant frequency 105 kHz < f r < 125 kHz and response times 50 ms < τ resp < 200 ms.Notably, the magnetomotive readout employed measures the velocity, rather than the position, of the resonator.This method induces a (π/2) phase shift relative to the position.Consequently, the −(π/2) phase shift (from the drive to position) intrinsic to the resonator is neutralized by the readout's phase shift, resulting in a net in-loop phase of 0. This analysis assumes minimal electrical delays at lower frequencies, although such delays may warrant consideration at higher frequencies.Hence, in this context, the pulse delay can be set to T d = 0.If an optical readout that does not cancel out the phase delay caused by the resonator is used, the pulse delay should be set to where f BPF is the bandpass central frequency.The pulse delay element will generate a −3(π/2) phase shift (time delay corresponds to a negative phase shift) at f BPF .The BPF exhibits a phase shift of 0 only at this central frequency.By sweeping the central frequency of the BPF, the loop phase condition will only be met if f BPF = f r and an oscillation will be excited.

C. Frequency Counter
Fig. 3 illustrates the block diagram of the FC architecture.The FC employed in this study is an enhanced version of a state-of-the-art interpolating reciprocal counter with continuous trigger events (implemented in PHILL from Invisible-Light Labs GmbH).It has been modified to better suit the task of tracking resonance frequency changes with improved usability.
The front-end of the FC is a frequency divider, which enables counting k cycles of the input signal, where k can be any integer and specifies the number of counted periods in one timestamp.To avoid aliasing and noise folding, it is recommended to keep k as small as possible, i.e., set it to k = 1, since the sampling rate of the counter, f rate , is directly dependent on the input signal frequency, given by f rate = f s /k.
The subsequent stage of the system is the main counter with an interpolator.It functions as a standard reciprocal counter, tallying the number of rising edges of the internal clock that occur in an interval of k periods of the input signal and generating the timestamps for the interval boundaries.However, due to the potential error of up to one clock cycle in such a counter, an interpolation mechanism is employed to enhance the precision of the timestamps up to 100 ps at 100 kHz.
The output rate of the main counter is directly linked to the frequency of its input, necessitating resampling to achieve a fixed sampling rate.First, the timestamp series is interpolated onto the internal clock transitions time grid using a zeroorder hold.Second, it is decimated to the desired sampling rate through a CIC decimator.Third, the resampled timestamp series is low-pass filtered, which defines the final system bandwidth as specified by H L in (14).Finally, the filtered timestamp series is converted to the frequency output using (1) or (2).
Constructing a digital PLL entails three critical components: an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and field-programmable gate array (FPGA) circuitry.For minimizing time quantization errors, the ADC and DAC typically operate at high sampling rates, often exceeding 40 MHz, and generally require a resolution of 14 bits.It is important to note that both the ADC and the DAC, particularly those with such specifications, are expensive components.On the FPGA, implementing demodulators and proportional-integral-derivative (PID) controllers for the PLL involves multiplicative operations.This necessitates using FPGAs equipped with DSP slices for efficient execution.However, FPGAs with DSP slices are considerably more expensive than their non-DSP counterparts.
Conversely, an FC's architecture includes a COMP, an FPGA, and an interpolator.COMPs are relatively inexpensive components and can even be omitted if the counter is connected post the SSO's COMP, as utilized in this study.The interpolator can be integrated internally via a time-todigital converter (TDC), as discussed in [13], or implemented using cost-effective integrated circuits like the TDC7200.As illustrated in Fig. 3, all components of the FC can be incorporated into an economical FPGA without DSP slices.This aspect renders the FC a more budget-friendly alternative compared to the digital PLL.

IV. RESULTS AND DISCUSSION
We conducted 10 s measurements (as shown in Fig. 4) to analyze the output frequency fluctuations due to thermomechanical and detection noise for various frequency shift detection scenarios and system parameter choices.The experimental setup, which incorporated magneto-motive readout, introduced significant detection noise.Consequently, the thermomechanical noise peak could not be resolved at the resonator output, resulting in a value of K > 1.As discussed in [9] and [11], this leads to an AD with a 1/τ dependency if the system time constant is shorter than the resonator time constant.When K < 1, the sensor is intrinsically limited by the thermomechanical noise of the resonator, not by the noise generated in the transduction and the frequency detection mechanisms.Also in such thermomechanically limited systems, filtering in the frequency detector as represented by H L in ( 14) can be used to trade off speed versus accuracy.However, the enhancement techniques proposed and that are to be demonstrated below, while beneficial for considerably alleviating detection noise influence, will not have the same level of impact on systems where thermomechanical noise is the dominant factor.In the following, we examine the FC under four different conditions.

A. Filtering of Timestamp Data Versus Frequency Data
In the first experiment, shown in Fig. 5, we compare two alternatives for an FC, with conversion of timestamp series to frequency data after or before low-pass filtering.As articulated in Section II, the expected 1/τ dependence of the AD is altered to 1/ √ τ for large τ .This is due to the mixing of the high-frequency noise components by the nonlinearity of the time-to-frequency conversion process, resulting in intermodulation noise at lower frequencies.This can be alleviated by removing or reducing high-frequency noise before time-tofrequency conversion by low-pass filtering the counter output in the form of a timestamp series.The ADs of these measurements are shown in Fig. 5 showing that filtering the timestamp data first and then conversion to frequency yields better AD than conversion before filtering, as predicted by theory.

B. Sweeping the Gate Time of the Counter
In the second experiment, we investigate the impact of varying the number of counted periods k of the signal, i.e., the gate time of the counter, on the performance and the filtering process in the FC.As seen in Fig. 6, increasing k seemingly does not lead to an improvement in the AD without suppressing it (raw).In contrast, low-pass filtering the FC output results in improved ADs.The best AD is observed for k = 1 with the LPF.
ADs for the unfiltered raw data at the counter output fall exactly on top of each other when k is varied, albeit starting at larger τ values for larger k due to the larger sampling interval of k periods.This result is puzzling at first thought, since theoretical considerations indicate that we should be able to use the gate time of the counter as a control knob for trading Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 5. Effect of the position (before or after time-to-frequency conversion) of a first-order LPF with a cut-off frequency of 200 Hz on the AD.The "Raw" curve is for the raw unprocessed output of the FC without any subsequent filtering.The "LPF time" curve corresponds to the output of the proposed FC with low-pass filtering before time-to-frequency conversion.The "LPF frequency" curve represents the use-case of filtering the output of a conventional reciprocal counter where time-tofrequency conversion has already been performed.The SSO loop BPF with a 20-kHz bandwidth was used for all experiments.Fig. 6.Comparison between the ADs of raw and filtered (in the FC with a first-order LPF with a cut-off frequency of 200 Hz) data for varying gate time as set with k counted periods.The SSO loop bandpass filter (BPF) used in this experiment had a bandwidth of 5 kHz with the corresponding time constant τ BPF .
off response speed versus precision.While the response time of the counter is definitely prolonged with increased gate time (sudden frequency shift at the input will be fully reflected in the counter output after k periods of the input, as discussed before), results in Fig. 6 suggest that there is no improvement in the precision of the output.
The seemingly unexpected result in Fig. 6 can be resolved and deciphered as follows.The sampling rate at the output of the counter is inversely proportional to the gate time, with the counter producing a measurement for every k periods of the input signal.When AD is computed based on this sampled frequency data for the smallest τ of k periods, the only averaging in the sense of (9) reflected in the data is the one that is inherently performed by the counter front-end, with no additional averaging in the actual AD computation as discussed before.This means that the AD computed as such is actually a characterization of the frequency fluctuations of the counter input signal, as opposed to the conceptually synthesized signal based on the counter output.Thus, it makes perfect sense that computed ADs for varying k fall exactly on top of each other, since they all represent a characterization of the input signal, not the counter output.Another perspective on the seemingly puzzling results in Fig. 6 is as follows.With increased gate time, the sampling rate at the output of the counter is not large enough to justify the use of the frequency data to compute the AD (for the counter output) with (8), since (10) does not hold in this case, and the additional averaging that needs to be part of the AD computation is missing.
While we resolved the results in Fig. 6 based on theoretical arguments, it is desirable to experimentally observe the precision improvement one can obtain in an FC by increasing the gate time.This requires somehow increasing the sampling rate at the counter output.With a gate time of k input periods, one can attain a k-fold increased sampling rate by employing a sequence of k parallel counter front-ends, where each front-end counts over k periods of the input signal, but with one period delay relative to the previous one in an interleaved manner.However, this would increase the hardware cost and complexity considerably.Instead, we simply emulate k parallel counter front-ends by first producing output from the counter with k = 1 for every period of the signal, and then processing this output with an MAVGF with a window length of k.Apart from a larger latency at the output, this emulation is hardware-equivalent to having k parallel counter front-ends and does not involve any approximations.One can obtain the frequency data at the k-fold lower sampling rate (output of only one of the k front-ends, used to generate Fig. 6) by simply downsampling the MAVGF output with a downsampling ratio of k.
The ADs computed from the raw counter output with k = 1, the MAVGF output with k = 121, the downsampled moving average output, as well as LPF processed versions of the moving average output and its downsampled version, are shown in Fig. 7.As expected, we observe the perfect coincidence of the AD curve for the downsampled moving average output with the curve for the raw counter output.We now also observe the theoretically claimed precision improvement at the counter output with increased gate time (emulated with the moving average output) even when there is no extra lowpass filtering.With increased sampling rate, computation of AD with ( 8) is justified since (10) now holds.The additional averaging required in AD computation for τ values larger than the sampling interval is performed using the data samples available at the higher rate.
Further, low-pass filtering the downsampled moving average output results in a precision improvement as indicated by Fig. 7, but not as much as the one we observe for the moving average output at the higher sampling rate and its filtered version.On the other hand, it seems strange that the moving average output has higher precision when compared with its downsampled version.In the end, specific frequency measurement values in the downsampled data are exactly equal to a subset of the values in the higher rate data, and therefore should have the same precision.In fact, use of AD in order to characterize the precision of the downsampled data is not appropriate since (10) does not hold.However, one can simply compute the standard deviation of the downsampled data, which is in fact equal to the standard deviation of the higher-rate date assuming statistical stationarity.Any DSP with memory, that involves dynamics over time (including AD computation), on the downsampled data is not meaningful, and introduces aliasing and noise folding due to the low sampling rate.When gate time is set to the lowest value, the input signal period with k = 1, the counter front-end averages over the signal period T s , which is also set to the sampling interval at the counter output.Therefore, a front-end bandpass filter with a maximum bandwidth set to half the signal frequency is needed to prevent aliasing and noise folding, even when k = 1.
We thus conclude that, even though gate time can be used as a control knob for trading off precision versus response speed when an FC is used as a frequency shift monitor, it is better to set the gate time to the smallest value with ADs showing that resampling and filtering the signal at a fixed sampling rate achieve the same performance, whereas the event-triggered timestamp method results in a degradation.(Raw: no filtering; LPF: low-pass filter.)k = 1 and generate output at the largest rate possible, with an appropriate front-end bandpass filter to prevent aliasing.Then, instead of emulating a larger gate time with a simple MAVGF (a specific type of FIR filter), it is better to use an appropriate, bandwidth adjustable FIR or IIR digital filter that can offer a better precision versus speed trade-off.For the results we present in this work, we used a first-order IIR LPF.

C. Resampling for a Fixed Sampling Rate
In the third experiment, we consider resampling of the FC output, which has an input-dependent sampling rate, to a fixed sampling frequency.We compare filtering of the raw output and the resampled version.We also compare our proposed resampling technique with the continuous event-triggered timestamp method described in [5].
We consider and compute six versions of the frequency data as follows.
1) The raw main counter output (for k = 1) with an input-dependent sampling rate is generated.2) The raw output is passed through a first-order Butterworth LPF with a cut-off frequency of 200 Hz.
3) The raw output is processed using the event-triggered timestamp method with T int = 100 µs.4) The output processed with the event-triggered timestamp method is also passed through the LPF.5) The raw output is first processed with a zero-order hold to increase the sampling frequency to the frequency f CLK = 76.92MHz of the internal clock.Subsequently, it is decimated using a CIC decimator with a decimation factor of R = 8192, resulting in a final sampling rate of 9.4 kHz.6) The resampled data is passed through the LPF.We note that the digital LPF is implemented at the respective Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.sampling rate of the data it is applied to, corresponding to the same cut-off frequency in each case.The ADs for the six versions of frequency data described above are shown in Fig. 8.The event-triggered timestamp method produces an uncertainty in the sampling instants up to one period of the input signal, which manifests itself in the form of additional frequency noise resulting in a larger AD, discernible in Fig. 8 right before thermal drift kicks in.The additional frequency noise produced by this technique, which cannot be suppressed, is even more noticeable after the data is processed with the LPF.On the other hand, the data produced by our proposed resampling technique exhibits a slightly improved AD compared to the raw main counter output.This improvement can be attributed to the inherent low-pass filtering performed by the CIC decimator.Furthermore, if the resampled signal is further processed with an LPF, the AD obtained is identical to that when the raw counter output is low-pass filtered with the same cut-off frequency.

D. Proposed FC Versus PLLFD
In the final experiment, we compare the proposed FC with a commercial, lock-in-based PLLFD.The PID coefficients of the PLLFD are generated by the software that comes with the equipment, targeting a loop bandwidth of 200 Hz, resulting in the values k p = 2.92 and k i = 13.34Hz/deg/sec.The LPF in the PLL demodulator is a first-order filter with a cut-off frequency of 1 kHz, and the PLL operates at a sampling rate of 27 kHz.The transduced NEMS output after the preamplifier is fed to the PLLFD, whereas it is processed with a bandpass filter (with a bandwidth of 5 kHz) to produce the input for the FC.The FC raw output (with k = 1) is processed with a CIC decimator with a decimation factor of R = 8192, resulting in a final sampling rate of 9.4 kHz.The output of the decimator is processed with a LPF with a cut-off frequency of 200 Hz.Fig. 9 illustrates the comparison between the state-of-theart PLLFD method for frequency tracking and the proposed FC-based technique.It can be observed that both methods exhibit almost the same performance in both measurement and theory.

V. CONCLUSION
In this study, we investigated various aspects of frequency shift monitoring mechanisms based on FCs for resonant sensors.We characterized their precision, both in theory and experimentally, in the presence of thermomechanical and detection noise.Through theoretical models, analyses, and articulate arguments, combined with a series of experiments and elucidated results, we have gained valuable insights into various scenarios, system architecture and parameter choices.
We proposed a novel and cost-effective FC-based frequency shift monitoring scheme, which was overlooked in the NEMS literature.Our FC-based architecture features wide bandpass filtering for signal conditioning combined with digital low-pass filtering in the sampled data domain before timestamp series for the signal transitions are converted to frequency data.This architecture not only alleviates the detrimental effect of intermodulation noise generated by the nonlinearity of time-to-frequency conversion, but also enables a flexible and practical platform for real-world applications where all DSP is performed at a fixed, input-independent sampling rate.
We investigated mechanisms for trading-off response speed versus precision in our proposed FC-based scheme.Although we have shown that the gate time of a counter can be used as a control knob for this purpose, it is more effective and efficient if the gate time is set to the smallest possible value, i.e., the cycle time of the input signal, to generate an output at the largest sampling rate possible.Then, speed versus precision trade-off can be conveniently achieved by modifying the digital filtering characteristics in a more flexible manner.
The output of a standard reciprocal counter, where gate time is set to the cycle time of the input signal, has an input-dependent sampling rate.This is inconvenient for the subsequent DSP.We developed a resampling scheme that involves a zero-order hold and a CIC decimator to convert the output to a fixed, input-independent sampling rate.We have shown experimentally that the resampled and filtered output has the same (or slightly better) precision as the filtered raw output of the FC as characterized by ADs.
Finally, we compared the precision of the proposed FC-based scheme with a commercial implementation of the common and standard PLLFD technique in terms of ADs.Our results showed that both methods achieve the same performance, indicating that the proposed FC-based frequency tracking method can serve as a viable and cost-effective alternative to the state-of-the-art PLLFD method.
Overall, our experimental results, theoretical models, analyses, and findings contribute to a better understanding of frequency detection mechanisms.This understanding combined with our FPGA-based flexible and cost-effective platform paves the way to developing new frequency shift Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
monitoring schemes with enhanced precision, response speed, and/or reliability.
Looking forward, the insights gained from our study open up several avenues for further research and development in the field of precision frequency measurement for sensing applications.There is potential for advancing the DSP techniques used in our architecture.Machine learning-aided algorithms, for instance, could be employed to dynamically optimize and adapt filtering parameters in real time, potentially leading to even more precise and responsive frequency tracking.Our research lays the groundwork for exciting developments, and we anticipate that the concepts and techniques presented in this work will contribute to innovations in sensors based on frequency shift monitoring in the near future.

Fig. 1 .
Fig. 1.(a) Block diagram of the second-order CIC decimator with the decimation factor R and the comb section delay N. (b) Transfer function of the decimated output.

Fig. 2 .
Fig. 2. (a) Picture of the NEMS resonator used in the experiments and its connection to the setup.(b) Block representation of the SSO tracking scheme with the FC and the PLLFD.

Fig. 3 .
Fig. 3. Block diagram of the proposed FC architecture, where s in is the input signal, f is the frequency output.

Fig. 4 .
Fig. 4.Time-domain steady-state measurements acquired by the main counter (with interpolator block), using two different bandpass filter bandwidths: 20 and 5 kHz.

Fig. 7 .
Fig. 7. Measurement-based model of the FC acquisition mechanism emulating a large gate time with k = 121 by applying an MAVGF to data acquired with k = 1 and downsampling, with comparison of low-pass filtering at different stages.(Raw: no filtering; MAVGF: moving average filter; LPF: low-pass filter.)

Fig. 8 .
Fig. 8.ADs showing that resampling and filtering the signal at a fixed sampling rate achieve the same performance, whereas the event-triggered timestamp method results in a degradation.(Raw: no filtering; LPF: low-pass filter.)

Fig. 9 .
Fig.9.ADs of raw (unfiltered) and low-pass filtered FC output in comparison with a PLLFD with the same bandwidth.Results show that there is no difference in performance between a commercial PLLFD with the FC proposed in this work.