1.2–2.8-GHz 32.4-dBm Digital Power Amplifier With Balance-Compensated Matching Network

In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2–2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. It supports 50-MHz 64-quadratic-amplitude modulation (QAM) with average output power (<inline-formula> <tex-math notation="LaTeX">$P_{\text {avg}}$ </tex-math></inline-formula>) of 25.37 dBm, error vector magnitude (EVM) of −26.97 dB, adjacent channel power ratio (ACPR) of −29.61 dBc, and 10-MHz 1024-QAM with <inline-formula> <tex-math notation="LaTeX">$P_{\text {avg}}$ </tex-math></inline-formula> of 22.14 dBm, EVM of −35.75 dB, and ACPR of −35.37 dBc, respectively.


I. INTRODUCTION
With the development of wireless communication, power amplifiers (PAs) with high-power, energy efficient, low supply, and low cost are highly demanded.CMOS analog PAs with high power and linearity is highly developed.However, the system efficiency is relatively low due to extra modules.Digital PAs (DPAs) exhibit enhanced efficiency and medium output power.A watt-level CMOS DPAs with merits of wideband, high efficiency, low supply, and compact size still remain great challenges.In this letter, a 1.2-2.8GHz watt-level DPA with balance compensated matching network is proposed.Such matching topology is consisted of a 4-to-1 transformer with a compensated series-loaded capacitor.A prototype DPA is implemented and fabricated using a conventional 40-nm CMOS technology, which exhibits 32.4 dBm peak output power and 53.8% peak drain efficiency (DE) under a 1.1/2.5Vsupply.

II. CIRCUIT DESIGN
The block diagram of the proposed wideband watt-level DPA based on a balance compensated matching network is shown in Fig. 1.A 4-way series combining architecture is adopted.Each switch array consists of 6-bit unary MSB cells and 4-bit binary LSB cells with cascode 2.5 V thick-oxide transistors, 2.5 V digital AND gates and buffers.Meanwhile, the matching network performs the 4-way power combining, differential to single conversion, wideband impedance matching, and balance compensation, simultaneously.Besides, two sets of parallel high speed 5:1 deserializer and encoder are used to convert the serial baseband signals to thermometer and binary codes.

A. Matching Network with 4-to-1 Transformer
Higher output power can be achieved with increased drain current, i.e., smaller Z in of the transformer once the voltage swing remains the same.Such operation leads to a larger inductance ratio of the transformer.However, such ratio is limited due to the Q degradation.In the proposed DPA, series power combining scheme is used.In this way, the inductance ratio is reduced and lower passive loss is achieved.

B. Imbalance Compensation Technique
The simplified circuits of 4-way power combiners are depicted in Fig. 2    the entire secondary coil, which leads to enhanced impedance balance.And thus, the compensated transformer is capable of higher efficiency and power.

III. RESULT
The proposed watt-level wideband DPA fabricated using a conventional 40-nm CMOS technology.The photograph is in Fig. 3.The chip size and core size are 2.3 mm × 1.26 mm and 1.34 mm × 0.84 mm, respectively.The supply is 1.1/2.5V.
The measured results of output power, DE, and power added efficiency (PAE) are depicted in Fig. 4.Meanwhile, the peak output power, DE, and PAE are 32.4 dBm, 53.8%, and 43.8%, respectively.As shown in Fig. 5, the 10 MHz 1024-QAM signal with EVM of -35.75 dB is achieved at 2 GHz, Table I shows the comparison with state-of-the-art high-power DPAs.

IV. CONCLUSION
In this letter, a wideband watt-level high efficiency DPA based on balance compensated matching network is proposed.To achieve high output power with a compact size, the 4-to-1 combining transformer is introduced.Meanwhile, to decrease the imbalance, the imbalance compensation capacitor is utilized.The proposed DPA fabricated in 40-nm CMOS technology shows the merits of watt-level output power, high efficiency, and wide bandwidth.
V. ACKNOWLEDGMENT AND NEXT PLAN I would like to thank my supervisor Associate Professor Huizhen Jenny Qian for her guidance on radio-frequency integrated circuits (RFIC) design.I am also extremely grateful to IEEE and MTT-S for encouraging me to take up this research.With the support of the funding and my supervisor Associate Professor Huizhen Jenny Qian, I have published one MWCL paper [5].I will continue to study in this field to become an excellent RFIC designer and make more progress in excellent and efficient communication for human being.
(a)  and (b).A compensation capacitor C bc marked in red is introduced, as shown in Fig.2(b).Compared with transformer without compensation in Fig.2(a), it is notable that Fig.2(b) exhibits uniform current distribution for