Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS

Analog and RF mixed-signal cryogenic-CMOS circuits with ultrahigh gain-bandwidth product can address a range of applications such as interface circuits between superconducting (SC) single-ﬂux quantum (SFQ) logic and cryo-dynamic random-access memory (DRAM), circuits for sensing and controlling qubits faster than their decoherence time for at-scale quantum processor. In this work, we evaluate RF performance of 18 nm gate length ( L G ) fully depleted silicon-on-insulator (FDSOI) NMOS and PMOS from 300 to 5.5 K operating temperature. We experimentally demonstrate extrapolated peak unity current-gain cutoff frequency ( f T ) of 495/337 GHz (1.35 × /1.25 × gain over 300 K) and peak maximum oscillation frequency ( f MAX ) of 497/372 GHz (1.3 × gain) for NMOS/PMOS, respectively, at 5.5 K. A small-signal equivalent model is developed to enable design-space exploration of RF circuits at cryogenic temperature and identify the temperature-dependent and temperature-invariant components of the extrinsic and the intrinsic FET. Finally, performance benchmarking reveals that 22 nm FDSOI cryogenic RF CMOS provides a viable option for achieving superior analog performance with giga-scale transistor integration density.


I. INTRODUCTION
C RYOGENIC superconducting (SC) digital processors operating at 4 K, employing Josephson junctions (JJs) for single flux quantum (SFQ) logic, offer the promise of greatly reduced operating power for high-performance cloud computing systems due to the exceptionally low energy per operation of SFQ circuits [1].This allows a significant reduction in overall energy delay product and hence has led to renewed interest in SC computing with SFQ.It is equally important to complement SC logic technologies with a compatible high-bandwidth, low latency memory technology colocated in the same 4 K temperature plane.For instance, the operation of a 1.3 GHz embedded cryo-dynamic randomaccess memory (DRAM) macro with a 2T-gain-cell was demonstrated at 4 K as an option for ultrahigh density cryomemory sub-system for SFQ logic processors [2].Integration of cryogenic-DRAM in the same thermal plane as the JJ SC logic shortens the interconnect length and improves data access latency.Reduced sub-threshold leakage through the DRAM access transistor at cryogenic temperature was harnessed to enable 10 6  × higher retention time and consequently lower refresh power [2].Memory capacity of cryogenic-DRAM can further be increased by designing the DRAM memory cell at denser CMOS nodes.Interfacing cryogenic DRAM with SC logic still remains a technology challenge.For instance, SFQ logic operates with 2 mV amplitude pulses with picosecond duration which implements input and output circuits challenges.Also, JJs by themselves cannot directly drive bit/wordline or CMOS sense amplifiers in DRAM arrays, which operate at 0.8 to 1 V supply.In this context, multistage signal booster and level translator circuits with high gain (400 V/V) and GHz bandwidth, are required to interface SC circuits with cryo-DRAM memory.Furthermore, cryogenic-CMOS based analog and mixedsignal interface systems have been proposed for control and read out of qubits in a large-scale quantum computer [3].Placing the cryo-CMOS control electronics in close physical proximity to the quantum processor can provide significant benefits in terms of system scalability and low latency [4].As the cryogenic qubit controller requires generation and acquisition of GHz range signals with low power dissipation and high immunity to noise [5], design-space exploration of cryogenic RF circuits is required to ensure strict power budgets along with superior analog and RF performance.
The ultra-thin body and buried-oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) CMOS platform is a potential platform for both of the above-mentioned cryogenic RF applications, due to high transistor density, low power dissipation, and reduced parasitic and optimized RF performance [6], [7].Commercially available FDSOI CMOS technologies (22 and 28 nm node) have been investigated in detail down to 4.2 K, along with self-heating effects [8] and device variability [9].However, these studies mainly evaluated the temperature dependence of MOSFET dc parameters, like threshold voltage, sub-threshold swing, transconductance, and drive-current.RF performance of both FDSOI NMOS and PMOS has not been yet studied in detail and quantified at a deep cryogenic temperature [10].In addition, smallsignal circuit models for cryogenic FDSOI are also essential to develop a reliable RF circuit design toolkit, which is still not in existence for 22 nm cryogenic FDSOI technology [11].
This work presents a detailed description and analysis of RF performance gain in 22 nm FDSOI technology at cryogenic temperature, as demonstrated in our previous work [12].In this article, we investigate RF performance Si NMOS and SiGe PMOS [6] FETs at cryogenic temperature on Globalfoundries 22 nm FDX CMOS platform.Electrical dc and RF characterization of 22 nm FDSOI FETs were performed from 300 K down to 5.5 K. RF FoM such as transistor cut-off frequency (f T ) and maximum oscillation frequency (f MAX ) were extracted as a function of drain current (I DS ) bias and operating temperature.A small-signal equivalent circuit of MOSFET [13] was utilized to model the RF response of FDSOI FET from 300 to 5.5 K. Temperature variation of the small-signal equivalent model parameters was used to identify the temperature-dependent and temperatureinvariant FET parameters that set the limit of cryogenic RF performance.Finally, the performance of 22 nm FDSOI FETs at cryogenic temperature is benchmarked against other advanced node cryogenic CMOS technologies.

II. DEVICE DESCRIPTION AND EXPERIMENTAL DETAILS
Commercially available 22 nm FDSOI CMOS technology provides Si channel nFET and SiGe channel (with Ge content around 25%) pFET fabricated with gate-first high-k metal gate process [6].Fig. 1 shows xTEM of 22 nm FDSOI Fig. 1(a) and (c) nFET and Fig. 1(b) and (d) pFET, respec-tively.The thickness of the un-doped ultra-thin semiconductor channel is about 6 nm, while the buried oxide is 25 nm thick.Capacitance equivalent thickness (CET) of the high-k gate-stack was found to be 1.3 nm.In this work, experimental measurements were performed down to 5.5 K using Lakeshore CPX-VF cryogenic probe station.Cryogenic dc characterization was performed using a Keithley 4200 SCS parameter analyzer, whereas the RF measurement setup consists of ground-signal-ground (GSG) probes with 50 µm pitch and an 8722D vector network analyzer.S-parameters are measured from 300 to 5.5 K, on 18 and 28 nm LG FETs with 16 gate-fingers of 0.5 µm width each, over 0.5-35 GHz frequency range, under cold-FET (VDS = 0 V, |VGS| = 0, 0.2 V) and saturation (|VDS| = 1.0 V, |VGS| = 0.0-1.2V) bias conditions.S-parameters of the ON-chip open and short structures are also measured for all temperatures.A two-step de-embedding method using the ON-chip open and short structures, as described in [14], has been followed to correct for the interconnect-line and access parasitic embedded in the test structure.S-parameters measured on the open structure were converted to Y parameters (Y Open ); this provides the parallel-connected pad and interconnect parasitic.Similarly, the S-parameters of the short structure were measured and converted to Y parameters (Y Short ).The series components of the interconnect parasitic were then obtained from the open and short measurements by Z Series = (Y Short − Y Open ) −1 , as described in [14].Finally, the transistor Y-parameters were obtained by measuring the transistor S-parameters, converting them to Z-parameters (Z DUT ), and sequentially de-embedding both series and parallel parasitic, using where, Z DUT is the Z-parameter representation of the measured device.These de-embedded transistor Y-parameters were then used to extract the RF FoMs of the transistor, such as f T and f MAX .
Pad and access parasitic de-embedded S-parameters were then used to extract the RF FoMs of the transistor, such as f T and f MAX .Subsequently, ''cold'' FET measurement at V GS = 0 V was employed for both gate length structures to further de-embed the effect of extrinsic FET resistances [15].Extrinsic FET capacitances were also de-embedded using the ''cold'' FET measurements in accumulation condition (at V GS = −0.2/+0.2V for nFET/pFET), as explained in [15].Finally, access and extrinsic FET parasitic de-embedded S-parameters were used to extract the intrinsic FET parameters at each bias point from the measurements in saturation condition.

A. CRYOGENIC DC CHARACTERIZATION OF 22 nm FDSOI
The well-tempered transfer characteristics (I D -V GS ) of 18 nm gate length (L g ) nFET and pFET from 300 K down to 5.5 K, are shown in Fig. 2  saturation region (V DS = 1 V), respectively.The output characteristics with excellent saturation behavior [see Fig. 2(c)] shows drain current (I DS ) improvement of 37% for nFET and 60% for pFET under iso-gate overdrive (|V GS − V T ,Lin | = 1 V) at 5.5 K compared to 300 K.The linear (V TH,Lin ) and saturation (V TH,sat ) region threshold voltage increase at cryogenic temperature for both nFET and pFET [see Fig. 3(a) and (b)], due to the increase in the Fermipotential at lower temperature [16].V TH,Lin shift in SiGe pFET (160 mV) was found to be more compared to Si nFET (122.5 mV) at 5.5 K.However, the FD-SOI technology harnesses the back-gate biasing capability even at cryogenic temperature, which can be exploited to re-target the V TH at low temperature.Fig. 3(c) shows the V T tuning capability of the n-FDSOI MOSFET at different temperatures.Backbias voltage (V B ) of +2 V is required to re-target the V TH at 5.5 K to that at 300 K for 18 nm NMOS FDSOI FETs.Interestingly, the back-biasing efficiency (γ = V T / V B ) of n-FDSOI FETs was found to be constant across temperature (γ = −80 mV/V).This indicates the highly doped p-well substrate does not undergo dopant freeze-out even at 5.5 K. Subthreshold slope (SS), on the other hand, improves for both the NMOS and PMOS down to cryogenic temperature [see Fig. 3(d)].However, SS does not scale linearly with temperature below 70 K and saturate around 20 mV/dec.This can be attributed to the location of the Fermi-level close to the high interface trap density (D it ) region, as well as a sharp change in Fermi occupation function at cryogenic temperature, both leading to higher interface trap response capacitance (C it ) [17].This results in a sharp rise in the n-factor (n = SS Experimental /SS Ideal ) below 70 K with an inverse temperature dependence (T −1 ), as shown in the inset of Fig. 3(d).The transconductance in the saturation region (g m,sat ) is plotted as a function of the gate length (L G ), in Fig. 3(e) and (f) for nFET and pFET, respectively.g m,sat scales as L −0.3 G for both deeply scaled (L G < 50 nm) nFET and pFET across all temperatures.Improvement in g m,sat was found to be 33%/25% for nFET/pFET from 300 to 5.5 K, across all channel lengths, due to reduced phonon scattering and improved source/drain contact resistance [12].However, boost in g m,sat is saturated below 150 K as carrier transport is dominated by temperature invariant surface roughness (SR) scattering.Also, it should be noted that, g m,sat in nFET FDSOI was found to saturate below 28 nm gate length, whereas it continues to improve with L G scaling in pFET FDSOI.This can be possibly due to the fact that g m,sat at scaled gate length nFET is still dominated by the n+ Si source/drain contact resistance.However, this is not the case for Si-Ge channel PMOS since the source/drain contact resistance of p+ SiGe is lower compared to NMOS.

B. CRYOGENIC RF CHARACTERIZATION OF 22 nm FDSOI
Cryogenic RF characterization of 22 nm FDSOI technology involves extraction of two main RF FoMs as a function of drain current bias and operating temperature, namely transistor cut-off frequency (f T ) and maximum oscillation frequency (f MAX ).In order to extract f T and f MAX , access parasitic de-embedded S-parameters were used to calculate short-circuit current gain (H 21 ) and Mason's unilateral power gain (U), as mentioned in [10].f T was calculated through −20 dB/dec extrapolation of H 21 to unity gain (|H 21 | = 0 dB), over a frequency range of 1-20 GHz.Fig. 4 shows the measured |H 21 | (symbols), under peak-g m gate bias and |V DS | = 1 V, along with −20 dB extrapolation (line) for NMOS (red) and PMOS (blue) at 300, 70, and 5.5 K in Fig. 4(a)-(c), respectively.A similar method was followed to extrapolate f T as a function of drain-current bias.Fig. 5(a) and (b) plot the drain-current dependence of extrapolated f T for different temperatures ranging from 300 to 5.5 K for NMOS and PMOS, respectively.Extrapolated peak-f T as a function of temperature shows an improvement of 35% from 367 GHz at 300 K to 494 GHz at 5.5 K for NMOS and 25% from 268 GHz at 300 K to 337 GHz at 5.5 K for PMOS, as shown in Fig. 5(c   Fig. 7(a)] and PMOS [see Fig. 7(b)].Extrapolated peak-f MAX was found to improve by 30% for both NMOS (from 373 GHz at 300 K to 497 GHz at 5.5 K) and PMOS (from 288 GHz at 300 K to 372 GHz at 5.5 K), as shown in Fig. 7(c).Accuracy of the de-embedding method used in this work is validated by the excellent agreement of extrapolated f T and f MAX at 300 K with reported values for 22 nm FDSOI FETs (nFET/pFET f T 350/244 GHz, nFET/pFET f MAX 370/277 GHz) [18].
It should be noted that drain current densities (I DS /W ) corresponding to both extrapolated peak-f T and peak-f MAX are invariant of temperature.

C. SMALL-SIGNAL CIRCUIT MODEL FOR CRYOGENIC FDSOI
A small-signal equivalent circuit model was used to capture the cryogenic RF performance of 18 and 28 nm L G FETs   S-parameters for 18 nm L G NMOS and PMOS show excellent agreement across the entire temperature range, as highlighted in Fig. 9(a)-(f).The access capacitance and inductance elements were found to be temperature invariant, whereas interconnect-line resistance was reduced at low temperatures.However, due to infinitesimally low value (<3 ), these parameters were not found to have a significant effect on the measured S-parameters across temperatures.
Small-signal equivalent model parameters for 18 nm L G n and p FDSOI at 300, 70, and 5.5 K are listed in Table 1.Fig. 10 summarizes the temperature and gate length dependence of small-signal equivalent model parameters.The intrinsic g m improves by 39%/28% for NMOS/PMOS due to reduced phonon scattering at low temperature [19], as shown in Fig. 10(a).However, SR scattering slows the rate of improvement in g m,int below 150 K, which is also consistent with the cryogenic measurement result.Source-drain series resistance (R se , R de ) are found to be invariant of gate length and improves by 11%/12% for NMOS/PMOS at low temperature due to reduced sheet resistivity of source/drain extension [20], but saturates below 100 K [see Fig. 10(b)].Simultaneous improvement in g m,int and R se , R de contributes to the observed boost in f T .C gg,i scales with gate length whereas C gg,e has no gate length dependence [see Fig. 10(c) and (d)].Both the intrinsic and extrinsic gate capacitances (C gg,i and C gg,e respectively) remain almost invariant with temperature for NMOS and PMOS, whereas the gate-resistance (R ge ) decreases monotonically by 32%/24% for NMOS/PMOS [see Fig. 10(e)] due to reduced resistivity of gate metal contact (NiSi) and poly-Si at a cryogenic temperature [21].The combined effect of improvement in f T and R ge explains the improvement in f MAX at low temperature.Output conductance (g o ) however increases at low temperature [see Fig. 10(f)], due to slightly degraded short channel effect (SCE) likely from partial channel dopant de-activation in the channel.
However, small-signal equivalent circuit model parameters for cryogenic-RF FDSOI were extracted with reference to the M1 (metal 1) plane.Hence, it should be noted that effective values of the model parameters and also extracted f T /f MAX may vary depending on the connection of the extrinsic transistor to different metal layers present in an actual circuit.Cryogenic characterization and circuit model implementation of different interconnect layers is hence required to allow the accurate design of cryogenic-RF CMOS.Also, intrinsic transconductance (g m,i ) in this work has been considered as a real number.However, a phase factor associated with g m,i can also be included for capturing the non-quasi-static response of the small-signal equivalent circuit model [22], in order to allow operation at higher frequencies (>100 GHz).

D. DELAY-TIME ANALYSIS OF CRYOGENIC-RF FDSOI
A delay-time analysis is performed to identify the contribution of different delay subcomponents on f T improvement at 22 nm FDSOI FETs at cryogenic temperature [23].The analytical expression of f T can be obtained from the small-signal The total delay (τ Delay = 1/2π f T ) can hence be partitioned into four components, such as intrinsic transit time (τ t ), extrinsic charging delay (τ ext ), parasitic delay (τ par ), and delay due to short-channel effect (τ SCE ) where, τ t = (C gg,i /g m,i ), τ ext = (C gg,e /g m,i ), τ par = R sd,e • C gd,e , and τ SCE = (R sd,e • (C gg,Ts ) • g o /g m,i ).
Transit time (τ t ) can be calculated as the ratio of channel length (L Ch ) and average velocity of carriers (v Avg ) in the channel.Hence, the observed improvement in transit time can be attributed to enhanced average carrier velocity at cryogenic temperature for both NMOS and PMOS [24].Fig. 11(c) summarizes the enhancement in v Avg due to faster electron and hole transport in n and p-MOSFETs (L G 18 and 28 nm), respectively.Improvement in g m,int enables a reduction in τ ext as C gg,e remains invariant with temperature.τ par also scales with temperature due to reduced R se , R de .Moreover, τ SCE improves down to 70 K due to improved g m,int but slightly degrades at lower temperature as g o also increases.Hence reducing the extrinsic device parasitic capacitance (low-k spacer), reducing source/drain series resistance, and  improving SCE through thinner body, scaled equivalent oxide thickness (EOT) are potential pathways to further improve the RF performance of 22 nm FDSOI technology at cryogenic temperature.

IV. CONCLUSION
In this work, we demonstrate record RF FoMs such as f T of 495/337 GHz and f MAX of 497/372 GHz for NMOS/PMOS at 5.5 K, on 22 nm FDSOI platform.This improvement is attributed to a 39%/28% boost in intrinsic g m as well as 11%/12% lower source-drain external series resistance (R se , R de ) and 32%/24% lower gate resistance (R ge ) for NMOS/PMOS at cryogenic temperature.Output conductance increased by 17% for both NMOS and PMOS at cryogenic temperature, with no significant effect on f T .Furthermore, the back-biasing capability of 22 nm FDSOI technology can be utilized for V TH tunability at cryogenic temperature.A small-signal equivalent circuit model was used to extract the temperature variation of intrinsic and extrinsic transistor parameters for 22 nm FDSOI technology down to deep-cryogenic temperature (5.5 K).This paves a pathway for design-space exploration of high gain-bandwidth mixed-signal circuits for cryogenic RF applications.Performance benchmarking of cryogenic CMOS technologies, as listed in Table 2, reveal that 22 nm cryogenic-RF FDSOI FETs showcased in this work provide superior f T , f MAX for both NMOS and PMOS, and hence are an excellent option for achieving superior analog performance with high transistor density at cryogenic temperature.

FIGURE 1 .
FIGURE 1. Schematic of device structure and xTEM image of regular-well 22 nm FDSOI for (a) and (c) Si nFET and (b) and (d) SiGe pFET respectively, as shown in [6].
(a) and (b) for linear (V DS = 50 mV) and

FIGURE 3 .
FIGURE 3. DC characterization of cryogenic FDSOI technology.Threshold voltage shift with temperature at |V DS | = 50 mV and |V DS | = 1 V for (a) nFET and (b) PMOS; (c) 200 mV negative shift in V TH can be obtained through back-bias at 5.5 K to match the same V TH at 300 K. (d) SS at |V DS | = 1 V for NMOS (blue) and PMOS (red), n-factor (n = SS/SS Ideal ) increase sharply with inverse temperature dependence at cryogenic regime (inset), due to high interface trap response capacitance (C it ); L G scaling trend of transconductance (g m,sat ) at different temperatures (300, 150, 70, and 5.5 K) show constant boost of 33% and 25% for (e) nFET and (f) pFET, respectively.

FIGURE 4 .
FIGURE 4. Extraction of f T from −20 dB/dec extrapolation of access/pad parasitic de-embedded short-circuit current gain (|H 21 |) to unity, under peak-g m gate bias and |V DS | = 1 V for 18 nm L G NMOS (red) and PMOS (blue) at (a) 300, (b) 70, and (c) 5.5 K.

FIGURE 5 .FIGURE 6 .
FIGURE 5. Drain-current (I DS /W ) dependence of extrapolated f T over the temperature range 300 to 5.5 K for 18 nm L G .(a) NMOS and (b) PMOS, under |V DS | = 1 V. (c) Extrapolated peak-f T as a function of temperature show boost of 35% (to 495 GHz) and 25% (to 337 GHz) at 5.5 K for NMOS and PMOS, respectively.

FIGURE 7 .
FIGURE 7. Drain-current (I DS ) bias dependence of extracted f MAX over the temperature range 300-5.5 K for 18 nm L G .(a) NMOS and (b) PMOS, under |V DS | = 1 V. (c) Peak f MAX as a function of temperature show f MAX boost of 30% to 497 and 372 GHz at 5.5 K for NMOS and PMOS, respectively.

FIGURE 8 .
FIGURE 8. (a) Different access and pad parasitic in RF test structure.(b) Schematic and (c) small-signal equivalent circuit model of 22 nm FDSOI FET with illustration of access/ interconnect parasitic, extrinsic, and intrinsic FET.

FIGURE 9 .
FIGURE 9. Modeled (solid line) S-parameters using small-signal equivalent circuit model show perfect agreement with measured S-parameters (symbol) from 0.5-35 GHz for 18 nm gate length n-FDSOI at (a) 300, (c) 70, and (e) 5.5 K and p-FDSOI at (b) 300, (d) 70, and (f) 5.5 K for V DS = 1.0 V and V GS at maximum g m .

FIGURE 10 .
FIGURE 10.(a) Intrinsic g m (g m,int ) improves at low temperature in NMOS and PMOS due to reduced phonon scattering.(b) Source/drain series resistance (R se , R de ) improve by 15% at 5.5 K. (c) Intrinsic (C gg,i ) and (d) extrinsic (C gg,e ) component of gate-capacitance (C gg,T = C gg,i + C gg,e ) remains invariant with temperature.(e) Reduced resistivity of gate metal contact (NiSi) and poly-Si cause gate resistance (R ge ) reduction at cryogenic temperature.(f) Channel conductance (g o ) increase by 25% at low temperature.

FIGURE 11 .
FIGURE 11.Delay-time analysis shows 38%/25% improvement in intrinsic transit time (τ t ) and 40%/27% improvement in external parasitic delay (τ ext ) at 5.5 K compared to 300 K for 18 nm L G (a) NMOS and (b) PMOS, respectively.(c) Improved transit time can be attributed to enhanced average electron and hole velocity at cryogenic temperature in NMOS and PMOS, respectively.equivalent circuit model as 2πf T = g m,i C gg,T + g m,i R sde C gdi + C gde + g o g m,i C gg,T.