Subthreshold Spintronic Stochastic Spiking Neural Networks With Probabilistic Hebbian Plasticity and Homeostasis

The neural sampling core (NSC) proposed herein offers a spintronic device-based circuit and learning mechanism utilizing imprecise and stochastic components, similar to biological brains, to realize ultralow-power neuromorphic computations at subthreshold voltages. Leveraging principles from neural sampling, a biologically plausible theory from computational neuroscience, a spintronic stochastic spiking neuron with digital Postsynaptic potentials is proposed in conjunction with low-precision spintronic synapses utilizing a new event-driven Probabilistic Hebbian Plasticity Rule, and a novel homeostasis mechanism that balances neural activity across multiple timescales and process variation effects. The primary computational operation, the summation of presynaptic potentials weighted by their corresponding synaptic efficacy and the neuron’s homeostatic parameters, is performed in a parallel analog fashion using noisy and imprecise subthreshold components. It is demonstrated herein that the NSC is capable of learning orientation selectivity, much like the simple cells found in the visual cortex, in an unsupervised fashion at 311 nW per neuron and 1.9–7.7 nW per active synapse using a 200-mV supply voltage.


I. INTRODUCTION
R ECENT research into spiking neural network (SNN)   hardware has aimed to achieve computational capabilities akin to biological brains, such as inference, at efficiencies unachievable with Von-Neumann hardware [1].Several custom SNN application-specified integrated circuits (ASICs), such as IBM's TrueNorth [2] and SpiNNaker [3], have demonstrated impressive capabilities at very low power using standard CMOS technology.Furthermore, much work is being done on developing neuromorphic hardware utilizing emerging nonvolatile devices, such as spintronics and memristors, implementing primarily synapses [4]- [12] but also neurons [8]- [13] in compact and energy-efficient designs when compared to CMOS-only approaches.
An intriguing observation is that biological brains and nanoscale electronic circuits share characteristics that can provide insights toward designing circuits and architectures that can be utilized for biologically inspired computation with potential power efficiency comparable to brains.First, the primary computational structures of biological brains, neurons and synapses, are highly heterogeneous and imprecise [14], [15], which is akin to the fact that all manufactured nanodevices have behavioral variability arising from process variation (PV), especially CMOS devices operating at subthreshold voltages [16].Perhaps by designing circuits and architectures that can adapt to, and even utilize, such heterogeneity while trying to aggressively lower supply voltages, even greater power efficiency could be achieved compared to adhering to the strict design margins and deterministic behaviors that VLSI circuits are typically designed to realize.Second, the fundamental mechanism underlying neural activity, ion channel opening and closing, is a stochastic process, which leads to stochasticity throughout neural activity [17].Coincidentally, a promising framework in computational neuroscience, neural sampling, has theoretically proven that a particular biologically plausible model of stochastically spiking neurons in cortical circuit motifs represent the samples from an underlying conditional distribution that can be used for probabilistic inference [18], [19].Therefore, leveraging heterogeneity and stochasticity in neuromorphic architectures using emerging devices that are intrinsically stochastic, such as spintronics [8], [9], [13], could lead to more capable and efficient neuromorphic hardware.
The neural sampling core (NSC) presented herein is motivated by the ultralow-power and robust characteristics of biological neural networks, which utilize stochastic and heterogeneous components with local learning rules in competitive networks.The NSC is a thrust to mimic the underlying computational principles of the brain in nanoelectronic circuits that can realize self-adaptive and low-power neuromorphic hardware with noisy and imprecise CMOS and spintronic devices operating at subthreshold voltages.
The following contributions are provided: 1) a stochastic spiking neuron circuit with protracted digital postsynaptic potentials realizing behaviors from neural sampling; 2) a low-precision hybrid spintronic-CMOS synapse circuit with a new event-based Probabilistic Hebbian Plasticity (PHP) unsupervised learning mechanism; 3) a novel homeostasis mechanism regulating neural activity across multiple time scales and PVs.The above contributions are integrated into a low-power neuromorphic hardware approach operating at subthreshold voltages, yet remaining robust to noisy and imprecise components.
The remainder of this paper is organized as follows.Section II delineates the requisite background information on spintronics, neuromorphic hardware, and neural sampling, which underlies the NSC approach.Section III presents the NSC and its associated circuits and algorithms.Section IV details the simulation results, analyzing the unsupervised learning capabilities, the power consumption of each circuit, and the effects of input noise.Section V concludes this paper and provides the future directions toward implementing and improving the NSC.The accompanying Supplementary Material details and justifies the modeling methodology, simulation framework, and provides the corresponding parameters that have been used.

A. SPINTRONICS
The field of spintronics aims to utilize the properties of nanoscaled magnetic structures to realize computational and nonvolatile memory elements [20]- [22].The most well-developed spintronic device is the magnetic tunnel junction (MTJ) shown in Fig. 1(a), which consists of a thin tunneling oxide, typically MgO, sandwiched between two magnetic layers [21].One magnetic layer is called the fixed layer, since its magnetic orientation remains unchanged during its operation, and the other is called the free layer, since its magnetic orientation is altered according to the physical behaviors underlying the device's switching mechanism.The most popular switching mechanism for MTJs is spin-transfer torque (STT), which works by passing a current of sufficient density and duration through the device [23].The state of the MTJ is represented by the resistance of the device, which changes based on the orientations of the free layer relative to the fixed layer.The antiparallel (AP) state results in a higher resistance than the parallel (P) state, and the relative resistance change between the two states is called the tunneling magnetoresistance ratio (TMR) [21].A relatively recent spintronic device, called the Spin-Hall effect MTJ (SHE-MTJ), improves several aspects of the standard two-terminal MTJ by placing a heavy metal, such as Pt or β-Ta underneath the free layer, which decouples the read and write paths as shown in Fig. 1(b) and can improve the energy efficiency of the write process if properly designed [24].For both the two-terminal MTJ and three-terminal SHE-MTJ, the switching process is a stochastic function of the current density and the pulse duration, whereby deterministic implementations require large current densities and pulse durations to ensure a very high probability of switching [25].Alternatively, several works, including herein, utilize the intrinsic stochastic switching behavior, which allows for much less current density to be used during the switching process, and thus, less power [8], [9], [26].A key parameter of spintronic devices is the energy barrier ( ), which is a function of the magnetic material properties and the shape of the device and it determines the retention time of the free layer and the current density needed to switch the device for a given pulse duration [9].When used as a memory element, MTJs and SHE-MTJs typically have ≥ 40k b T , where k b is Boltzmann's constant and T is the temperature in Kelvin.For 40k b T , thermal agitations can stochastically switch the device between parallel and AP states on timescales of seconds to picoseconds, which is practically unusable for the nonvolatile memory applications.However, recent work into probabilistic spintronic logic has demonstrated that very low spintronic devices are useful for realizing stochastic computations in compact circuits, which can be utilized for invertible logic and Boltzmann machines [27], restricted Boltzmann machines [28], and stochastically spiking neural circuits [13].One promising probabilistic spintronic device is the Embedded p-bit [29] shown in Fig. 1(c), which consists of an MTJ with a very low , an nMOS transistor, and a CMOS inverter.The input to the inverter is essentially a voltage divider between the stochastically switching MTJ and the nMOS, and therefore, the probability of the output of the inverter being high will have a sigmoidal behavior based on the input voltage to the nMOS.This behavior is demonstrated in greater detail in [29] and the Supplementary Material.
The integration of multiple technologies on a single chip will always increase integration complexity.However, it is understood that the energy barrier can be manipulated by adjusting the volume of the device as well as the in-plane dimensions for in-plane devices [30], [31].Thus, it is possible to integrate low-barrier and high-barrier devices on a chip by adjusting the length and width of the MTJs, which can be done on the same mask, adding a minimal increase in integration complexity.

B. NEURAL SAMPLING
Neural sampling is a theory of brain computation from computational neuroscience that interprets the stochastic spiking behavior of biological neurons as stochastic samples of underlying conditional distributions [18], [19].Particularly, it models the spiking behavior of neurons with an instantaneous stochastic spiking rate exponentially dependent upon the membrane potential, combined with a refractory period of duration τ and a commensurately prolonged rectangular postsynaptic potential (PSP), which approximates the PSPs found in vivo.Combined with a Hebbian learning rule, such a model can realize a generative model of the input distribution [19].This is, in contrast, to typical leaky integrate-and-fire (LIF) spiking neurons, which models spikes as impulses and neurons as a leaky integration of synaptically weighted presynaptic spikes that fires if a threshold is reached and then reset [26].For the rest of this paper, a spike means a rectangular pulse of τ clocks, as in neural sampling.Several cortically inspired circuit motifs have been developed utilizing neural sampling, which have demonstrated the impressive results of unsupervised and reward-based learning [19], [32].Thus, neural sampling provides a theoretically accomplished and biologically relevant framework for using stochastic neural models to achieve brainlike computations, and we provide a detailed connection to this work in the Supplementary Material.

C. STOCHASTIC NEUROMORPHIC HARDWARE
Several recent works have leveraged the stochastic switching properties of spintronic devices to realize unsupervised learning in SNN neuromorphic hardware as delineated in Table 1.The work developed by Zhang et al. [12] utilized multiple parallel MTJs to form a compound magnetoresistive synapse with a stochastic spike-timing-dependent plasticity (STDP) learning rule in conjunction with an MTJ-based stochastic spiking neuron to realize an SNN able to achieve respectable accuracies on MNIST data set.However, their work did not evaluate the power consumption of the design, which can be quite large for many parallel MTJs per synapse in a crossbar nor the effect of PV on the CMOS circuitry necessary for the neuron.
The long-term short-term stochastic synapse developed by Srinivasan et al. [26] utilizes two SHE-MTJs with distinct peripheral circuitry to realize various switching characteristics corresponding to different STDP sensitivities, enabling one SHE-MTJ to have sharper correlation sensitivity and greater synaptic strength than the other, which had moderate correlation sensitivity.They demonstrated that the scheme has faster training convergence, resulting in a reduction in total training energy consumption.However, the scheme was quite sensitive to STDP and circuit parameters and they did not analyze the effect of PVs.
The all-spin stochastic SNN developed in [8] leverages one-bit SHE-MTJ synapses with a stochastic-STDP learning rule and SHE-MTJ-based stochastic spiking neurons with a homeostasis mechanism to realize a low-energy SNN with online learning.However, the SHE-MTJ neuron requires write-read-reset cycling, which adds additional timing and energy overheads, the stochastic-STDP learning rule requires precision between the spike timing, switching probability, and write current, the homeostasis mechanism is rather coarse since it simply cuts off neurons that reach a certain spike count during learning, and the effect of PVs is not analyzed.
In addition, the spintronic stochastic spiking neurons in [8], [12], [30], [33] demonstrate the utilization of high-barrier spintronic devices for stochastic spike generation by applying an input current pulse, which may or may not have switched the device, then reading the state of the SHE-MTJ to determine if it spiked, then applying a strong reset pulse.This three-phase write-read-reset scheme requires additional timing and power overheads that are not experienced with low-barrier p-bits.The work in [30] also explored utilizing low-barrier telegraphic SHE-MTJs to implement stochastic spiking neurons without the write-readreset overheads, but their approach utilizes the direct output of an inverter without any event generation or synchronization mechanism, so it does not resemble spiking or PSP behavior, which can make it challenging for the event-based probabilistic Hebbian learning rules.
Thus, the NSC developed herein extends beyond these promising works by developing a robust subthreshold stochastic SNN approach utilizing a 3-bit hybrid spin-CMOS synapse with series and parallel SHE-MTJs, a flexible and adaptive homeostasis mechanism, and a p-bit stochastic spiking neuron with digital PSPs implementing neural sampling and enabling a simple and robust event-driven unsupervised learning mechanism, all developed and analyzed with the effect of PVs in both the spintronic and CMOS devices.

III. NEURAL SAMPLING CORE
This section delineates the constituent circuits of the NSC, such as the stochastically spiking neuron with a refractory period and prolonged digital PSPs congruent to those utilized in neural sampling's theoretical modeling, a three-bit synapse with the event-driven probabilistic Hebbian learning rules and a novel homeostasis mechanism.Since an important premise of this paper is that the NSC should be able to adapt and utilize the heterogeneity of components that emerges from PV, we model PV in both the spintronic and CMOS devices as described in the Supplementary Material at all stages of development and analysis.This section is organized by first detailing the operational principles of each circuit and then integrating them into a cohesive mixed-signal architecture with discussion.Although detailed later, it is worth mentioning here that there are two reciprocating phases based on the state of the clock; the read-phase occurs when the clock is low and the update-phase occurs when the clock is high.

A. STOCHASTIC SPIKING NEURON
The stochastic spiking neuron circuit shown in Fig. 2(a) consists of an embedded p-bit and a digital PSP circuit that operates as follows.Based on the voltage applied to IN and the state of the stochastically switching MTJ in the embedded p-bit, p-bit OUT will either be high or low.If p-bit OUT is high at the positive edge of a 100-MHz CLK, then the output of the PSP circuit, Neuron OUT , will go high and hold it for eight clocks, which corresponds to a τ of eight clocks.The waveform shown in Fig. 2(b) is an illustrative snapshot that shows the relevant circuit signals obtained from SPICE simulations for the parameters given in the Supplementary Material.A more detailed analysis of the sigmoidal probabilistic circuit behavior with PV is also detailed in the Supplementary Material.

B. HYBRID SYNAPSE WITH PROBABILISTIC HEBBIAN PLASTICITY
The hybrid spintronic-CMOS synapse shown in Fig. 3 and the PHP learning rule were codesigned to take advantage of the prolonged PSP signals with the stochastic switching behavior of spintronic devices.After extensive investigations and examinations with alternative learning rules, PHP was found to yield the best results for circuits with PV as shown in Section IV.The circuit operates as follows.The synapse in Fig. 3 uses three SHE-MTJs (S1-S3) to store the synaptic weight, one pMOS transistor (M 1) that operates as a voltage-controlled current source since the circuit is at subthreshold and two nMOS transistors (M 2 − M 3) that are  used when updating the synapse.The circuit operates during the read phase as follows.If the presynaptic neuron is not active or has not spiked within the last τ clocks, then IN will be at VDD, N will be at VDD, and no current will flow through M 1 onto SUM.If the presynaptic neuron has spiked within the previous τ clocks, then IN will be at GND, causing a voltage divider between S1 and S2-S3, which determines the voltage at N , which then controls the current through M 1 into SUM.The synaptic weights determined by the P or AP states of S1-S3 are shown in Table 2 where W 0 < W 1 < W 2 ∼ W 3 < W 4 < W 5 and detailed in the Supplementary Material.It is also worth noting that this scheme can be amended to have a greater range of possible weight values by increasing the number of SHE-MTJs in series or parallel with S1-S3 for additional area overhead.
PHP modifies the synapses during the update phase in an event-driven fashion as follows.If the postsynaptic neuron, POST, has spiked during the previous τ clocks, then both M2 and M3 are turned on, allowing current to flow through the write paths of S1-S3 based on the voltages applied to PRE and IN.If the presynaptic neuron has spiked within the previous τ clocks as well, then the synapse will update according to a synaptic potentiation event, that is, different voltages will be applied to PRE and IN for a given pulse duration such that S1 has a probability of switching to its AP state and S2-S3 have a probability of switching to their parallel states, which all have the effect of lowering the voltage at N and increasing the current through M1 during the read phase.If the presynaptic neuron has not spiked within the previous τ clocks, then the synapse will update according to a synaptic depression event, that is, voltages will be applied to PRE and IN for a given pulse duration such that S1 has a probability of switching to its parallel state and S2-S3 have a probability of switching to their AP states, which all have the effect of increasing the voltage at N and decreasing the current through M1 during the read phase.Therefore, each time a postsynaptic neuron spikes, all associated synapses are probabilistically updated for τ clocks, and more coincident presynaptic spiking will have a higher chance of strengthening the synapse, whereas nonspiking presynaptic neurons will have a chance of being depressed.More details can be found in the Supplementary Material.

C. HOMEOSTASIS MECHANISM
The homeostasis mechanism, which acts to increase the activity of under active neurons and decrease the activity of over active neurons, is implemented with a number of the homeostatic synapses shown in Fig. 4 connected to the input of each neuron.The two homeostatic synapse designs shown in Fig. 4 utilize alternative mechanisms for implementing homeostasis on both fast and slow time scales, where S1 has a higher probability of switching compared to S2 and, therefore, adapts on a faster time scale.The positive-feedback effect of synaptic plasticity needs a fast homeostasis mechanism to balance network activity [34], [35] while a slower homeostasis mechanism is beneficial for balancing the neuron's excitability in the presence of its intrinsic heterogeneity arising from PV.Both of the designs operate similar to the regular synapse during the read phase as follows.During the read phase BOT is pulled to GND, causing a voltage divider between S1 and S2, which determines the voltage at N , which then determines the current through M1 into SUM.The weight values are akin to the regular synapses described previously in that if S1 is AP and/or S2 is P, then the homeostatic synapse has a higher effective weight than vice versa and is detailed in the Supplementary Material.
The two designs differ during the update phase as follows.The circuit shown in Fig. 4(a) requires S1 to have a lower than S2, which causes it to have a higher probability of switching for the same current and pulse duration.The circuit shown in Fig. 4(b) does not require S1 and S2 to have different s but requires more overhead with an additional nMOS and two horizontal wires to isolate the two devices during the update phase, allowing different voltages and/or pulse durations to switch the two devices with different probabilities such that S1 switches with a higher probability than S2.During the update phase, UPDATE goes high and different voltages are applied to TOP and BOT for Fig. 4(a), or TOP, TOP, BOT, and BOT for Fig. 4(b), depending on the state of the connected neuron-if the neuron is active, then a homeostatic depression event occurs, and if the neuron is inactive, then a homeostatic potentiation event occurs.

D. INHIBITION MECHANISM
Inhibitory feedback is a mechanism to ensure that only a small number of output neurons are active at a time by decreasing the input strength of the others, and therefore, their chances of spiking, each time one has spiked.This enforces competition between the neurons, which enforces selectivity [36].Without it, it is likely for all neurons to become receptive to all input patterns and, therefore, there is no information from the network that can be used to discern the input patterns from one another, which is a key for unsupervised learning and probabilistic inference [36].The exact inhibitory mechanisms that the brain utilizes is still an active area of research but many SNN models utilize a fixed inhibition model such that every time a neuron spikes, a fixed decrease in input strength is applied to all other neurons [19], [37], and the same is used for the NSC.In order to minimize area overhead, the inhibition mechanism is implemented with a single nMOS connected to the SUM wire and GND.The input voltage to that nMOS is chosen such that the effect on SUM is equivalent to the negative of the strongest synaptic weight, W 5, and its associated distribution according to PV, as discussed in more detail in the Supplementary Material.

E. ARCHITECTURAL DISCUSSION
Fig. 5 shows all of the core components of the NSC integrated into a single-layer feed-forward SNN.During the read phase, which is when CLK is low, if POST is also low, and therefore, M read is on, all of the synapses with spiked presynaptic neurons, all of the homeostatic synapses, and all of the inhibitory feedback with active POST signals will source and sink current, generating a voltage at SUM due to the resistance of R sum and M read , which is the resulting parallel analog computation of weighted presynaptic spikes plus the cumulative effect of the homeostatic synapses minus any active inhibition and is applied to the input of the stochastic spiking neuron circuit.When CLK goes high, the postsynaptic neuron may or may not have spiked, M read turns off to prevent wasted current flow, all inhibitory feedback turns off for the same  The event-based nature of the NSC with its nonvolatile parameters affords flexibility to its operational and greater architectural needs.For instance, the NSC is described herein with two phases corresponding to different states of the clock for simplicity, but in principle, many other operations could intermix with the two main phases, such as routing algorithms for intrachip and interchip communications or monitoring processes.In addition, the clock rate could be adjusted based on the application needs, using a slower clock when idle and a faster clock as needed.The clock rate could also be adjusted based on as-manufactured timing considerations.Another beneficial aspect of the nonvolatile nature of the NSC is that the more power-intensive update phases are only required during training and/or retraining.Once a desired capability is achieved, the update phases can be much more dispersed or stopped altogether, saving considerable power.
Another benefit of the NSC is that it is able to learn patterns of different dimensions, as is described in Section IV, using all the same constituent circuits and devices with just an alteration of the number of homeostatic synapses-smaller dimensional inputs require more homeostatic synapses.Therefore, fixed NSC networks of a certain size could be fabricated and then inputs and homeostatic synapses could be turned on or off depending on the application needs.Also, this could provide redundancy in the case of unusable components, providing a higher potential yield.

IV. RESULTS
This section describes the simulation results of the NSC.The circuits of the NSC were simulated and analyzed using SPICE and then modeled in Brian2, an SNN simulation framework [38] to obtain the unsupervised learning results.Readers are strongly recommended to refer to the Supplementary Material regarding the details about Monte Carlo simulations for PV in both synapses and neurons.

A. UNSUPERVISED LEARNING
The emergent unsupervised learning capabilities of the NSC are demonstrated by learning a cortically inspired behavior, orientation selectivity, within a feed-forward SNN of 50 output neurons with 60 homeostatic synapses each and 900 Poisson spiking input neurons that each correspond to a pixel in a 30 × 30 stimulus window.The input pattern distribution consists of 180 28 × 2 bars centered and rotated in the stimulus window such that they cover the complete 180 • of rotation.The synaptic weights are initialized with S1-S3 randomly distributed and the homeostatic synapses are initialized with S1 in AP state and S2 in P state.Up to 10 000 randomly chosen samples from the input distribution are presented to the network for 100 clocks where each input neuron that the randomly chosen bar corresponds to has a Poisson spike rate of 75 spikes per 1000 clocks and all others have a spike rate of 1 spike per 1000 clocks.In between each sample is a brief period of 20 clocks whereby all input neurons have a spike rate of 1 spike per 1000 clocks.Fig. 6(a) shows the temporal evolution of a random selection of output neuron's receptive fields, that is, the strength of their 900 synapses shaped into a 30 × 30 window corresponding to the stimulus window, where a lighter color indicates a stronger synaptic strength, illustrating the emergent specialization of each neuron to a particular input pattern.Fig. 6(b) illustrates the emergent orientation selectivity in another way, where all synapses were fixed and each input pattern was presented to the network for 100 clocks and the spikes of all output neurons were counted and shown for a random selection of five output neurons.It can be seen that the spike counts closely resemble the tuning curves for simple cells in V1 cortex [39].In addition, the Supplementary Material shows the tuning curves for all output neurons, and it can be seen that the entire range of possible orientations is well represented by the collection of output neurons.The NSC was also tested using a smaller stimulus window of 20 × 20 and bars of 18 × 2, and the only needed change was an increase in the number of homeostatic synapses to 90.

B. NOISE ANALYSIS
The NSC is also quite robust to input noise and is actually able to utilize such noise for some benefit.This was tested by adding a uniformly distributed random spike rate between 0 and 7.5 spikes per 1000 clocks to each input neuron for each pixel in the stimulus window as described previously.The noise had a regulating effect, decreasing the number of homeostatic synapses required to just 30 for a 30 × 30 stimulus window.The NSC was still able to learn orientation selectivity with the noise, although the receptive field was qualitatively more noisy and the tuning curves were on average a bit broader, as shown in the Supplementary Material.

C. POWER ANALYSIS
The average power consumption for each of the NSC circuits was found using SPICE simulations as described in the Supplementary Material and was found to be 310 nW for the stochastic spiking neuron with PSP circuit, 1.9-7.7 nW for each of the input synapses, depending on the synaptic strength, and 1-3.4 nW for each of the homeostatic synapses, depending on its strength.The average power consumption of the network during the read phase for the neurons, homeostasis mechanism, and active synapses for the 20 × 20, 30 × 30, and 30 × 30 with noise test cases are shown in Fig. 7.The inhibitory mechanism was found to be negligible since very few output neurons are ever active at one time.As shown, the power consumption due to the output neurons is all equal since the number of neurons does not change.The power consumption due to the synapses increases from the 20 × 20 case to the 30 × 30 case since there are more inputs and synapses, and the noise increases the synaptic power consumption due to there being more active synapses as well as a higher number of higher strength synapses.The homeostasis power consumption is highest for the 20 × 20 case since it has the fewest active input synapses and, therefore, needs on average more homeostatic input synapses to drive the neurons to spike, and is lowest for the 30 × 30 with noise for the exact opposite reason.The power consumption of the update phase is not considered due to the NSC requiring updates only during training or retraining, and is thus a very small fraction of the total lifetime energy usage.In addition, the power consumption of the update phase depends heavily upon the materials, dimensions, and technology of the devices used.

V. CONCLUSION
The NSC described herein provides several intriguing insights to realizing ultralow-power neuromorphic circuits and architectures.Future directions for extending the NSC could be to implement recurrent connections and migrate the inhibitory mechanism to a population of inhibitory neurons, which would more closely resemble cortical network motifs, to explore how networks of NSCs could be connected together in deep or hierarchical fashions to realize greater computational ability, or to develop methodologies that can implement supervised or reinforcement learning capabilities.

FIGURE 1 .
FIGURE 1. Overview of relevant spintronic devices.(a) Two-terminal MTJ illustrating its three primary layers with a shared read and write path.(b) Three-terminal SHE-MTJ with a decoupled read path through the MTJ and the write path through the spin-hall metal.(c) Embedded p-bit with a very low MTJ and its associated CMOS circuitry.

FIGURE 2 .
FIGURE 2. Stochastic spiking neuron developed herein.(a) Neuron utilizes an embedded p-bit to compute the sigmoidal probability of spiking based on the voltage at IN and the PSP circuit senses the state of the p-bit at the positive clock edge and holds Neuron OUT high for 8 clocks for each spike.(b) Operational waveforms for IN = 144 mV, which corresponds to a spiking probability of ∼0.5.

FIGURE 4 .
FIGURE 4. Two alternative implementations of the homeostatic synapse.(a) This implementation requires the energy barrier of S1 to be different than S2 such that they have different switching probabilities for the same current.(b) This implementation does not require S1 to have a different energy barrier than S2 but requires additional update circuitry to provide different current pulses to each SHE-MTJ.

FIGURE 5 .
FIGURE 5. Structure of NSC illustrating the integration of the synapses, inhibitory feedback, homeostasis mechanism, and stochastic spiking neuron.

FIGURE 6 .
FIGURE 6. Unsupervised learning results for the NSC.(a) Emergence of orientation selectivity is illustrated here in the receptive fields for a random selection of five neurons.Brighter colors correspond to a higher synaptic weight.(b) Tuning curves for a random selection of five neurons are shown, illustrating their response to a narrow range of orientations.Each color represents a different neuron.

FIGURE 7 .
FIGURE 7. Average power consumption for each component of the NSC during the presentation of all 180 • of possible orientations for the 20 × 20, 30 × 30, and 30 × 30 with noise cases.