3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs

— This work presents new insights into 3D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat-transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit level simulations indicate a strong impact of temperature variation on functionality and figures of merits such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements


INTRODUCTION
In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge.With the deployment of large numbers of sensors and smart devices to form the edge of the Internet of Things to the scale of 50 billion and rising, data is now being generated at the edge rather than in the large-scale data centers that form the cloud.Current estimates put the ratio of data generation at the edge at over 40x that of global data center traffic, today around some 20ZB.The pure cloud computing model cannot handle this massively distributed, YB-scale quantity of data -the network infrastructure resources simply do not have the capacity to move the data from the edge to the cloud, the data is vulnerable to attacks and the transmission delay is prohibitively high.In advanced applications where delay requirements are particularly stringent (e.g. 1 ms in cooperative autonomous driving), the cloud computing model cannot consistently meet the deadlines.
The limits of the cloud computing model have given rise to the emergence of edge computing, where computing tasks are performed as close as possible to data sources to meet the low power and latency criteria [1].However, resources are constrained at the edge, in terms of available computational power, memory capacity and most importantly energy.
Hardware is critical at this level and there is a clear need to explore the suitability of breakthrough emerging technologies to meet the energy-efficiency, performance and compactness requirements of edge computing hardware as alternatives to traditional von Neumann machines.IRDS identifies Gate-All-Around (GAA) nanowire field effect transistors (NWFETs) as a future mainstream solution [1], both in lateral and vertical configurationshowever, the challenge is to extrapolate analyses beyond the device level to quantify relevant performance metrics [2][3].
In particular, junctionless Vertical NWFETs (VNWFET), capable of addressing existing process challenges such as downscaling, short-channel effects, compactness and electrostatic control, are difficult to meaningfully compare to existing mainstream technologies due to the additional vertical dimension and opportunities for innovative 3D logic design [4].A critical specific issue in this evaluation lies in the correct evaluation of the electrothermal behavior of the device [5].Indeed, the electrical performances of aggressively scaled transistors are strongly impacted by selfheating, ultrafast thermal transport and thermal conductivity degradation, all of which link to electron-phonon coupling which is not well understood at the nanoscale.The integration of this technology in the mainstream design flow is thus not straightforward and requires design technology cooptimization (DTCO) at an early stage [6][7].This paper is an important step to achieve this goal.
In this paper, we propose a compact model to enable multiphysics evaluation of intrinsic transistors, considering electro-thermal and trapping effects investigated through multiphysics simulations based on non-Fourier heat-flow [8].From the theoretical understanding of these effects in junctionless devices, the proposed compact model [9] captures temperature-induced increase in drain current through temperature dependence of model parameters including threshold voltage, drain/source Schottky barrier height and series access resistances.The proposed model also incorporates two additional sub-circuits for dynamic selfheating and trapping phenomena for evaluation of these effects at circuit level.We then project device performance to circuit level by using this compact model to characterize four basic 3D logic cells (INV, NAND, NOR and XOR) based on vertical nanowire transistors in terms of delay and energy consumption, thus proving that this emerging technology can be used as the basic building block for logic gates.
The paper is organized as follows: section II first describes the physical basis and implementation of the compact model (based on experimental measurements of the devices under test).Section III subsequently describes the logic cells and our characterization methodology in terms of delay and energy consumption, and with varying temperature.Section IV discusses results and perspectives, and summarizes possible future work.

A. Multiphysics modeling of intrinsic transistors
To accurately capture the underlying physics of junctionless FETs, the compact model presented in this work has been specifically developed based on the understanding of carrier transport studied using numerical multiphysics and TCAD simulations.Junctionless FETs offer a much and simpler fabrication process in comparison with classical MOSFETs [10], making them compatible for pursuing scaling beyond the sub 20-nm nodes.Most importantly, along with the absence of metallurgical junctions in these devices, they are heavily doped and the nanowire diameters are tailored to be quite thin in order to maintain gate electrostatic control over the channel.In order to ensure design compatibility between the junctionless VNWFET technology [10] and associated circuit simulations, the transistor compact model developed based on charge transport in gate-all-around junctionless transistors [9] is used first to calibrate the model parameters against experimental data of a wide range of transistor geometries (22 and 34 nm NW diameter with 16 to 81 nanowires in parallel) at room temperature.
Key physical parameters include doping, gate work function, mobility, drain/source Schottky barrier and threshold voltage.Once a good accordance between the model and the data is obtained, the compact model is then modified to take into account electrothermal and trapping effects, two critical issues in nano-scale junctionless transistors that can potentially impact dynamic circuit performance.To do so, we leveraged on-wafer DC measurements over a wide temperature range (15-100 °C) and pulsed-conditions with varying pulse widths (1 µs -10 ms) to dissociate temperature and trap-induced effects.From the experimental observations, it could be understood that increasing the temperature leads to a monotonically increasing drain current conforming to prior observations in junctionless transistors [11].This is explained by the strong temperature dependence of the threshold voltage in junctionless devices that leads to an increase in drain current along with a degradation of the on-off current ratio.This effect is further pronounced by the weak temperature dependence of the mobility due to competing lattice and impurity scattering mechanisms [11].From the pulsed I-V measurements, it could similarly be observed that the drain current showed a continuous increase with increasing gate pulse-width, allowing for an increasing number of traps to activate while the device temperature increases simultaneously.For very large pulses, the transistor current saturated to the measured DC current.This phenomenon can also be considered to impact the threshold voltage as confirmed by the VTH-shift with pulse width.This further affirmed that the threshold voltage in junctionless transistors is an important parameter to model both electrothermal and trapping effects.In the following sections, in-depth physical understanding of these effects, obtained through multiphysics simulations and compact modeling, are presented.

1) Electro-thermal and Trapping effects
Thermal management is one of the most challenging design criteria in nanoscale transistors owing to a lack of understanding of the heat conduction governed by phonon transport in sub-10 nm devices that include (1) ballistic, (2) boundary scattering and (3) confinement regimes [12].
Junctionless transistors are fabricated with a very thin channel along with a chosen gate work-function to ensure that the transistors switch to off state at zero gate bias, switching to full depletion mode.In addition, the nanowires are required to be strongly doped to ensure a higher drive current in order to compensate for the Schottky barriers at the source and drain sides.Phonons can be considered as a quasiparticle originating due to lattice vibration and can be confined in the Si/SiO2 interface similar to trapping, leading to a reduction of the thermal conductivity.In addition, due to electron-phonon coupling and phonon confinement, carriers (electron or hole) can also be trapped in the lattice distortion leading to the wellknown self-trapped electron phenomena [13].Moreover, in the nanoscale regime, explaining ultrafast heat flow using the classical hydrodynamic formalism based on Fourier's law no longer remains valid.The Guyer and Krumhansl equation (GKE) has recently been demonstrated to capture nondiffusive heat transport in the nanoscale regime beyond classical Fourier's law, offering understanding of non-local thermal effects [14].
To understand the electron-phonon coupling behind the electrothermal behavior and trapping effects for nonequilibrium states in both steady and transient conditions in junctionless transistors, we leveraged finite element method (FEM) based COMSOL multiphysics simulations [15] based on the GKE formulation by solving the non-Fourier heat equation coupled with the drift-diffusion model and interface trapping effects.The material parameters are included in the simulator physics library whereas the operating conditions and device geometries are defined according to our experimental setups.The governing equation of the GKE for non-Fourier heat dissipation is written as [16],

𝑑𝑟
(1) where  is the heat flux,   is the phonon relaxation time,  is the thermal conductivity, ℓ is the phonon MFP,  is the heat capacity, T is the temperature.To consider the electrothermal effect we use the energy-conservation equation: where  is the dissipated power defined as  =     .The multiphysics simulations reveal that the temperature distribution inside the nanowire exhibits a steady increase of internal device temperature along the channel (Fig. 1(a)), reaching the peak near the drain (Fig. 1(b)), implying thermal confinement and self-heating at elevated temperatures and bias conditions.This is reflected by an equivalent degradation in thermal conductivity within the channel (Fig. 1(b)).As highlighted in the previous section, the temperature variation induces a linear threshold voltage shift which can be extracted from experimental results (Fig. 1(c)).In addition, the thermal resistances (RTH) of the VNWFETs have been extracted from both measurements and Multiphysics simulations [17] which exhibit an inverse geometrydependence (Fig. 1(d)).
Similarly, under pulse conditions, we studied the thermal conductivity and temperature rise using COMSOL for various pulse widths that also indicated an increase of the device temperature (along with an equivalent reduction of thermal conductivity) due to phonon accumulation near the drain region at high bias conditions and larger pulse widths (Fig. 2(a)).The numerical model was then used to extract the trap densities (Fig. 2(b)) that were compared with the VTH variation for different pulse widths, which revealed a clear trend in both cases: the VTH drift observed from the measurements could be described by a similar relation that also governs trap density,   =   (1 − exp (−  /) ).This led us to define the following physical relation for trapinduced VTH-shift in our model: ∆V  = αqN T /C ox , where α is a constant, q is the electronic charge and COX is the gate oxide capacitance.Figs.3(a    2) Compact model implementation Following the multiphysics simulations, it could be confirmed that in the junctionless nanowires, thermal conductivity reduces significantly with temperature, thus creating temperature hot-spots and leading to possible device self-heating.Moreover, the trap density evolves exponentially with applied gate pulse width saturating to the DC value where internal device temperature rises significantly coupled with the presence of traps.To translate these effects for compact modeling, we modify the expression of the threshold voltage to capture the effect of internal device temperature increase and trap density fluctuation.To do so, we leverage the equation ∆  = ∆  () + ∆  (  ), where the first term captures a linear temperature dependence through a temperature coefficient whereas the second term incorporates a trap density-like dynamic exponential formulation activated through a FLAG parameter, with both parameters extracted from experimental results.In addition, an equivalent electrical subcircuit consisting of the thermal resistance and capacitance (extracted from low-frequency S-parameter measurements) has also been added to the compact model formulation in order to capture the dynamic variation of internal device temperature due to self-heating which can also be activated through a FLAG parameter.Lastly, temperature coefficients of additional model parameters such as the Schottky barrier height, series access resistances, intrinsic carrier concentration and drain induced barrier lowering are also implemented in the model equations.Compact model simulation results are validated against experimental data for both pulsed (Fig. 3

B. Enhanced devices through the integration of materials
or architectures While junctionless VNWFETs already bring significant benefits to transistor performance, additional features can be naturally achieved.This subsection covers emerging characteristics of such functional enhancements from a prospective viewpoint.

1) Ferro gate
Adding ferroelectric material to the VNWFET gate stack [18] enables non-volatile logic as well as non-volatile reconfigurability.For example, a non-volatile full adder [19] is able to store one of the summands in a non-volatile manner, which is of particular interest in multiplication operations used in digital filters or convolutional neural networks, and where one summand varies constantly (data), while the other one varies rarely (coefficients).Reconfigurable in-memory computing is enabled by the conjunction of ferroelectric VNWFETs with classical LookUp Table (LUT) circuit structures such as a LUT2 [20] and where the output depends both on the select inputs (S0 and S1) as well as on the stored states (here 4 states stored in a non-volatile manner to reflect a 2-input truth table), i.e.  = . 1 ̅ . 0 ̅ + . 1 ̅ . 0 + . 1 . 0 ̅ + . 1 . 0 .

2) Reconfigurable FETs
Polarity-controllable transistors (PC-FETs) leverage a multitude of input gates on a single ambipolar channel, to dynamically select both conduction state, as well as carrier type (Fig. 4) [21].PC-FETs connected to a common body enable inherent X-to-1 multiplexing in a single transistor with  X independent drain-contacts.Non-volatile PC-FETs in a 3D tile also intimately incorporate multi-bit memory capability within computing elements, thus opening the way for a new concept for computing-in-memory.

C. Toward Dynamic Modeling
Another design perspective for improved dynamic performance of the logic cells includes optimized test structures.To ensure circuit design involving a 3D emerging technology, accurate compact models capturing the static and dynamic device behavior are mandatory [7], but on-wafer test structures of such devices also include parasitic elements induced by pads and interconnects that are necessary to probe the devices under test (DUT).Due to the 3D nature of interconnects, standard methods to remove these parasitic contributions (de-embedding) become inaccurate owing to the fact that classical design of passive test-structures (Open and Short) no longer remain sufficient to completely model the extrinsic 3D parasitic network.Figure 5 shows the respective sizes of the DUT and its associated test structure illustrating the requirement to reinvent dedicated deembedding methods for the 3D VNWFET technology.In [22] a new de-embedding method for this technology was introduced that makes use of electromagnetic (EM) simulations to virtually reconstruct the entire parasitic network including coupling capacitive, inductive and resistive parasitic elements.
The values of all these parasitic elements constituting the small-signal equivalent circuit (SSEC) were calculated through (i) analytical equations from the physical dimensions, (ii) the material properties of the device, (iii) the standard calibration techniques such as SOLT (Short-Open-Load-Thru) as well as (iv) from EM simulations.The overall SSEC is shown in Fig. 6 along with the values of the parasitic elements.At this stage, this SSEC can be used to generate the ABCD matrices of the gate and drain parasitic access contributions for successful de-embedding of the intrinsic Sparameter measurements [17,22].This allows us to extract the intrinsic transistor S-parameters for device modeling and subsequently continue towards 3D logic cell design.

III. STANDARD LOGIC CELL MODELING
In this section, we leverage the developed compact model to assess the performance metrics of various 3D logic cell circuit topologies in the VNWFET technology.The ultimate goal of this study is to enable logic synthesis, which needs a library of characterized basic logic cells as a prerequisite.

A. Energy-delay characterization of standard logic cells
The goal of the following simulation-based exploration is to study the impact of using a large range of nanowires per transistor on typical static and dynamic logic performance metrics, for several standard logic cell topologies.In the simulation protocol, we assume that the gate capacitance behaves in the same way for both p-and n-type VNWFETs, and that the capacitive load on the output of each structure is equivalent to that of a single inverter of drive strength 1.Since the VNWFET gate capacitance is experimentally determined to be 20aF per NW, and assuming that its evolution with NW number is linear, we deduce a capacitance contribution for INV1X1 as 160aF.
In this context we aimed to study the behavior of four main logic cells: INVX1, NAND2X1, NOR2X1, and XOR2X1.Figure 7 depicts the transistor-level schematics of these Boolean gates, where the formalism OPnXk indicates the boolean operation OP, the number of inputs n and the number of outputs k of each gate.carried out simulations using the HSpice TM commercial simulator, where we used the compact model described in section II implemented as an executable Verilog-A model for the VNWFET.The gate physical length Lg and the nanowire (NW) diameter dnw are both parameters which are determined by the fabrication process.Throughout this work, and based on experimental devices, the values of these parameters are set to Lg = 18 nm and dnw = 22 nm respectively.Based on this, as well as the definition of other fixed model parameters, we investigated the number of nanowires for p-type and n-type transistors to be used, as the only design parameter remaining to enable the optimization of device and circuit performance.The first essential step in this work is to verify the functionality of the n-type and p-type VNWFET devices themselves through DC-sweep simulation in order to ensure that they have the expected IDS/VGS characteristic behavior, as illustrated in Figure 8. Subsequent to this verification, we simulate an elementary inverter gate shown in Figure 7(a) in order to determine the correct ratio between n-type and p-type NW (number of nanowires per VNWFET) values to obtain an optimal midpoint voltage.In this work, we also chose a range of values of NW for n-type transistors that allows us to study the behavior of the device under different drive strengths.For each value, we run DC-sweep simulations while varying the gate voltage from 0 to VDD and assessing the output behavior for varying numbers of nanowires for the p-type device.We find that for all the defined NW values, a ratio of 1 between the number of NWs of p-type and n-type will give us an optimal midpoint voltage at half VDD as shown in Figure 9, which leads to balanced noise margins and well-matched rise and fall times of the cell.Fig. 9: Variation of inverter output voltage as function of the input voltage variation between 0 and VDD (1V) for different ratios between the number of nanowires (NW) used for p-type and n-type transistors.It can be clearly seen that a ratio of 1 between NW of p-type and n-type devices achieves optimal midpoint voltage at half VDD.
It is important of course to note that this ratio depends on the set of parameters used in the simulation.For this study, the chosen values for the number of NWs of the n-type device of the inverter were 4, 24, 44 and 64.The corresponding number of NWs for the p-type device is chosen according to the above described methodology.For the other cells, and in order to achieve drive strengths equivalent to that of the inverter, we redefine the number of nanowires by doubling the number of NWs in case of two series transistors.After defining the sets of NW parameters, we identify the simulation limitations of the executable model and adjust our simulations accordingly.Then a detailed study of the static and dynamic behavior of all cells was carried out, as detailed in the following subsections.
This study was done by varying the number of nanowires used in each logic gate to study their behavior under different drive strength.The simulations showed that using this technology we can successfully implement logic NOT, NAND, NOR and XOR functionalities as shown in Fig 10.
To characterize the library of standard logic cells, it is necessary to study the main conventional performance metrics of the targeted logic cells, i.e. propagation delay, rise/fall time and dynamic power consumption where:  The delay corresponds to the time difference between the output voltage and input voltage to reach half VDD  Rise (resp.fall) time corresponds to the time needed by the output voltage to rise (resp.fall) from 0.1VDD (resp.0.9VDD) to 0.9VDD (resp.0.1VDD)  The dynamic power consumption for a particular transition is calculated by measuring the supply current during the output transition  The leakage power is calculated by measuring the supply current during all static combinations of inputs For each cell, all the possible output transitions based on input(s) transitions are defined.Then for each case, the timing and energy consumption are measured as described above.For all the cells under study we found, as expected, that with the increase in the number of NWs used, a decrease in delay (Fig 12) and rise/fall times is observed as well as an increase in dynamic power consumption (Table I).

B. Parasitic-annotated assessment
For devices with such small dimensions and compact footprint, circuit-level parasitics (in particular from coupling capacitance, metal contact, layout-related issues) can significantly limits the benefit in design.In order to assess the impact of parasitics, we designed the layout for a 2-input XOR gate (one of the more complex logic functions, and including in-cell generation of complemented inputs) as shown in Fig. 13(a) and extracted the associated parasitic network based on the aforementioned geometrical parameters and material coefficients.Metal interconnect layers connect top and bottom nanowire contacts, as well as gate contacts surrounding the nanowires to create GAA devices.Transient simulation results for the resulting parasitic-annotated 2-NW/transistor XOR2 cell are shown in Fig. 13 (b).This enabled us to carry out a comparative study in order to quantify the impact of parasitic interconnect networks on key performance metrics.The full dataset is shown in Table II.
Comparing delay and energy per transition figures, we quantify the average increase in delay as +4% and energy/transition as +19% when considering the parasitic interconnect network.
) and (b) show the multiphysics simulation results depicting good agreement with experimental I-V characteristics.

Fig. 1 :
Fig. 1: Electrothermal simulations using COMSOL: (a) temperature contours along the nanowire, (b) Temperature and thermal conductivity at different measurement temperatures; Extracted (c) temperature dependence of the threshold voltage, (d) thermal resistance of the VNWFETs.

Fig. 2 :
Fig. 2: Electrothermal simulations using COMSOL: (a) temperature and thermal conductivity distribution inside the nanowire obtained at room temperature under different pulse conditions along the nanowire, (b) Extracted threshold voltage (measurement) and trap density (COMSOL) showing similar dependence on the pulse width.

Fig. 3 :
Fig. 3: Evolution of drain current with (a) different pulse widths and (b), (c) measurement temperatures comparing experimental results, multiphysics and compact model simulations for a p-VNWFET with 25 parallel nanowires of 22 nm diameter.

Fig. 4 .
Fig. 4. Polarity-controllable transistor with Fe-Gate.While PC-FETs require a constant input to program gates, Fe-gate oxides are programmed by a pulse, reducing the dynamic power consumption.

Fig. 5 :
Fig. 5: Schematic depicting the size of the test structure featuring GSG (Ground-Signal-Ground) pads allowing the use of the RF probe with regards to the size of one single nanowire featuring the channel of the VNWFET.

Fig. 6 :
Fig. 6: The complete SSEC (Small-Signal Equivalent Circuit) of the passive elements associated with the VNWFET test structure.

Fig. 7 .
Fig. 7. Schematics of logic cells studied: (a) INV1X1, (b) NAND2X1, (c) NOR2X1, (d) XOR2X1.The first step was to prove the ability of implementing such cells based on the VNWFET technology.In this context, we

Fig. 8 .
Fig. 8. Variation of drain-source current IDS with gate-source voltage VGS and number of nanowires per VNWFET NW of (a) n-type VNWFET and (b) ptype VNWFET.

Fig. 11 .
Fig. 11.Delay in output (a) rising, (b) falling transitions of a NAND gate as affected by different input transitions

Fig. 11
Fig.11is a detailed example on how we studied the delay behavior of each logic cell.It is clear that the delay is dependent on the input(s) transitions, and that with the increases of NWs used per VNWFET the delay will decrease.For all the cells under study we found, as expected, that with the increase in the number of NWs used, a decrease in delay (Fig12) and rise/fall times is observed as well as an increase in dynamic power consumption (TableI).

Fig. 13 .
Fig. 13.2-input XOR logic cell.(a) Layout used for parasitic extraction.(b) Transient simulation results with and without parasitic annotation.

Table I :
The dynamic energy values (aJ) for the logic cells under study, for all possible input transitions leading to output rising or falling transitions and for different number of NWs.