Circuit-based Electrothermal Modeling of SiC Power Modules with Nonlinear Thermal Models

—Silicon Carbide (SiC) power devices have the potential to operate at high temperatures beyond the capabilities of silicon power devices. At increased temperatures, the temperature-dependent material properties of the SiC die and the package multilayer structure can inﬂuence the electro-thermal (ET) device performance. In this paper, a new Step-Back-Correction (SBC) technique implemented in a Finite-Difference-Method-based thermal modeling tool is proposed to reduce the computational cost while maintaining a good accuracy of ET simulations for multichip power modules. The simulations take the temperature dependence of the thermal conductivity k ( T ) and both conduction and switching losses into account. The importance of considering k ( T ) for an accurate temperature prediction of SiC power devices is demonstrated for thermal impedance evaluations characterized by high temperature swings, as well as for a 100 kHz boost converter with low device temperature amplitudes in the steady-state. The proposed ET modeling is validated by COMSOL simulations and IR camera measurements on an example of a custom-designed and -manufactured half-bridge SiC power module.


I. INTRODUCTION
E MERGING silicon carbide (SiC) power semiconductor devices have pushed the performance limits of power electronic (PE) systems, allowing faster device switching and higher device operational temperatures.System optimization and advanced packaging are necessary in order to utilize SiC power semiconductor devices in the most efficient way in PE applications [1].Besides enhanced electromagnetic performance, advanced packaging technologies strive towards increasing the operational temperature range of SiC power devices in the applications beyond T max = 150 − 175 • C [2].For higher operating temperature range and with large temperature variations, temperaturedependent thermal properties of package materials can have a high impact on the overall electrothermal package performance.For example, due to its high thermal conductivity, aluminum nitride (AlN) ceramic substrates have been employed in power modules designed for high temperature and/or high voltage applications [3]- [5].The thermal conductivities of SiC and AlN feature more pronounced temperature-dependency than other materials as copper (Cu), aluminum oxide (Al 3 O 2 ) and silicon nitride (Si 3 N 4 ), The authors are with the Advanced Power Semiconductor Laboratory, ETH Zurich, Switzerland, contact e-mail: (race@aps.ee.ethz.ch).cf.Fig. 1.As temperature of power devices is a crucial design parameter for system performance and reliability, great efforts are made in the direction of evaluating temperature development inside of power semiconductor packages under application conditions, by means of real-time device temperature measurements and/or electrothermal (ET) modeling [6].The main focus of this paper is placed on efficient ET modeling of multichip power modules, taking into account temperature-dependent thermal properties of multilayer package structures.This provides a highly valuable input for accurate temperature prediction of SiC power devices operating with higher temperature amplitudes and levels, i.e.T max = 200 − 225 • C.
In the state-of-the-art literature, ET modeling has been mainly performed using linear and time invariant thermal models [7]- [14], i.e. neglecting temperature-dependent material properties.Non-linearity can be taken into account by fully numerical two-way ET modeling using the well-known multiphysics tools such as COMSOL [15] and ANSYS [16].However, modeling the device switching losses within such two-way coupled ET modeling environments is not straightforward and circuit simulators implementing temperaturedependent device models are required to calculate switching losses, which are further used as input to determine the temperature of the respective devices.Furthermore, Spice-like circuit simulators specialized for computationally extensive simulations of device switching behavior and handling various Spice models of power semiconductor devices typically provided by device manufacturers, are preferred for power electronics applications.
The thermal time constant of PE converter design with large heatsinks is in the range of seconds, so that the device temperature variation under nominal operation is rather small for the most PE applications.Neglecting small temperature swings allows the application of iterative approaches for evaluating the steady-state device temperature in operation [17], [18].On the other hand, estimating the time-dependent temperature of power semiconductor devices has to be performed using fully coupled ET modeling, which in turn can be achieved by either simulating PE converter circuits simultaneously with (non-)linear thermal models or directly coupling a circuit simulator with a thermal modeling tool.While the former approach is expensive with respect to computational time and memory storage, since device temperature is updated in every time step of the circuit simulation, which can be in the range of picoseconds, the weak point of the latter approach is data exchange between two simulators, which can contribute to longer simulation time.
Typically in the commercial circuit-based ET modeling environments, such as e.g.ANSYS Icepak-Simplorer, [19], only temperature-invariant thermal models can be used.Extracting nonlinear thermal models is not straightforward.A nonlinear thermal model can be imported in the circuit domain in the form of either equivalent Cauer- [20], [21] and Foster-type networks [22], or reduced-order equivalent circuit models [23], [24].Cauer-and Foster-type networks are obtained typically by performing FEM simulations or thermal transient measurements at different power levels, while specialized model-order reduction techniques as presented in e.g.[23] are required for extracting reduced-order non-linear equivalent circuit models.For both methods, the computational cost significantly increases with a higher number of heat sources, i.e. higher number of power semiconductor dies.To avoid thermal modeling requiring insurmountable memory storage and extensive FEM simulations, an ET modeling method considering nonlinear thermal conductivity was proposed in [24], employing the so-called Kirchhoff transformation.Namely, the effect of temperature-dependent thermal conductivity of SiC dies was approximated from an equivalent linear model using a single correction factor derived from a smaller number of steady-state FEM thermal simulations.As tuning the correction factor is based on steady-state FEM simulations, this approach is not suitable for modeling transients of multichip power modules taking into account temperaturedependent thermal conductivities of a multilayer package structure.Consequently, the temperature-dependent thermal properties of packaging materials are commonly neglected in conventional ET simulations based on reducedorder thermal models [12]- [14].
A PSpice-COMSOL-based 3-D ET modeling with a MAT-LAB script used as an interface link between the PSpice and COMSOL simulations was presented in [25], on an example of an IGBT power module operating under short circuit conditions.The package material layers below the baseplate, such as thermal interface material (TIM) and heatsink, were not modeled, in order to improve the simulation efficiency.Namely, the circuit-based ET simulations of power modules with large heatsinks is computationally challenging due to few orders of difference between their electrical and thermal time constants.By not modeling the material layers contributing to a larger thermal time constant such as TIM and heatsink, existing in the actual power converters, the steady-state solution of the ET simulation can be reached at lower computational cost.Furthermore, the computational complexity is increasing by using third software as MATLAB for the interface link between the thermal and circuit simulators, as well as, for modeling multichip power modules, which was not addressed in [25].
based thermal modeling tool with a built-in interface link to the LTSpice circuit simulator, allowing computationally feasible circuit-based ET simulations of multichip power modules with temperature-dependent thermal conductivity of package materials.Moreover, the proposed ET modeling approach allows to control the trade-off between accuracy and computational cost when simulating fast electrical transients.
In comparison to FEM-based thermal modeling, the FDM uses a structured mesh and leads to an equivalent threedimensional RC thermal network.The advantages using the FDM for thermal modeling of power modules are described as well as in [10], [12], [13], [34], [35], however the computational cost when modeling nonlinear thermal systems due to temperature-dependent material properties and the importance of considering temperature dependent material properties have not been addressed up to now.FDM-based thermal solvers presented in [34], [35] addressed modeling of temperature-dependent package material properties.The presented modeling approaches require a high-order system matrix to be updated and solved in every simulation step, which significantly slows down the simulation and makes it less attractive for ET simulations.The FDM-based thermal modeling tool developed in-house is therefore extended in this work by a new modeling approach, which allows decreasing computational cost of FDM-based thermal modeling with temperature-dependent thermal conductivities.
The paper is organized as follows: in Section II, the effects of temperature dependent thermal conductivity and specific heat capacity are analyzed on an example of a SiC half-bridge (HB) power module designed in-house.In Section III, the proposed FDM-based thermal modeling approach is presented and compared to COMSOL FEM thermal simulations.In Section IV, fully-coupled circuitbased ET simulations of the developed HB SiC power module are performed for different current pulses using a commercial circuit simulator, LTSpice, and the improved FDM thermal tool, showing a higher modeling error when employing constant thermal conductivities.The verification is performed by using IR camera measurements and COM-SOL FEM-ET simulations for the case of power semiconductor devices operating in conduction mode.Challenges and perspectives of fully-coupled circuit-based ET modeling when both conduction and switching losses have to be taken into account are discussed in Section V. Namely, the advantage of ET simulation based on an iterative approach over coupling thermal and electrical domains by means of a circuit simulator is demonstrated for a 1.2 kV HB SiC power module employed in a high frequency (100 kHz) boost converter.

II. ANALYSIS OF TEMPERATURE-DEPENDENT MATERIAL THERMAL PROPERTIES
In this section, the impact of temperature-dependent thermal conductivity k(T ) and specific heat capacity c p (T ) on the temperature development of SiC power devices is investigated using the structure of a half-bridge (HB) power module (PM) designed and manufactured in-house [36].The PM contains 4 SiC dies [37], soldered with SAC305 on Cu-AlN-Cu Direct Copper Bonding (DCB) substrates, see Fig. 2a).The DCBs are in turn soldered to a Cu baseplate, which is thermally connected to the 4 mm thick Cu coldplate by the thermal interface material (TIM), cf.Fig. 2b).Electrolube HTSP thermal paste is used as TIM layer.The package was not optimized for high temperature operation, so all experiments and simulations performed to validate the proposed modeling approach were designed to keep the junction and solder layer temperature below T max = 210 °C.In the simulations, the temperature of the coldplate's bottom surface is set to a constant value, which models the cooling system of the Mentor Graphics Power Tester 1500A used for thermal characterization.As the heat is mainly generated in the channel during the nominal device operation of SiC power MOSFETs, the heat sources are placed at the top surface of the power semiconductor dies.The chip Al-metallization and bond-wires are neglected in the analysis, since they do not have a significant impact on the dominant heat-flow towards the heatsink.Table I shows the analytical formulas used for modeling the temperature-dependent thermal conductivity k and specific heat capacity c p of the package materials, Cu, SiC and AlN.Constant thermal properties for the solder (SAC305) (k = 55 W m −1 K −1 , c p = 218 J kg −1 K −1 , mass density ρ = 7800 kg m −3 ) and TIM layers (k = 1.09W m −1 K −1 , c p = 1090 J kg −1 K −1 , ρ = 1470 kg m −3 ) are used due to a lack of information about the temperature-dependent behavior of these materials.The assumption of die attach layer with a weak temperature-dependence of thermal conductivity is typically justified for power modules with silver sinter joints [38] designed for high temperature operation.Accordingly, the presented analysis based on a die attach layer with a constant thermal conductivity leads to accurate conclusions on the importance of considering nonlinear thermal conductivities of power module's materials for high-temperature applications.
In the following analysis, a single device marked in Fig. 2 as LS2 is used as heat source, without loss of generality.Four simulation types with respect to k and c p of SiC, Cu and AlN are performed in COMSOL Multiphysics: (SIM1) both c p and k temperature-dependent, (SIM2) c p =c p (T amb ) and k temperature-dependent, (SIM3) c p temperature-dependent and k=k(T amb ), and (SIM4) c p =c p (T amb ) and k=k(T amb ), with T amb = 100 °C.Throughout this paper, except when specified, the thermal impedance matrix Z th is calculated from the junction temperatures T j evaluated as the average temperature at the active area of the dies, which in turn corresponds to the temperature evaluated by temperature sensitive electrical parameter (TSEP) measurements [16].
Both self, Z th11 , and mutual thermal impedance, Z th21 , are evaluated for two input power steps of 100 W and 200 W as shown in Fig. 3a)-3b) and Fig. 3c)-3d), respectively.For both power levels, overlapping thermal impedances are obtained in SIM3 and SIM4, demonstrating a negligible impact of c p (T ) on the device temperature evaluation in the temperature range up to for P heat = 100 W, cf.Fig. 3a), and T jmax = 207 • C for P heat = 200 W, cf.Fig. 3c).The matching between self-impedances evaluated in SIM1 and SIM2 furthermore confirms that the temperature dependence of the heat capacity of SiC can be neglected in the temperature range up to ≈ 225 • C. It is worth mentioning that for fast and large temperature changes, i.e. ∆T > 800 K in few µs, also c p (T ) plays an important role as demonstrated for short circuit operation of a SiC power MOSFET in [39].The modeling error made by neglecting k(T ) is still acceptable for a lower input power of P heat = 100 W, where the absolute difference for Z th11 is only 0.02 K/W and a junction temperature difference of ∆T j,max = 2 • C, i.e. 1.3%; whereas for P heat = 200 W, Z th11 is underestimated by 0.04 K/W leading to ∆T j,max = 8 • C, i.e. ≈ 3.9%.The mutual-impedance Z th21 is not influenced by the temperature dependence of material properties, cf.Fig. 3b) and 3d), as the thermal coupling between the two dies is mainly determined by the heat path via the top Cu layer of the DCB substrate with almost constant thermal properties, cf.Fig. 1.

III. THE PROPOSED FDM-BASED THERMAL MODELING TOOL
In this section, a FDM tool developed in-house [40] is further improved in order to model the temperature dependence of thermal conductivity in a computationally more efficient way and hence, to alleviate the coupling between the electrical and thermal domains.This allows temperature profiles of power devices carrying variable currents to be estimated more accurately.

A. Modeling Method Implementation
An FDM thermal model describes the three-dimensional (3-D) geometry in the form of a 3-D equivalent electrical network.Each element of the structured mesh is associated to an m-th FDM node, with a thermal capacitor C th,m connected to the ground node, representing the heat storage, and thermal resistors R th,mk connected to the neighbor k-th node, modeling thermal conduction paths in a Cartesian coordinate system.The values C th,m and R th,mk are determined based on the elemental cell geometry and material properties [41].Then, the equivalent network can be expressed in a matrix form described by equation ( 1), where G th is the symmetric conductance matrix containing the information about R th,i j , C th is the diagonal capacitance matrix, Q(t ) is the input vector modeling heat sources in time-domain and T (t ) is the temperature vector representing the unknown temperature distribution to be calculated.
The System of Linear Equations (SLE) given by (1) of order n, where n is the number of nodes, is solved in the developed FDM-based thermal tool using the Gear-Schichman integration method [42], which leads to equation (2a), where the superscript indicates the i -th time step and ∆t is a discretization time step.The matrix on the left-hand side of equation (2a) is the so-called system matrix S th , whereas the right-hand side is denoted as a modified input vector Qi , thus leading to equation (2b).As G th is symmetric and very sparse and C th is a diagonal matrix, the matrix S th is a sparse matrix, hence it can be efficiently reduced with a model order reduction (MOR) approach.
Considering that the discretization of power module geometries can lead to a very high number of nodes n, typically n > 10 4 , a reduction of system complexity is highly recommended to speed up the calculation time at each time step.The MOR technique used in this paper is the Passive Reduced-order Interconnect Macromodeling Algorithm (PRIMA) [43], which guarantees a very accurate reduced model of a RLC network.Applying the MOR transformation to equation (2b) leads to a reduced system defined by equation (3).
The size of the new reduced order system matrix S thRed is n red × n red , where n red n.The reduced size n red and accuracy is controlled by an expansion order parameter, i.e. a high expansion order leads to a more accurate model with a higher number of nodes.The selection of a suitable expansion order strongly depends on the number of ports.

The node temperature vector T i
Red is then calculated using a direct solver based on the lower-upper (LU) decomposition.
In order to include the temperature dependence of the thermal conductivity k, the conductance matrix G th containing the information about k(T i ), and hence, the system matrix S th , have to be updated in each simulation step [34], which complicates the implementation of MOR techniques for non-linear systems.A modeling approach named Step-Back Correction (SBC) is proposed in this paper with the aim to avoid a re-calculation of S th in each time step and make an FDM thermal simulation with temperaturedependent thermal conductivity computationally more efficient.The idea of the SBC method is that the modeling error made when using a temperature-independent conductivity is corrected retroactively in the next time step, which is realized by a correction term introduced in the modified right-hand side input vector.In this way, S th is calculated only once at the beginning of the simulation.The reduced SLE (3) at i + 1-th time step, t i +1 , is modified according to the procedure described in Fig. 4: The two introduced matrices G Tid th and G Td th are the temperature-independent (Tid) and temperaturedependent (Td) thermal conductance matrix, respectively.While G Tid th is defined once during the model initialization and then used to fill out S th , G Td th is constructed in each time step based on the actual k(T i ).In line 5 of Fig. 4, a reverse MOR transformation is applied to evaluate the original temperature vector, which is multiplied by the difference (G Tid th − G Td th ) as specified in line 10, in order to calculate the correction term.This step is necessary, as a direct link between the physical nodes and the reduced model does not exist.The correction term is combined with the updated input vector, and applying a MOR transformation to the right-hand side expression, as given by line 11, leads to a corrected reduced input vector Qi+1 cRed .The modified SLE is then solved for the unknown vector T i +1 Red , containing the information about the temperature of the selected nodes, i.e. ports.Here, it should be pointed out that the SBC method requires a reconstruction of the temperature vector in each time step, instead of the reconstruction of the whole system matrix.Accordingly, the additional computational cost of FDM-SBC is mainly determined by the calculation of G Td th and the correction term.However, in each time step not only the average temperature across the active die area can be calculated but also the temperature of all FDM nodes.Accordingly, the temperature distribution of the whole package defined by mesh nodes can be extracted.

B. Thermal Modeling Verification
In this section, the accuracy of the developed FDM-SBC method is verified with COMSOL Multiphysics, i.e. a wellknown FEM-based modeling tool, on the example of the HB PM shown in Fig. 2. Five ports, i.e. four for the junction temperatures and one for the boundary to the ambient, are defined in the model.The thermal conductivities of die-attach and DCB-solder layers are properly calibrated to match the T j obtained from IR-camera measurements [36].The bottom boundary temperature is fixed to 100 • C.
In the proposed FDM tool, the geometry is discretized in ≈ 37'500 nodes and a PRIMA-MOR of order twelve is selected to simulate the temperature response to a power pulse P in .A mesh with ≈ 35'000 elements is used for the COMSOL simulations.Two temperature responses are evaluated for input power P in = 50 W and P in = 150 W applied for 5 s to the four dies, as shwon in Fig. 5.
The comparison between the simulation results demonstrates good matching between the COMSOL FEM-based and the proposed FDM-based thermal model.The relative error between the two modeling approaches is below 0.5 % for the entire transient simulation of the virtual junction temperature, which is mainly ascribed to the different meshing and modeling approaches.Namely, the maximum difference between the two approaches is 0.1 K for 50 W and 0.3 K for 150 W. In order to quantify the relevance of k(T ) for this specific test case, the temperature responses of all four dies are evaluated assuming constant k(T = 100 • C) as shown in Fig. 5b), i.e. the T j of LS2 die is underestimated by 6.1 K.
The simulations are performed on a machine with eight cores of an Intel(R) Xeon(R) Gold 6254 processor, 3.10 GHz, 96 GB RAM.In the proposed FDM-SBC-based modeling, the simulation time depends on the number of time-steps as shown in Table II.
Large time-steps lead to inaccuracies during fast transients, however the steady-state temperature is not affected, as shown in Fig. 6.This proves that the error of the steady-state solution does not increase with larger time steps, when using the proposed FDM-SBC approach, and furthermore, it allows controlling the trade-off between the simulation time and accuracy, which is highly important for ET simulations of power converters, i.e. the average device temperature during a longer electrical transient is rather of interest.Namely, the selection of a proper thermal time-step is crucial to ensure a steady-state solution in a reasonable time, especially when the thermal tool is coupled with a circuit simulator.
Similarly, the number of FDM nodes n impacts the simulation time, as the SBC requires in each time step to reconstruct T i , to update G Td th and to apply the MOR to the corrected RHS vector.The simulation time for 5001 time-steps and the meshes of 28'400 and 47'700 elements is 4h 20min and 17h 20min, respectively.However, with an optimized structured mesh of a multichip power module, a high number of FDM nodes is not necessary to achieve an accurate solution, i.e. the number of ≈ 37'500 elements used in Fig. 5 can be further reduced.An implementation of an automated optimized structured meshing in the developed FDM thermal tool will be addressed in the course of future work.It should be noted that the FDM simulation with temperature dependent thermal conductivities based on the proposed SBC approach is ≈ 5 times slower than the FDM simulation with temperature-invariant thermal conductivities.However, this increase in calculation time is necessary to obtain an accurate thermal model.With the aim to validate the effectiveness of the SBC approach, the same simulation is performed in the FDM thermal tool by updating the system matrix S th in each time step using the corresponding time-changing thermal conductivity k(T i ).The simulation time lasted more than 48 h on the same machine for 37'500 mesh-nodes and 5001 time-steps.Updating S th in each time step prohibits using the MOR approach, as the MOR pre-processing would have to be performed in each time step, which would lead to an even longer simulation time.
The simulation time in COMSOL on the same machine for a non-linear model with 38'139 domain elements and 2501 time-steps is 3h 20min, when using a fixed timestepping algorithm defined in the same way as in the FDM simulation.It should be noted that COMSOL implements adaptive time stepping strategies, with time steps automatically determined during the simulation to satisfy a desired error tolerance, which can improve the simulation time.The output values at the time points defined by the user are then calculated by interpolation.For the loads abruptly changing in time as it is the case of a power pulse experiment, the so-called Events Interface have to be used in COMSOL to accurately calculate the temperature response.Accordingly, explicit time events corresponding to fast transitions in the input have to be set at the beginning of a COMSOL simulation so that the algorithm selects fine enough time steps around the transition points.A similar modeling approach is to be implemented in the developed FDM-thermal model in the course of its further development.

IV. THE PROPOSED FDM THERMAL TOOL-LTSPICE ET MODELLING APPROACH
This section presents an ET modeling based on coupling a circuit simulator and the developed FDM thermal tool, which allows the time step in the thermal domain ∆t th to be selected independently from the time step in the circuit domain ∆t el .LTSpice is selected as a free commercial circuit simulator.The coupling is accomplished in an automatized way by updating an LTSpice netlist with the latest junction temperature calculated in the FDM thermal tool, and by providing the average dissipated power, calculated from the LTSpice simulation during a thermal time step, to the FDM thermal tool, as shown in Fig. 7a).As the device temperature is represented as a single parameter in the circuit domain, the average junction temperature is used as an output parameter T j from the thermal simulation, cf.Fig. 7. Considering the junction temperature as the maximum temperature at the top of the die would result in an overestimation of the temperature for most of the active region of a power device.The average temperature T avg is calculated by means of a boundary surface port, with a cross section area equals to the die active area, which selects the corresponding surface FDM nodes.In circuit-based ET simulations, only this single temperature value T avg is forwarded to the circuit simulator, and hence, it is directly available, while the temperature distribution defined by the other FDM nodes can be extracted in a postprocessing step.
The ∆t el is defined in LTspice with an adaptive time stepping algorithm, i.e. the ∆t el varies accordingly to the electrical dynamic.An integer parameter R is introduced to define how frequently the device junction temperatures are updated in LTSpice.Namely, each LTSpice simulation is run with fixed device temperatures for t el,sim = R • ∆t th , see Fig. 7b).The R parameter further decouples the circuit and thermal domains, which is beneficial in the cases when a small ∆t th is needed to sample the exact temperature profiles but the temperature change is negligible for the device electrical behavior, which is shown in more detail in Section V.The simulation time period t end , the thermal time step ∆t th and the parameter R are defined by the user at the beginning of an ET coupled simulation.

A. Verification by COMSOL ET Modeling: Conduction Mode
The accuracy of the proposed ET-FDM modeling approach is first verified with a fully-coupled COMSOL ET-FEM simulation of the HB PM shown in Fig. 2 7. Coupling of the proposed FDM thermal tool with a commercial circuit simulator: a) data transfer between the tools and b) an example of time-steps for the proposed FDM thermal tool, T j is updated in the circuit netlist every R • ∆t th .
dependent R ds,ON behavior implemented in the LTSpice compact device model provided by manufacturer was modified to consider the measured R ds,ON (T ) variability between four SiC power MOSFET dies soldered in the power module.Polynomial curve fitting was used to analytically model R ds,ON (T , I ) characteristics in COMSOL in the considered temperature and current ranges.As the temperature (T)dependence is much stronger, a polynomial expression of 4 th order is used for T-dependence and the current (I)dependence is modeled by a 1 st order polynomial function.The thermal conductivity of solder layers was adjusted according to X-ray inspection of the solder voids formed during the soldering process and the IR-camera measurements, which is explained in more detail in in [36].The IR measurements were performed with a FLIR A655sc camera using a spatial resolution of 0.14 mm and a maximum available image frequency of 200 Hz.The IR-measurements were verified by comparison with the virtual junction temperature T vj measured via a temperature sensitive electrical parameter (TSEP) [36].In the simulations, each of two DCB solder layers was separated in two regions as shown in Fig. 2a), resulting in a total of eight modeling regions for the die-attaches and baseplate solder layer.
The ET modeling in COMSOL is based on the multiphysics coupling of the partial differential equations for heat conduction and electrical currents, i.e Joule heating [15].Namely, in comparison to the proposed ET FDM modeling with heat sources uniformly located in the active die area, for the fully-coupled ET FEM modeling the heat sources are distributed in general in all elementary volumes with current conduction.Another substantial difference between the two approaches is a higher mesh density in COMSOL, since the electric current spreading requires a finer mesh than the heat equation, thus leading to a much more computational expensive model.Accordingly, for the comparison between the proposed ET modeling approach and the ET COMSOL modeling, the temperature and current dependent electrical conductivity σ el (T, I DS ) of four individual SiC MOSFETs were calibrated to match R ds,ON (T, I DS ) implemented in LTSpice, and then assigned on the top surface boundary of the SiC dies.A 4 µm thick aluminum layer representing the top metalization was implemented in the COMSOL model to enable the current spreading from the bond wires to the entire MOSFET's active area.The same thermal material properties were used in both modeling tools.
The temperature responses calculated by the proposed ET-FDM model, the ET COMSOL model and the IRmeasurements for a total heating current of 57.8A applied for 5 s are presented in Fig. 8.The maximum difference between the proposed ET FDM-LTSpice simulations and COMSOL is 0.85 K, while the maximum difference to the IR camera measurements is 1.4 K at t =5 s.Namely, the IR-temperatures shows a temperature increase after 5 s, which can be explained by a non-ideal silicone oil cooling system of the measurement equipment [36], neglected in the simulations.This effect is even more pronounced at higher temperatures, i.e. higher load currents, and hence, a more detailed thermal model should be implemented in both COMSOL and the proposed FDM tool to represent the actual behavior of the measurement system with a higher accuracy, which was not in the focus of this paper.The two ET models give close results also for a higher current pulse of 69.8 A, where the non-linearity of the thermal package model becomes relevant.A maximum temperature difference of 1.48 K is found for the entire transient, cf.Fig. 9a), while the simulated current sharing between SiC power MOSFETs is shown in Fig. 9b).The small relative difference < 1 % between the temperature simulation results with the proposed FDM-LTspice tool and COMSOL can be further explained by to the intrinsic modeling differences of the two modeling approaches.The simulation time required to obtain the results shown in Fig. 9 using the FDM-LTSPice tool is 2.5 hours with a thermal time step of 2.5 ms, updating the LTSpice circuit simulation with a new temperature input after R=4 time steps in the thermal simulation.

V. CIRCUIT-BASED ET MODELING WITH SWITCHING LOSSES
A large difference between the electrical time constants τ el in the range of nanoseconds and thermal time constants τ th from milliseconds to seconds of PE systems [13], [21], [41], [44] makes the numerical coupling between electrical and thermal aspects more challenging in terms of computational efficiency.In addition, including AC power losses, i.e. the switching losses, in a fully numerical ET simulation is not straightforward, as the switching losses depend on both device and circuit and hence, have to be calculated externally.
When considering fast switching transients, both direct simulations via equivalent thermal networks characterized by a common electrical and thermal time step, and the ET simulations with decoupling ∆t el and ∆t th lead to computationally cumbersome simulations.Accordingly, for the design optimization of PE converters, an iterative approach is preferable to evaluate the junction temperature of power devices in steady-state operation.In an iterative approach, a PE circuit is simulated for a longer time period in order to ensure steady-state system behavior, using fixed junction temperatures of power devices.The steady-state power losses are then calculated and used in the thermal simulation to find the next set of device junction temperatures to be used in the following circuit simulation.This iterative procedure is repeated until the difference between the temperature values in subsequent iterations is smaller than a specified relative error tolerance.The iterative modeling approach is on the other hand only accurate if the device temperature oscillations in the steadystate system operation are small, so that temperaturedependent parameters in both the thermal and electrical domains can be treated as constant.It should be noted that even the iterative procedure is frequently skipped in the design optimization of power converters [18], [34], [45].
An example of a 100 kHz synchronous boost converter shown in Fig. 10 is used to evaluate the above mentioned challenges of ET modeling and to show the importance of taking into account temperature dependence of thermal conductivity of package materials when estimating the junction temperature of SiC power MOSFETs during a fast switching operation.The analysis is performed by comparing an iterative procedure, an ET simulation using ANSYS Electronics Desktop, and the proposed FDM-LTspice ET approach.The 1.2 kV HB PM design presented in [46] housing a single die per HS/LS switch is used in the boost converter.For the purpose of evaluating temperature dependence of package material properties, AlN ceramic, cf.Fig. 1, was used for DCB substrate in the ET simulations.The switches S1 and S2 are modeled as two 1.2 kV SiC power MOSFETs [47].The switch S1 operates with a duty cycle of 0.542.The behavioral LTSpice device models provided by the vendor and the thermal model of the HB PM are used for the ET modeling of the boost converter.The accuracy of ET simulations depends on both compact (Spice-) device models and thermal models.However, the development and/or verification of temperature-dependent Spice models developed by device manufacturers was not in the scope of this paper.Therefore, the proposed FDM thermal tool-LTSpice modeling approach was verified by ANSYS Electronics Desktop (EDT) simulations using the same Spice-models in both environments.

A. Direct ET Modeling
As ANSYS EDT can only handle temperature-invariant thermal models, the ET analysis of the boost converter was performed in the proposed FDM thermal tool-LTSpice modeling environment and ANSYS EDT with constant material thermal properties.
1) ET Modeling τ el = τ th : ET modeling in ANSYS EDT employs two simulation environments: a circuit simulator, Simplorer, and a thermal modeling tool, Icepak.A thermal model of the HB PM is first developed in Icepak, leading to the extraction of the thermal matrix, Z ths = [Z ths,11 , Z ths,12 ; Z ths,21 , Z ths,22 ], representing thermal responses of SiC power MOSFETs S1 and S2 to a power step pulse [48].The ambient temperature as well as the initial temperature of all package layers are set to T 1 = 80 • C. The temperature T 1 was also used to calculate the package thermal material properties.In the next step, a linear temperature invariant Reduced Order Model (ROM) of the package is built using ANSYS EDT and imported in ANSYS Simplorer.However, this modeling technique does not allow: 1) to model temperature dependent material properties, and 2) to keep a direct link between the extracted thermal ROM and all physical features of the 3-D package thermal model in ANSYS Icepak.Therefore, a change in the power module structure requires a re-extraction of the thermal ROM, which makes this modeling approach less attractive for a converter design process.In the ANSYS Simplorer, the thermal model is solved in each simulation time step so the simulated temperature response corresponds to the instantaneous power dissipation.In the HB PM example, the TIM layer contributes to a thermal time constant of several seconds, so that reaching the steady-state temperature in the ET simulations was not feasible with the available resources in terms of memory.Therefore, the ET simulation in ANSYS Simplorer was performed for the initial t end = 5 ms of the boost converter operation, cf.Fig. 11 and the total simulation time was 26 min.Neglecting the effects of the actual cooling system and low thermally conductive interface layers has been exploited in literature [25], [49] to avoid long transients in ET simulations.Performing thermal simulations in every time step of the electrical domain is not required in practice, since the temperature change during a time step in the circuit domain can be regarded as negligible.Instead, the overall average temperature change during a longer electrical transient is rather of interest for power electronics applications.Accordingly, the number of thermal simulations should be kept as small as possible in order to speed up the ET simulations, which is shown in more detail on the example of ET simulations using the proposed FDM thermal tool-LTspice coupled modeling environment.
2) ET Modeling τ el = τ th : In the proposed FDM thermal tool-LTSpice modeling environment, thermal simulation was performed using the PRIMA-MOR of order eight.The boost-converter was simulated starting from T 1 .The ET simulations were performed for t end = 5 ms and different sets of thermal time steps ∆t th and parameter R as summarized in Table III and shown in Fig. 11a).Each LTSpice simulation is run with fixed device temperatures for t el,sim1 = R•∆t th .The effect of the instantaneous power dissipation on the junction temperature is observed in ET-SIM1 performing 15 thermal steps in a switching cycle of 10 µs, i.e. ∆t th = 0.67 µs, and updating the device temperature in LTSpice simulation once per switching cycle (R = 15).The results are comparable with the ANSYS modeling approach as shown in Fig. 11b).The temperature differences between the ANSYS ET simulation and the proposed coupled ET simulation ET-SIM1 is less then 1  be mainly explained by the differences of thermal models and the mesh.
A longer ∆t th implies that power losses used as the input for each thermal simulation step are calculated by averaging instantaneous power losses over a longer time interval.In Fig. 11c), the simulation results of ET-SIM 1-3 are compared for the last 10 switching periods.This comparison demonstrates the impact of averaging power dissipation during a single switching cycle (ET-SIM2) and 125 switching cycles (ET-SIM3), which corresponds to R = 1 and ∆t th = 10 µs and 1.25 ms, respectively.As shown in Fig. 11c), the information about fast temperature oscillations is lost for a longer ∆t th and the modeling error slightly increases.The simulation times presented in Table III point out, however, that the computational cost decreases significantly by increasing ∆t th .The temperature swing within a switching period of the simulated boost converter is very low, i.e. < 1 • C. Accordingly, if this small temperature dynamics is not of interest for the design of the power converter, the computation time of ET analysis can be decreased from several hours to ≈ 5 min by using a longer ∆t th equal to 125 switching cycles, i.e. ∆t th = 1.25 ms.
Another way to reduce the computation time is to run the LTSpice simulation after performing R thermal time steps in the FDM thermal tool.The ET simulations, ET-SIM4 and ET-SIM5, were performed with ∆t th = 250 µs, and R = 60 and R = 7500, respectively.In Fig. 11d), an almost perfect matching between the simulation results of ET-SIM1, ET-SIM4 and ET-SIM5 points out that even running only the LTSpice simulation once during 5 ms is acceptable for evaluating the average junction temperature for the first 5 ms.Namely, the change of the converter's electrical behavior in the temperature range 80−102 • C does not affect significantly the temperature response.
The coupling between LTSpice and the FDM tool contributes significantly to a longer simulation time.Particularly, the computational cost of coupling is mainly determined by data exchange between the simulators and slow circuit simulations of mission profiles containing a large number of fast switching transients.LTSpice as a Spicebased simulator allows modeling device switching behavior more accurately than the circuit simulators dedicated to PE applications.A less computationally expensive interface link between the two simulators is needed to further improve the coupling.Accordingly, for the design of power converters, the simplifications of device models can be adopted, controlling the trade-off between the accuracy and simulation time more precisely.The presented analysis shows the capabilities of the proposed FDM-LTspice modeling, while also indicating the main challenges of efficiently coupling the circuit and thermal domains.

B. Iterative ET Modeling Approach
As the steady-state device temperatures T j1,ss and T j2,ss could not be calculated in practice by the fully coupled ET simulations described in the previous section, an iterative approach was employed to find T j1,ss and T j2,ss taking into account the temperature-dependent thermal parameters of package and device materials.The electrical simulation in LTSpice was initialized with the specified values of inductor current and output voltage in order to skip the electrical transient.During the iterative approach, 500 switching cycles (5 ms) are simulated in every circuit simulation with fixed temperatures of S1 and S2.The steady-state power losses are calculated as an average over the last 50 switching cycles (0.5 ms) and then imported in the proposed FDM thermal tool to calculate T j1,ss and T j2,ss for the given power inputs.The iterative analysis was conducted with two initial temperatures of 80 This analysis shows the importance of considering temperature dependent thermal conductivities for the temperature estimation of fast switching power devices operating in a higher temperature range, which in turn impacts the design optimization of the cooling system.Moreover, it shows that an iterative approach is more efficient for estimating the temperature of power devices than a fully coupled ET circuit-based simulation.However, it is applicable only for small oscillations of device junction temperature under steady-state conditions.Power semiconductor devices can experience temperature oscillations with higher amplitudes in steady-state operation in power cycling tests, inverters for aircraft internal distribution systems, low-speed motor drives or induction motors [45], [50], [51].For these applications, the ET modeling approach based on the developed FDM thermal tool and a circuit simulator is highly beneficial for accurate prediction of device temperatures, and hence, accurate virtual prototyping.

VI. CONCLUSION
This paper verifies the importance of including the temperature dependence of the thermal conductivity of power semiconductor and package materials for an accurate temperature prediction of SiC power devices operating in a wide temperature range.The temperature prediction becomes less accurate by assuming temperature-invariant material properties.A fully coupled circuit-based ET modeling method using the developed FDM thermal tool and LTSpice is implemented to enable the prediction of the temperature and current distribution of power devices within multi-chip power modules in a computationally efficient way, while including temperature-dependent thermal conductivity.An example of a SiC power MOSFET half-bridge power module is used to verify the modeling capabilities of the FDM-LTSpice simulations in comparison to the wellknown commercial thermal modeling tools of COMSOL and ANSYS, and IR camera measurements.The computational complexity of fully coupled circuit-based ET simulations is compared to an iterative ET modeling approach for a more accurate temperature prediction of SiC power devices with dominant switching losses.

Fig. 2 .
Fig.2.The half-bridge power module used for the analysis of temperaturedependent material thermal properties: a) top view and b) cross section.The four dies are labeled as high side (HS) and low side (LS).

Fig. 3 .
Fig. 3. Power step response of the LS2 die soldered in the half-bridge power module shown in Fig. 2 for four different sets of material properties: (SIM1) temperature dependent k(T ) and c p (T ), (SIM2) k(T ) and c p =const., (SIM3) c p (T ) and k=const., and (SIM4) k=const.and c p =const: a) the selfimpedance Z th11 for P heat = 100 W, b) the mutual-impedance Z th21 for P heat = 100 W, c) Z th11 for P heat = 200 W d) Z th21 for P heat = 200 W.

Fig. 5 .
Fig. 5. Comparison of the proposed FDM-SBC approach with a commercial FEM tool, power pulse response of the HB PM (Fig. 2) for a) 50 W and b) 150 W applied to the 4 dies.In b) the response for k(T = 100 • C) is shown for comparison.

FEMFig. 6 .
Fig.6.Impact of the number of time-steps (table II) on the temperature profile of LS2 simulated with the proposed FDM-SBC approach for P in = 150 W applied to the 4 devices.The non-linear FEM simulation from COMSOL is shown as reference.
and IR camera measurements.In this example, DC power losses, i.e. the conduction losses, are the dominant heat source.The onstate resistances R ds,ON (T ) of four SiC MOSFET dies were first characterized in the wide temperature range [25 • C, 225 • C] using a wafer prober MPI TS2000-HP and a Keithley curve tracer 2600-PCT-4B.The current-and temperature-

Fig. 8 .
Fig.8.The HB PM temperature response to a current pulse of 57.8 A. Comparison between the proposed ET-FDM approach, the ET-FEM model and IR-measurements.

Fig. 9 .
Fig. 9. ET simulation of the HB PM for a current pulse of 69.8 A. Comparison between the proposed ET-FDM approach and the ET-FEM model, a) temperature and b) current profiles.

Fig. 10 .
Fig. 10. Circuit schematic of the simulated 100 kHz synchronous boost converter with the output power P out = 13.5 kW, the dead time t dead = 200 ns, input voltage V in = 300 V, output voltage V in = 650 V. S1 and S2 are 1.2 kV 40 mΩ SiC MOSFETs.

Fig. 12 .
Fig. 12. Iterative coupling of LTspice and the proposed FDM thermal tool for calculating the steady-state thermal behavior of a 100 kHz synchronous boost converter with two initial junction temperatures of 80 • C and 225 • C and three sets of thermal conductivities: a) k(T ), b) k(T = 80 • C), and c) k(T = 225 • C).
• C and 225 • C. The steady-state temperature was reached after four iterations as shown in Fig.12.In this study, three different sets of thermal conductivities were used: 1) temperature dependent thermal conductivity k(T ), Fig.12a), 2) constant thermal conductivity k(T = 80 • C) Fig.12b), and 3) constant thermal conductivity k(T = 225 • C), Fig.12c).The steadystate temperatures of S1 and S2 were determined with an error tolerance of less than 1 K.The steady-state temperatures estimated by using k(T = 80 • C), k(T = 225 • C) and k(T ) are 194.5 • C, 211 • C and 205 • C, respectively, for S1 and 150 • C, 156 • C and 152.5 • C, respectively, for S2.Accordingly, by using a constant thermal conductivity, the temperature of S1 is either underestimated by 5.1 % or overestimated by 3 %.Eight electrical and eight thermal simulations i.e. four iterations for each initial condition, were performed to calculate the steady-state temperatures in the observed example.The electrical simulation in LTSpice took ≈ 1 min, while the thermal simulation in the FDM tool ≈ 6 s.

TABLE I ANALYTICAL
EXPRESSION OF TEMPERATURE-DEPENDENT THERMAL PROPERTIES OF MATERIALS OF FIG. 1 AND USED FOR THE DUT OF FIG. 2

TABLE II SIMULATION
TIMES OF THE PROPOSED FDM-SBC APPROACH (MODEL WITH 37500 FDM NODES) FOR DIFFERENT TIME STEPS.

TABLE III DEFINITIONS
OF THERMAL TIME STEPS IN THE PROPOSED FDM THERMAL TOOL-LTSPICE COUPLED SIMULATIONS.