Instability Effect of PLL on Voltage-Source Converters during Grid Faults: Large-Signal Modeling and Design-Oriented Analysis

The phase-locked loop (PLL) is widely used in voltage source converters (VSCs) for the purpose of grid synchronization. This paper presents a design-oriented analysis of the impact of the PLL on the synchronization stability of VSCs during severe grid faults. By using the phase portrait, the large-signal nonlinear responses of the PLL during grid faults are characterized with different controller parameters. It is revealed that the synchronous reference frame-PLL (SRF-PLL) fails to remain synchronism with the grid when the system only has one equilibrium point during the fault. Moreover, there will be no synchronization stability problems if the first-order PLL is adopted in a system with equilibrium points during grid faults. Consequently, an adaptive PLL is proposed to stabilize the synchronization dynamics, which enables VSCs to operate with the SRF-PLL during normal operations, yet with the first-order PLL during grid transients. Time-domain simulations and experimental tests are given to validate the effectiveness of the theoretical analysis and the performance of the adaptive PLL.


I. INTRODUCTION
Voltage source converters (VSCs) are increasingly used in electric power grids for the efficient energy consumption and the renewable energy generation [1].To secure a reliable operation of the power system, the fault ride-through capability of VSCs is required by grid codes [2], [3], i.e., VSCs are required to remain connected with the grid during grid faults for a certain period of time, and the reactive power needs to be injected into the grid for supporting the grid voltage recovery.A typical reactive current profile required by the grid code for the fault ride-through is given in Fig. 1 [2].I q /I N (%) v g (p.u.) 0 0.5 1 −100 0.9 1.1

Dead band
Fig. 1.Typical reactive current profile for the fault ride-through [2].
A widely used control scheme for VSCs is the vector current control, where the phase-locked loop (PLL) is used for the purpose of grid synchronization [4].Apparently, the PLL should be able to remain synchronization with the grid even during grid faults.However, a recent report from the North American Electric Reliability Corporation (the NERC) shows that the PLL may lose synchronization with the grid during severe grid faults, which is one cause of an accidental trip of 900 MW solar photovoltaic inverters in Southern California [5].Therefore, the analysis of the impact of the PLL on the synchronization stability of the VSC during grid faults is urgently demanded.
In recent years, a number of research works have been reported on the effect of the PLL on the stability of grid-connected VSCs.It is found that the synchronous reference frame PLL (SRF-PLL) may deteriorate the stability of VSCs by introducing a negative incremental resistance at low frequencies [6]- [8].The frequency coupling dynamics of VSCs introduced by the PLL have also been explicitly revealed in [9].However, those research works are focused on the small-signal stability of VSCs, where the PLL is linearized around an equilibrium point, and thus the conclusions cannot be extended for assessing the synchronization stability of VSCs during grid faults (large disturbances), in which the nonlinearity of the PLL should be considered.In [10], a quasi-static large-signal model of the SRF-PLL is developed, which reveals that the VSC will lose synchronism with the grid if the PLL does not have equilibrium points during grid faults.In contrast, in the case that the PLL has equilibrium points during grid faults, the synchronization stability of the VSC is analyzed by means of the equal-area criterion (EAC) in [11].Yet, this EAC-based analysis is only valid when the proportional gain (Kp) of the PLL is zero, which is not a justified assumption in practice [12].Moreover, the EAC may lead to the inaccurate stability assessment for the PLL with a nonzero proportional gain [12].
To address the synchronization stability problem, an adaptive current injection method is proposed in [13]- [14], where the ratio of the injected active and reactive current is required to be equal to the ratio of the grid resistance and inductance.
Yet, the grid impedance is usually time varying and unknown in practice, which challenges the effectiveness of the adaptive current injection method.Moreover, with this method, the VSC may fail to inject 1 p.u. reactive current during severe grid faults, which is required by the grid code [2]- [3], as shown in Fig. 1.Another adaptive active current injection method is based on the output frequency of the PLL [15]- [16].However, it may also fail to inject 1 p.u. reactive current during severe grid faults, which violates the grid code.
In order to comply with the grid code and meanwhile enhance the synchronization stability of VSCs, this paper presents a design-oriented analysis based on the large-signal model of the PLL, and an adaptive PLL is proposed for stabilizing the synchronization behavior of VSCs during grid faults.A part of the research work has been presented in [12].Depending on the depth of grid voltage sags, the PLL may have two equilibrium points, one equilibrium point or even no equilibrium points during the fault [14].The loss of synchronization (LOS) is inevitable if there is no equilibrium point [10].Hence, this paper only considers the synchronization stability of VSCs with equilibrium points during the fault.
First, considering that the PLL has two equilibrium points during grid faults, the large-signal dynamic response of the system is characterized by means of the phase portrait, where the influence of PLL parameters on the synchronization stability of the VSC is explicitly identified.It is revealed that even if the PLL is designed with the positive damping ratio, the overshoot in the dynamic response of the output phase angle of the PLL may still destabilize the system.This insight cannot be derived from the small-signal analysis of the PLL effect [4], [17], [18].Hence, the synchronization stability of the VSC can be enhanced by reducing the phase overshoot, which is realized by increasing the damping ratio of the PLL.
Second, when there is only one equilibrium point during the fault, the SRF-PLL cannot guarantee the synchronization stability of VSCs no matter how large the damping ratio is adopted, which will be demonstrated in this paper.It is also found that if the SRF-PLL is reduced as a first-order PLL, there will be no synchronization stability problem, as long as it has equilibrium points during grid faults.Yet, the first-order PLL suffers from the steady-state phase tracking error when the grid frequency deviates from its nominal value [19].Hence, an adaptive PLL, which enables VSCs to operate with the SRF-PLL in the normal operation, and to be reduced as the first-order PLL during grid transients, is proposed in order to guarantee the synchronization stability of the VSC.It is noted that the proposed method has no requirement of changing the injected active and reactive current profile, and thus the risk of violating the grid code can be avoided.Lastly, time-domain simulations and experimental tests are given to validate the effectiveness of the theoretical analysis and the performance of the adaptive PLL.
It is worth noting that this paper is only focused on the synchronization stability impact of the SRF-PLL under three-phase balanced faults, since the SRF-PLL is widely deemed as the basic form of other advanced PLLs, such as decoupled double synchronous reference frame PLL (DDSRF-PLL) [20], delayed signal cancellation based PLL (DSC-PLL) [21]- [22], second-order generalized integrator based PLL (SOGI-PLL) [23]- [24], etc.

II. GRID-CONNECTED VOLTAGE SOURCE CONVERTERS
A. System Description Fig. 2 illustrates the simplified one-line diagram of a three-phase VSC using the typical vector current control, where Lf is the output filter of the converter and Zline represents the line impedance.The voltage at the Point of Common Coupling (PCC) is measured for synchronizing the VSC with the grid by means of the PLL.Idref and Iqref are current references for the active current and the reactive current.The Proportional+ Integral (PI) controller is used for the current regulation in the dq-frame to guarantee a zero steady-state tracking error [17].
In general, the timescale of the PLL is around 100 ms [10], [25], which is well decoupled from the timescale of the current control loop (i.e., 1 ms -10 ms) [10], [25].Hence, the dynamics of these two loops can be analyzed individually [10].
Therefore, in the synchronization stability analysis of the PLL, the current loop is considered as a unity gain with the ideal reference tracking, and thus the converter shown in Fig. 2 can be simplified as an ideal current source, and its phase angle is determined by the PLL [10], [25].

B. Mathematical Model of the PLL Considering Line Impedance Effect
Fig. 4 depicts the block diagram of the commonly used SRF-PLL [4].The three-phase voltages at the PCC are sampled and then transformed into the dq frame.The q-axis voltage is regulated by a PI controller for the phase tracking [4].The PCC voltage in the dq frame can be expressed as [4] ( ) ( ) Based on Fig. 4 and (1), the dynamic equation of the PLL can be expressed as ( ) where ωgn is the nominal grid frequency.Kp and Ki are the proportional and the integral gain of the PI regulator, respectively.
In the steady state, the integrator of the PI controller forces vPCCq to become zero, and hence θPLL=θPCC [4].
As shown in Fig. 3, vPCC is determined by the GCP voltage and the current flowing through the line impedance.The relationship between vPCCd, vPCCq, vgcp, ig and Zline can then be expressed as follows: ( which describes the dynamics of the PLL considering the line impedance interaction.The more intuitive results can be obtained by rewriting (6) in the measured dq frame of the PLL.Considering the line impedance as an inductance in series with a resistance, i.e., Zline=Rline+jXline, where Rline=Zlinecosθline and Xline=Zlinesinθline. Substituting these into (6), together with Id=Igcosφ and Iq=Igsinφ, which yields where vzq represents the q axis component of the voltage across the line impedance, while vgcpq represents the q axis component of the GCP voltage, and vPCCq=vzq+vgcpq.Based on (7), the equivalent diagram of the PLL considering the effect of the line impedance is plotted in Fig. 5.

A. Mechanism of the LOS of the VSC with Two Equilibrium Points during the Fault
Eq. ( 7) and Fig. 5 characterize the large-signal nonlinear dynamic behavior of the PLL, from which the mechanism of the LOS during grid faults can be elaborated.From (7) and Fig. 5, it is clear that vPCCq=0, i.e., IdXline+IqRline = Vgcpsinδ in the steady state.During the normal operation, the VSC is operated with the unity power factor, i.e., Id=Imax, Iq=0, where Imax represents the rated current of the VSC.
Therefore, IdXline+IqRline= ImaxXline.The curve of Vgcpsinδ before the grid fault is plotted as the dashed line in Fig. 6.Assuming that the system initially operates at the equilibrium point a at the steady state, where ImaxXline = Vgcpsinδ0 , as shown in Fig. 6.
During the fault, the magnitude of the GCP voltage drops to Vgcp1 and the curve of Vgcp1sinδ is plotted as the solid line in Fig. 6.The VSC needs to inject the reactive current to support the grid voltage during the fault.According to the grid code [2], the VSC should provide 2% reactive current per percent of the voltage drop.When the GCP voltage is below half of the nominal value, the VSC is thus required to inject the full rated reactive current, i.e., Id=0, Iq= -Imax, which leads to IdXline+IqRline= -ImaxRline.Obviously, if -ImaxRline < -(Vgcp1sinδ)max = -Vgcp1, the PLL does not have any equilibrium points and consequently the VSC loses the synchronization with the grid, which has been pointed out in [10].However, the LOS may still exist even if the PLL has equilibrium points during the fault.Note that the PLL has two equilibrium points if -ImaxRline >-Vgcp1, as the point c and the point e shown in Fig. 6, and has one equilibrium point if −ImaxRline = -Vgcp1.The latter case will be discussed in the last part of this section.Here only the case that the PLL has two equilibrium points during the fault is considered.
The operation point of the PLL moves from the point a to the point b when the fault occurs.As -ImaxRline < Vgcp1sinδ0 at the point b, it is known from Fig. 5 that the output frequency of the PLL starts to decrease, resulting in a decrease in δ.The frequency continues to decrease until it reaches the stable equilibrium point (SEP) c, where -ImaxRline =Vgcp1sinδ1, as shown in Fig. 6.Yet, as the output frequency of the PLL is below the grid frequency ωg at the point c, the phase δ continues to decrease.Then the output frequency of the PLL begins to increase after the point c due to the fact that -ImaxRline > Vgcp1sinδ.
Consequently, two possible operation scenarios can take place: 1) The output frequency of the PLL recovers to the grid frequency before the unstable equilibrium point (UEP) e, e.g., at the point d shown in Fig. 6(a).As -ImaxRline >Vgcp1sinδm still holds at the point d, the output frequency of the PLL further increases and results in an increase of δ.Thus, the operating point retraces the Vgcp1sinδ curve and finally reaches the SEP c after several cycles of oscillation, which implies that the system becomes stable, as shown in Fig. 6(a).
2) The output frequency of the PLL is still below the grid frequency even at the UEP e, as shown in Fig. 6(b).Then, the output frequency turns to decrease again after the point e, due to the fact of -ImaxRline < Vgcp1sinδ, and δ keeps decreasing.The PLL eventually loses synchronism with the power grid, as shown in Fig. 6(b).

B. Basic Concept of the Phase Portrait
It is clear that the assessment of the LOS requires extracting the large-signal nonlinear dynamics of the PLL.However, it is difficult to solve nonlinear equations explicitly [26].To tackle this challenge, the concept of the phase portrait has been introduced in [26] as a graphical way to analyze the dynamics of the first-and second-order nonlinear systems.In this work, the phase portrait is adopted to characterize the influences of controller parameters on the large-signal dynamics of the PLL.
The basic concept of the phase portrait is illustrated based on a general nonlinear differential equation, which is given by ( ) where x is the state variable of concern.Instead of solving x analytically, the x x −  curve can be readily plotted, as shown by the example in Fig. 7, which is called as the phase portrait [26].At each point, the changing trend of x is determined by its derivative x  , e.g., x will increase (moving rightwards in Fig. 7) if 0 x >  , and will decrease (moving leftwards in Fig. 7) , which are indicated by the arrows in Fig. 7. Thus, once the initial condition is determined, the system trajectory can be easily obtained based on the phase portrait.

C. Impacts of PLL Parameters on the Synchronization Stability of the VSC with Two Equilibrium Points during the Fault
As a second-order dynamic system, the dynamic response of the PLL are determined by its damping ratio (ζ) and setting time (ts) [17], and their relationships with controller parameters are listed as follows [17]: Applying the derivation to both sides of (7a), and considering the relationship , where ωn is the nominal grid frequency, which yields: Based on (11), the phase portraits of the PLL with different damping ratios and settling times during the grid fault can be plotted.For illustrations, three typical trajectories are given, which are shown in Fig. 8. From these phase portraits, two important conclusions can be drawn:   Therefore, the block diagram in Fig. 5 can be equivalently transformed to Fig. 9, where a positive feedback loop is formed.It is known from (10) that the smaller settling time corresponds to a larger Kp, which consequently increases the loop gain of the positive feedback loop, and thus the synchronization stability of the VSC is further deteriorated.
However, if the line impedance is pure resistive, whose value is independent on the output frequency of the PLL, the positive feedback loop does not exist and the settling time has no influence on the synchronization stability of the VSC, which has been clarified in our previous work [12].2) Fig. 8 (b) illustrates that the synchronization stability of the VSC can be enhanced by increasing the damping ratio of the PLL.From the analysis based on Fig. 6 (b), it is known that the LOS takes place when the dynamic response of the PLL has a phase overshoot to cross the UEP e.This phase overshoot can be reduced by increasing the damping ratio [26], and thus the synchronization stability of the VSC is enhanced.It is worth noting that this insight cannot be revealed from the small-signal analysis, where the PLL is modeled as the second-order linear system [4], and is kept stable due to the positive damping ratio contributed by Kp>0 and Ki>0.In contrast, the LOS may still happen during the large disturbances (e.g., grid faults), even if the damping ratio is positive.Hence, instead of setting the damping ratio as 0.707 based on the small-signal model of the PLL [4], [17]- [18], the tuning of PLL parameters needs to be further optimized for stabilizing the large-signal behavior of the PLL.

D. Synchronization Stability of the VSC with One Equilibrium Point during the Fault
In this part, the large-signal response of the PLL under the condition of -ImaxRline = -Vgcp1 is discussed.In this case, the SEP c and the UEP e merge as one point, as shown in Fig. 10.Thus, the output frequency of the PLL has to recover to the grid frequency at the point c(e) in order to remain the synchronism, i.e., 0 =  δ at the point c(e).Consequently, the dynamic response of δ must have an overdamped response for a stable operation, as shown in Fig. 10 (a).Any small phase overshoots in the dynamic response make the system crossover the point c(e), and eventually results in the LOS, as shown in Fig. 10 (b).The derivative of δ represents the deviation of the PLL-measured frequency from the grid frequency, which can be derived by applying the derivation on both sides of (7a), i.e.,

( )( ) ( )( )
where ( ) ( ) As shown in Fig. 10, -ImaxRline = Vgcp1sinδ holds at the equilibrium point c(e).Therefore, it is known from ( 13) that 1 0 =  δ at the point c(e).Yet, -ImaxRline < Vgcp1sinδ always holds during the period when the operating point of the PLL moves from the point b to the point c(e) under grid faults, as shown in Fig. 10.This makes the integration of (-ImaxRline − Vgcp1sinδ) smaller than zero at the point c(e).Hence, it is known from ( 12)-( 14) that the condition δ δ δ δ always holds at the point c(e) as long as Ki>0.This fact implies that the SRF-PLL will crossover the point c(e), and the LOS is inevitable.
Hence, the LOS cannot be avoided for the VSC with the SRF-PLL when there is only one equilibrium point during the fault.

A. Synchronization Stability Enhancement by using the First-order PLL during Grid Transients
As pointed out in part D of section III, the LOS of the VSC with only one equilibrium point during the fault is resulted from the integrator of the PI regulator in the SRF-PLL, and this problem can be solved by letting Ki=0, and thus ( ) always holds at the SEP, and the synchronization of the VSC can be remained as long as the equilibrium point exists.
Actually, setting Ki=0 makes the SRF-PLL become the first-order PLL (also called as the Type-I PLL [19]), as shown in Fig. 11.The first-order PLL has no LOS problem during grid faults as long as it has equilibrium points, which is an attractive feature.However, it suffers from the steady-state phase tracking error when the grid frequency deviates from its nominal value [4], [19], which limits its usage to applications where the frequency is fixed or has small variations around its nominal value [19].To tackle this challenge, an adaptive PLL is proposed in this paper for the synchronization stability enhancement.
The basic idea of this method is to let the VSC operate with the SRF-PLL during the normal operation in order to achieve the zero phase tracking error, and the SRF-PLL is switched to the first-order PLL during grid transients, which guarantees the synchronization stability of the VSC.
where Ki0 is the designed integral gain of the PLL during the normal operation, ωROCOF represents the ROCOF of the PLL, which is obtained by applying derivation to its output frequency, and a low-pass filter (LPF) is added after the derivation in order to attenuate the high-frequency noise.ROCOF1 and ROCOF2 represent different threshold values.Δωmax represents the output frequency limit of the PLL.

B. Comparison of Synchronization Stability Performance of the VSC with Different PLLs
In this part, the synchronization stability of the VSC with different PLLs are compared.The main parameters of the system is given in Table I.The GCP voltage that drops below half of the nominal voltage is considered during grid faults.
Based on the grid code, Id=0, Iq= -Imax is required during the fault [2]- [3], the lowest voltage which may guarantee the synchronization stability of the system in theory can be calculate as Vgcpmin=ImaxRline=0.1 pu, i.e., when the voltage drops below 0.1 p.u., the PLL does not have equilibrium points and the LOS is inevitable.

Im
Magnitude of the rated grid current 15.5 A (1)

Lf
Inductance of the output filter of the VSC 3 mH (0.096)

Rline
Line resistance 1 Ω (0.1) The control parameters of the PLL in three different cases are summarized in Table II.In cases I and II, the SRF-PLL is adopted during the normal operation and grid faults.The difference is that the damping ratio is set as 0.5 in the case I, while it is set as 1.5 in the case II.In the case III, besides using parameters in the case II, the adaptive PLL shown in Fig. 12 is further adopted to enhance the synchronization stability of the system.In this paper, ROCOF1= 200Hz/s, t1=1ms, ROCOF2=5 Hz/s, t2=5ms are chosen for the adaptive PLL.The large-signal nonlinear responses of different PLLs are analyzed by using phase portraits, which are plotted based on the dynamic equation given in (11).Different depths of voltage sags are evaluated and three typical scenarios are given, as shown in Fig. 13.It is shown that the system remains synchronization in all three cases when the GCP voltage drops to 0.2 pu, as shown in Fig. 13 (a).With the parameters in the case I, the LOS occurs when the GCP voltage drops to 0.14 pu, as shown in Fig. 13 (b), while the synchronization can still be remained when the parameters of the case II are adopted.The result of Fig. 13 (b) clearly shows that the synchronization stability of the system can be enhanced by the increased damping ratio of the PLL.Moreover, when the GCP voltage drops to the theoretically lowest voltage limit, i.e., 0.10 p.u., the synchronization can only be remained by using the adaptive PLL, as shown in Fig. 13(c).The result in Fig. 13(c) further validates the effectiveness of the adaptive PLL proposed in this paper.

A. Simulation Results
To validate the theoretical analysis, time-domain simulations are carried out in the MATLAB/Simulink and PLECS blockset with the switching circuit model shown in Fig .2. The parameters given in Table I and Table II are adopted.The output frequency limit of the PLL is set as 40 Hz~60 Hz.In the normal operation, the VSC operates with Id=Imax, Iq=0.When the GCP voltage drops more than 50% of the nominal voltage, the VSC injects rated reactive current the grid to support the grid voltage, i.e., Id=0, Iq= −Imax.Fig. 14 shows the simulation results of the VSC when Vgcp drops to 0.20 p.u.It can be seen that the VSC with all three different PLLs can be kept synchronized in this scenario, which agrees with the phase portrait analysis provided in Fig. 13(a).Moreover, for the adaptive PLL, the Ki switches to zero when the ROCOF of the PLL reaches the threshold, and switches back to its designed value when the VSC comes to the new steady state, as shown in Fig. 14 (c).It is clear that the seamless transfer between the normal operation and the transient operation is guaranteed for the proposed adaptive PLL.Fig. 15 shows the simulation results of the VSC when Vgcp drops to 0.14 p.u.It can be seen that the PLL with parameters ζ=0.5, ts=0.1scannot remain synchronization with the grid during the fault.The output frequency of the PLL is saturated at its lower limit (40Hz) and it cannot recover to the grid frequency after the fault, resulting in a continuous decreasing of δ, as shown in Fig. 15 (a).However, the VSC with other two designed PLLs can still be kept synchronized with the grid during the fault.The simulation results agree well with the phase portrait analysis provided in Fig. 13(b).Fig. 16 shows the simulation results of the VSC when Vgcp drops to 0.10 p.u.It can be seen that only the VSC with the adaptive PLL can be kept synchronized in this scenario, which agrees well with the phase portrait analysis provided in Fig. 13 (c).

B. Experimental Results
To further verify the simulation results, the experimental tests are carried out with a 10 kVA three-phase grid-connected converter.The experimental setup is shown in Fig. 17.The circuit used in the experiment is completely identical to that in  The VSC operates with Id=Imax, Iq=0 during the normal operation and Id=0, Iq= −Imax when Vgcp drops more than 50% of the nominal voltage.It can be seen that the VSC with all three different designed PLLs can be kept synchronized when Vgcp drops to 0.20 p.u., as shown in Fig. 18.However, the PLL with parameters ζ=0.5, ts=0.1scannot remain synchronization with the grid when Vgcp drops to 0.14 p.u.The output frequency of the PLL is saturated at the lower limit (40Hz) and cannot recover to the grid frequency after the fault, as shown in Fig. 19 (a).Moreover, only the VSC with the adaptive PLL can be kept synchronized when Vgcp drops to 0.10 p.u., as shown in Fig. 20 (c).It can be concluded that the synchronization stability of the VSC can be improved by properly increasing the damping ratio of the PLL, and it can be further enhanced by using the adaptive PLL.The experimental results here are in well agreement with the theoretical analysis and the simulation results given in Fig. 14-16.The major findings of the paper are summarized as follows:

Fig. 2 .
Fig. 2. A simplified one-line diagram of a grid-connected VSC with the PLL and the current control scheme.

Fig. 3 Fig. 3 .
Fig.3shows the equivalent circuit of the VSC, where φ is the angle difference between the PCC voltage vPCC and the grid current ig, which is also called the power factor angle.Ig is the amplitude of the grid current.Vgcp, θgcp are the amplitude and the phase angle of the voltage at the grid connection point (GCP), while VPCC, θPCC are the amplitude and the phase angle of the PCC voltage.θPLL is the phase angle detected by the PLL, and θPLL=θPCC is expected in the steady state.θline represents the line impedance angle.

Fig. 5 .
Fig. 5.The equivalent diagram of the SRF-PLL considering the effect of the line impedance.

Fig. 6 .
Fig. 6.Dynamic response of the PLL when the magnitude of the GCP voltage drops to Vgcp1.(a) Stable case.(b) Unstable case.

Fig. 7 .
Fig. 7.An example of the phase portrait.

1 )
Fig. 8(a) shows that the reduced settling time of the PLL jeopardizes the synchronization stability of the VSC.This is resulted from the frequency-dependent nature of the line reactance, which inherently introduces the positive feedback loop.Considering the relationship vzq in 7(b) can be rewritten as vzq=IdωnLline+IqRline+Id  line L δ .

Fig. 9 .
Fig. 9. Equivalent transformation of the block diagram of the SRF-PLL considering the effect of the line impedance.

Fig. 10 .
Fig. 10.Dynamic response of the PLL when the magnitude of the GCP voltage drops to Vgcp1.(a) Stable case (b) Unstable case

Fig. 2 .
Fig. 2. The parameters and test cases applied in experiments are same with that used in the simulation.The control algorithm is implemented in the DS1007 dSPACE system, where the DS5101 digital waveform output board is used for generating the switching pulses, and the DS2004 high-speed A/D board is used for the voltage and current measurements.The active/reactive current and the output frequency of the PLL are outputted through the DS2102 high-speed D/A board.A constant dc voltage supply is used at the dc-side, and a 45 kVA Chroma 61850 grid simulator is used to generate the grid voltage.
Phase portrait of the PLL when Vgcp drops from 1 p.u. to 0.6 p.u.Based on the grid code, it is required that Id=0.6 p.u. and Iq=−0.8 p.u. after the fault.