A Hybrid Cockcroft–Walton/Dickson Multiplier for High Voltage Generation

This paper presents a voltage multiplier topology that is a hybrid between a Cockcroft–Walton multiplier and a Dickson charge pump. The Cockcroft–Walton structure exhibits significant output voltage drop under load as the number of multiplier stage increases. This is because all coupling capacitors are connected in series. Dickson charge pump mitigates this issue by connecting all capacitors in parallel. But this solution comes at the expense of large capacitor voltage stress at the last multiplier stage. The proposed hybrid structure arranges some capacitors in parallel and others in series, thereby achieving low output voltage drop and low capacitor voltage stress at the same time. We develop a model that predicts hybrid multiplier's performance and validates it experimentally. We also demonstrate a 60–2.25 kV dc–dc converter based on a 16-stage hybrid voltage multiplier which achieves a voltage gain of 12.8 while keeping the highest capacitor voltage stress to 660 V.


I. INTRODUCTION
High-voltage power supplies are crucial in many medical and industrial applications. Applications include X-ray imaging [1], neutron radiography [2], particle acceleration [3], and electrostatic air filtering [4]. This paper presents a new voltage multiplier topology that is suitable for high-voltage dc generation.
Cockcroft-Walton multiplier [5] (also known as Greinacher multiplier [6] and Villard cascade) is a switched-capacitor circuit that generates a high-voltage dc from a low-voltage ac. This circuit comprises many units of half-wave voltage doublers stacked in series. Those cascaded voltage doublers form a long string of diodes which is tapped from intermediate nodes via coupling capacitors. Besides Marx generator, Cockcroft-Walton is arguably the most popular solid-state high-voltage generator topology [7]- [10].
The ideal case is when the coupling capacitance is large enough so that negligible voltage drop occurs on the capacitor. In that case, the output voltage is simply the peak-to-peak amplitude of the input ac voltage multiplied by the number of cascaded voltage doublers, or simply the number of stages. Since all capacitors and diodes are under the same voltage stress, it is easy to make full use of every device's voltage limits. Unfortunately, the output voltage of a Cockcroft-Walton multiplier quickly 'sags', i.e., deviates from the ideal value, as the number of stage increases [11]. This is because the output impedance adds up rapidly as more coupling capacitors are connected in series.
This material is based upon work supported by the National Science Foundation under Grant No. 1808489.
Jun Yang conducted this research while he was a visiting scholar at Stanford University.
The rapid increase of the Cockcroft-Walton multiplier's output impedance was one of the main motivations for the development of Dickson charge pump [12]. (Some like to reserve the name 'Greinacher' for this topology [13] since the circuit appears alongside the Cockcroft-Walton structure in Greinacher's paper [6].) Dickson is widely used both in integrated circuits to generate a voltage that is several times higher than the supply voltage [12], [14], and in discrete power converters [15], [16]. Coupling capacitors are connected to the diode chain in parallel instead of series. Therefore, only one capacitor exists between the input port and each intermediate node of the diode chain, regardless of the number of stages. The main shortcoming of Dickson topology is, however, that the coupling capacitor at the last stage (closest to the output port; farthest from the input port) needs to withstand voltage stress that is equivalent to the charge pump output voltage.
Oftentimes, high-voltage capacitors are more readily available than high-voltage diodes. In such cases, it is better to choose Dickson topology over Cockcroft-Walton topology. If the output voltage needs to be higher than the coupling capacitors' voltage rating, one may consider stacking multiplier stages in Dickson structure until the output voltage reaches the capacitor voltage limit, then switch to Cockcroft-Walton structure and continue stacking additional stages. This idea is the inspiration of our study.
The paper proceeds as follows. Section II analyzes a well-known two-stage Cockcroft-Walton multiplier example in order to help readers understand discussions throughout the paper. Readers who are familiar with the operation of a voltage multiplier may skip this section without loss of continuity. Section III presents a topology that is a hybrid of a Cockcroft-Walton multiplier and a Dickson charge pump. The achievable output voltage is higher compared to Dickson topology for a given capacitor voltage limit. At the same time, the output impedance is lower than that of Cockcroft-Walton topology. Section IV analyzes the proposed voltage multiplier and develop a general model. We also design a hybrid voltage multiplier as an example. Section V experimentally validates the analysis and the design example of the previous section. Section VI concludes the paper.

II. REVIEW OF A COCKCROFT-WALTON MULTIPLIER
In this section, we review the operation of a two-stage Cockcroft-Walton multiplier. The purpose is to familiarize readers with definitions of terms used throughout the paper. In this and the following sections we assume ideal diodes; i.e., zero reverse current, zero forward voltage drop, and zero capacitance between two terminals.    (Fig. 1a) and its operation during the push phase (Fig. 1b) and the pull phase (Fig. 1c). Here we assume large enough C 1 and C 2 to maintain relatively constant output voltage across the load, so that the output current i out remains continuous with only a small ripple. The amount of charge delivered to the load during one switching cycle 1/f is denoted by q and is found as i out /f where i out is the average value of i out .
The push phase (Fig. 1b) is the interval between t = 0 and t = 0.5/f , when the ac voltage source v in ramps up from −V pp /2 to V pp /2. Similar to the well-known case of a half-wave rectifier, a current spike occurs in i in at the end of the push phase to recharge capacitors C 1 , C 1 , C 2 , and C 2 . This sharp injection of charge is marked with red arrows, and the amount of charge flowing through each branch is marked next to the arrow. Meanwhile, i out remains relatively constant, delivering the charge of q/2 to the load. This charge flow is marked with a black dotted arrow. A similar analysis applies to the pull phase (Fig. 1c), the interval when v in ramps down from V pp /2 to −V pp /2, with the charge flow directions reversed. Fig. 2 shows voltage waveforms of intermediate nodes v 1 , v 1 , v 2 , and v 2 . Black solid lines indicate v 1 , and v 2 . Orange dotted lines indicate v 1 and v 2 . On the left-hand side of the figure is the ideal case waveforms when capacitors are so large that the voltage drop across them is negligible. In this case, the peak-to-peak swing of v 1 and v 2 is the same as the input peak-to-peak swing V pp , and the level of v 1 and v 2 remains unchanged throughout the switching cycle.
On the right-hand side of Fig. 2 is the realistic case where the voltage drop across capacitors is non-negligible. Due to those voltage drops, peak-to-peak swings of v 1 and v 2 are reduced by ∆V 1 and ∆V 2 , respectively. Also, peak-to-peak ripples of ∆V 1 and ∆V 2 occur in v 1 and v 2 , respectively. From the charge flow map of Fig. 1, one can find that ∆V 1 = 2q/C 1 , ∆V 1 = 2q/C 1 , ∆V 2 = 2q/C 1 + q/C 2 , and ∆V 2 = 2q/C 1 + q/C 2 . Let us define the output voltage drop ∆V as the difference between the ideal output 2V pp and the peak output in the realistic case v 2,max as indicated in Fig. 2. (We use the same definitions of ∆V and δV throughout the rest of the paper.) Then, v 2,max is equal to 2V pp − ∆V where ∆V is equal to ∆V 1 +∆V 1 +∆V 2 . Also, the peak-to-peak ripple of the output voltage, δV , is the same as ∆V 2 by definition.  (Fig. 3c). All three circuits are four stage multipliers where the first stage consists of C 1 , C 1 , and two diodes at the bottom, the second stage consists of C 2 , C 2 , and the next two diodes, and so on. Those three voltage multipliers are functionally identical provided that capacitors are sufficiently large to serve the purpose of a dc-blocking ac-coupling capacitor. Ideally, capacitors C 1 , . . . , C 4 isolate nodes v 1 , . . . , v 4 at dc and short them at ac, specifically at the switching frequency of diodes. The same argument applies to capacitors C 1 , . . . , C 4 and v 1 , . . . , v 4 . (A general discussion on this type of capacitor-diode voltage multipliers can be found in [17].)

A. Operating Principle
When capacitors are sufficiently large, voltages v 1 , . . . , v 4 swing by the peak-to-peak amplitude equal to that of the input voltage v in . Similarly, if C 1 , . . . , C 4 are large enough, voltages v 1 , . . . , v 4 remain steady with no ripple. Due to such behaviors, the column of capacitors C 1 , . . . , C 4 is known as an oscillating column (also known as coupling column), and the column of C 1 , . . . , C 4 is called a smoothing column [18]- [21].
Provided that the dc output current i out and the switching frequency f are the same in three multipliers, the amount of charge flowing through each wire for every switching cycle is also the same. Fig. 4 illustrates how much charge flows in each branch during the push phase ( Fig. 4a) and the pull phase ( Fig. 4b).
Here we define charge q as the charge delivered to the load for one switching cycle, i.e., where i out is the average value of i out . Dotted wires indicate dc-open ac-short connections realized by coupling capacitors. Assuming approximately equal output voltage at each multiplier stage, during the push and pull phases the input voltage source v in either sources or sinks the charge 4q, respectively. The corresponding current spikes are marked with red arrows. The output dc current i out , marked with a black dotted arrow, is provided by the capacitor network of the smoothing column.

B. Voltage Drop and Ripple at the Output
Capacitors C 1 , . . . , C 4 and C 1 , . . . , C 4 in Fig. 3 are not infinitely large in reality. Charge flowing as indicated in Fig. 4 causes voltage drop across capacitors. Those voltage drops are depicted in Fig. 5. Black solid lines indicate v 1 , v 2 , and v 3 waveforms whereas orange dotted lines are for v 1 and v 2 waveforms (from bottom to top). When the input voltage peakto-peak swing is V pp , the peak-to-peak swing of v 1 is a bit smaller than V pp due to the capacitor voltage drop. Let us define ∆V 1 as the difference between V pp and the peak-to-peak amplitude of v 1 . ∆V 2 , . . . , ∆V 4 are defined in an identical manner. Also, let us define ∆V 1 , . . . , ∆V 4 as the peak-to-peak ripple of v 1 , . . . , v 4 . Fig. 5 indicates that the peak value of the output voltage v 4 , denoted by v 4,max , can be expressed as where The output peak-to-peak ripple which we denote by δV is, by definition, The average output voltage V out is Table I lists voltage drops at each node in four-stage multipliers of Fig. 3. Among those three topologies, Cockcroft-Walton has the highest voltage drop in every node. This is because all capacitors are located on vertical branches. Vertical branches carry larger amount of charge than horizontal branches, as illustrated in Fig. 4, resulting in a higher voltage drop. Also, influences of capacitors on vertical branches accumulate with the number of stages because vertical branches of lower stages constitute the ground return path for upper stages.
To make the comparison of Table I more meaningful, let us assume that all capacitor values are equal to C. Using Equations (3) and (4), we calculate ∆V and δV of three topologies. The results are shown in Table II. Also shown in the table is the highest voltage stress on capacitors V C,max .
As shown for four-stage multipliers in Table II, the proposed hybrid topology in general exhibits V C,max , ∆V , and δV that are in between those of Cockcroft-Walton and Dickson. If it is desired to reduce the output voltage drop and ripple at the expense of increased capacitor voltage stress, switching the topology from Cockcroft-Walton to hybrid may be considered. Similarly, if one wants to reduce the capacitor voltage stress of a Dickson multiplier, he may consider switching to a hybrid topology provided that the increased voltage drop and ripple at the output are acceptable.

C. Power Conversion Efficiency
The sagging phenomenon of the output voltage described in (5) is intrinsically related to power conversion efficiency. Power loss occurs even in our ideal analysis because we assume that it is a voltage source that abruptly charges and discharges capacitors. Fig. 4 indicates that for every switching cycle, the input ac source provides energy of 4qV pp to the multiplier, which in turn provides the energy of qV out to the load. Dividing the output energy by the input energy per cycle gives the efficiency This equation, together with ∆V and δV values in Table II, indicates that the proposed hybrid topology has an efficiency that is lower than Dickson's, but higher than Cockcroft-Walton's. Note that this argument is valid only when the multiplier circuit is driven by a voltage source (a low-impedance inverter). When driven by a current source (e.g., through a series inductor, like in the experiment of section V-B), no energy is lost when capacitors are charged and discharged. Thus, ideally, the multiplier can achieve the efficiency of 100 % even with a non-zero output voltage drop.

D. Energy Stored in Coupling Capacitors
In some cases, the size of coupling capacitors are determined by the energy they need to store, rather than by the type of discrete packages predetermined by capacitor manufacturers. For example, each on-chip capacitors in an integrated-circuit voltage multiplier can be sized differently. Also, high voltage generators of tens of kilovolts or higher often uses custom-designed capacitors. In such cases, the total amount of energy stored in coupling capacitors, denoted by E cap , may be of interest because it has implication on the size of the circuit. Ignoring the voltage drop by capacitors and assuming every multiplier stage equally generates the voltage V pp , we calculate E cap for three topologies by summing all energies stored in eight individual capacitors: Dickson: Hybrid: As is the case for ∆V and δV , E cap of the hybrid topology also sits between Dickson's and Cockcroft-Walton's.

E. Influence of Diode Non-Ideality
This section discusses the influence of the diode's forward voltage drop V D,on and the diode's parasitic capacitance C D,j on the voltage multiplier's performance. When V D,on is nonzero, V out is reduced by 8V D,on . This reduction occurs because the voltage added by each multiplier stage is reduced by 2V D,on . Analyses in [12], [22], [23] draw the same conclusion for Dickson topology.
The influence of non-zero C D,j depends largely on whether C D,j is much smaller than or comparable to C. When C D,j is much smaller than C, the output voltage is mostly unaffected, and merely the amount of charge that enters or exits the multiplier input during half a cycle is increased by 8C D,j V p p. This increase in charge is because the voltage across every diode has to be either increased or decreased by V pp before any diode turns on. Consequently, the inverter circuit that drives the multiplier needs to provide a larger ac current, which may negatively impacts the inverter size or efficiency.
When C D,j is comparable to C, not only the input current is increased as explained above, but also C now exhibits nonnegligible voltage drop when the input current is charging and discharging C D,j . The effective ac input voltage seen by the multiplier circuit is reduced, and as a result, V out is decreased. How much V out is decreased depends on the multiplier topology, i.e., the location of coupling capacitors that causes this voltage drop, but as can be readily inferred, Cockcroft-Walton will be most, and Dickson will be least affected.

Cockcroft-Walton Hybrid Dickson
Detailed analysis regarding the effect of C D,j on the output voltage of a Cockcroft-Walton multiplier can be found in [24]- [27].

IV. GENERAL MODEL FOR THE HYBRID TOPOLOGY A. Derivation
In order to generalize the hybrid topology, let us define parameters m and n that determines a (m×n) hybrid structure. Fig. 6 describes the structure. Parameter m is the number of capacitors that appear on vertical branches of either an oscillating column or a smoothing column. Parameter n is the number of stages in each block as described in Fig. 6 (or, equivalently, the number of total multiplier stages divided by m). Fig. 7 illustrates charge flow at the k-th stage of an (m × n) hybrid multiplier. Note that this picture is an approximation since the charge flows in this manner only when voltages of each multiplier stage are identical. In reality, as the number of multiplier stages increases so does the voltage drop at each stage, which results in a lower amount of charge drawn by higher stages. A more thorough discussion that takes this effect into consideration can be found in [28].
The first (n − 1) voltage multiplier stages have a coupling capacitor on the horizontal branch, similar to Dickson topology. The n-th stage has its capacitor on the vertical branch, similar to Cockcroft-Walton topology. Then the whole n-stage structure repeats m times to constitute mn multiplier stages.
In fact, this definition of (m × n) hybrid topology includes Cockcroft-Walton and Dickson topologies. A (m×1) topology corresponds to an m-stage Cockcroft-Walton topology, and a (1 × n) topology corresponds to an n-stage Dickson topology. For example, three multipliers depicted in Fig. 3a, 3b,   nodes v k and v k are denoted by ∆V k and ∆V k , respectively, where k is an integer from 1 to mn. Table III lists ∆V k and ∆V k in terms of charge q and capacitance C. Here, for the sake of simplicity, we assume that all capacitor values are equal to C. The charge q is defined in the same manner as (1). To obtain the output voltage drop ∆V and the peak-to-peak ripple δV , we generalize Equations (3) and (4) as follows: Substituting entries of Table III into Equations (10) and (11), we obtain and The average output voltage V out is The highest voltage stress on capacitors V C,max is As a sanity check, evaluating Equations (12) and (13) for (m, n) = (1, 4), (4, 1), and (2, 2) yields entries of Cockcroft-Walton, Dickson, and hybrid columns in Table II, respectively. Also, putting n = 1, we get and which are the same results as those found in many academic papers (e.g., [5], [28]) and textbooks [19]- [21] regarding an m-stage Cockcroft-Walton multiplier.

B. Design Example
We give a design example to illustrate the practical use of the proposed topology. The goal is as follows: Using a 10 MHz (f ), 180 V peak-to-peak ac voltage (V pp ) as the input, design a voltage multiplier that delivers at least 50 W to a 100 kΩ (R load ) resistive load. Available capacitors have a value of 2.2 nF (C) and are rated at 1 kV, i.e., the capacitor voltage stress should be 1 kV or less.
First, we calculate the output voltage V out of an (m × n) multiplier. Since the load is resistive, from (1) it follows that Substituting (18) for q in (12) and (13), and plugging in these two expressions for ∆V and δV into (14), we obtain a firstorder equation that can be solved for V out . Values of V out solved for m and n from 1 to 8 are summarized in Fig. 8a. For 50 W power to be delivered to 100 kΩ, the output voltage should be 2236 V or larger. Subsequently, cells where V out is less than 2236 V are shaded red. Capacitor voltage stress is calculated by (15) and shown in Fig. 8b. Again, cells where the voltage stress is larger than 1 kV are shaded red. Fig. 8c shows topology names that correspond to each combination of m and n. Combinations that survived the filtering process of Fig. 8a and Fig. 8b are highlighted in green. Among those four topologies, namely (4 × 4), (3 × 5), (4 × 5), and (5 × 5), we choose (4 × 4) topology because the capacitor voltage stress is well below 1 kV and its parts count is close to minimal. (The minimal parts count is achieved by (3 × 5).)

A. Model Verification
The first experiment is to validate general model equations (12) regarding the output voltage drop, and (13) regarding output ripple. We build a (4 × 4) hybrid voltage multiplier, measure the output voltage and its ripple, and compare those values with theoretical and simulated values. Fig. 9a and Fig. 9b are the schematic and the photograph of the test setup.
We design the experiment so that the test condition is close to ideal. For that purpose, we use large coupling capacitors (0.2 µF), small silicon Schottky diodes with low parasitic capacitance (10 to 20 pF), light load (100 kΩ), and low switching frequency (50 kHz).   We measure the output voltage at four different sets of input voltage and output current. Fig. 10 shows measured waveforms. Fig. 11 summarizes the test results. Theoretical values in those plots are obtained by (12) and (13). Simulated values are obtained by using the diode SPICE model from manufacturer's website, which includes the parasitic capacitance and forward voltage drop. Results show that measured values match theoretical predictions by difference of 25 % or less. Also, half or more of those differences are predicted from simulation and thus can be explained by the influence of diode parasitic capacitance and forward voltage drop.

B. 60 V-to-2.25 kV DC-DC Converter Demonstration
The second experiment's goal is twofold: to verify the voltage multiplier design from section IV-B, and to demonstrate a dc-dc converter that is more relevant to real-world applications. First, we build a 60 V input, 10 MHz class-E resonant inverter to create a 180 V peak-to-peak ac voltage. Next, we implement the previously designed (4 × 4) hybrid multiplier and connect it to the inverter. We then measure the output voltage and capacitor voltage stress to verify the general model in section IV-A. Fig. 12a and Fig. 12b are the schematic and the photograph of the test setup.     The horizontal scale is 50 ns/div. channel 2 (green): v ds , 50 V/div; channel 3 (blue): Vout, 500 V/div; channel 4 (pink): vac, 50 V/div. The ripple in channel 3 is due to the noise coupled to the differential probe and does not represent the ripple at the converter output. Fig. 13 shows voltage waveforms captured during the circuit operation. The class-E inverter generates a 0 V-to-230 V ac voltage at its transistor drain node (v ds in Fig. 12a, green curve in Fig. 13), which after filtration by L s and C s become a 176 V peak-to-peak ac voltage (v ac in Fig. 12a, pink curve in Fig. 13) that drives the (4 × 4) multiplier. The multiplier output is measured to be 2.25 kV dc (V out in Fig. 12a, blue curve in Fig. 13). This experimental result is close to the intended multiplier design of section IV-B where the input is 180 V ac and the output is 2.29 kV dc. Note that the ripple of the output voltage waveform is due to the noise coupled to the differential probe and does not represent the ripple at the converter output.  The highest capacitor voltage stress is measured 660 V as shown in Fig. 14. This value matches the prediction of 720 V from Fig. 8b within 10 % difference. Therefore, we conclude that the experiment validates the model and its ability to yield practical results.
Interestingly, experimental data in Fig. 14 show less sagging as the number of multiplier stages increases, compared to simulated values with ideal capacitors. We believe this phenomenon is caused by parasitic series inductance in real capacitors. We confirmed through measurement that 2.2 nF capacitors used in the voltage multiplier have an equivalent series inductance (ESL) of 2.8 nH, thereby presenting a lower impedance than ideal capacitors over the frequency range of 10 MHz to 90 MHz. Indeed, simulation produces a better match with the experiment when ESL is included in the model. on its blocking capacitors, but it suffers from a significant output voltage drop as the number of multiplier stages increases. The Dickson topology is the opposite of Cockcroft-Walton, having a low output voltage drop but at the expense of high capacitor voltage stress. The reason is that Cockcroft-Walton structure has all coupling capacitors in series and Dickson structure has all of them in parallel. Based on this observation, we proposed a voltage multiplier topology that has both series and parallel blocking capacitors that are put together in a pattern so that it takes advantage of both Cockcroft-Walton and Dickson structures. We analyzed a voltage multiplier with m series capacitors in total and n parallel capacitors between them, which we named a (m × n) hybrid multiplier. The analysis shows that (m × n) hybrid structure reduces the capacitor voltage stress by m times compared to Dickson while at the same time significantly reducing the output voltage drop compared to Cockcroft-Walton.
Experiments with a (4 × 4) hybrid multiplier verified that the model we developed accurately predicts the output voltage drop and ripple. Also, experiments with a 2 kV (4×4) voltage multiplier showed that the proposed topology indeed reduces the capacitor voltage stress as predicted by the analysis. Finally, we demonstrated the relevance of the proposed topology to real-world applications by building a 90.9 % efficient, 60 V in, and 2 kV out dc-dc converter.