A Systematic Method for Studying the Use of DC/DC Converters With Three Discontinuous Conduction Modes as Automatic PFCs

This article describes a general method for studying the behavior of converters with three discontinuous conduction modes as automatic power factor correctors (PFCs). Some converters with a single discontinuous conduction mode (such as Buck-Boost, Flyback, SEPIC, Ćuk, and Zeta converters) can behave as automatic PFCs when operating in that discontinuous conduction mode, with a nearly constant duty cycle during each cycle of the line voltage. There are also dc/dc converters that, due to multiple diodes and inductors, can operate in different discontinuous conduction modes. A systematic method for studying these three discontinuous conduction modes was recently presented. This article extends that method to using the aforementioned dc/dc converters as part of an ac/dc converter with low harmonic injection in the line, identifying when the converters behave as “ideal automatic resistor emulators” (i.e., configuring ideal automatic PFCs) and when they behave as “quasi-ideal automatic resistor emulators” (i.e., as quasi-ideal automatic PFCs). As an example, the article examines a SEPIC converter used as a resistor emulator. In this case, three discontinuous conduction modes are possible, if the inductance of the input inductor is low enough to allow the input bridge rectifier diodes to stop conducting when the transistor is off. The study allows us to determine of the line current waveform when the converter operates in any of the possible discontinuous conduction modes. The results show that quasi-ideal automatic PFC behavior can be achieved in discontinuous conduction modes with low inductance values. Moreover, the results for the SEPIC can be easily extended to the Ćuk converter operating in the same manner. Finally, the theoretical predictions for the line current from the proposed study were verified through simulation using PSIM (in the case of both the SEPIC and Ćuk topologies), and through experimentation (in the case of SEPIC).

Abstract-This article describes a general method for studying the behavior of converters with three discontinuous conduction modes as automatic power factor correctors (PFCs).Some converters with a single discontinuous conduction mode (such as Buck-Boost, Flyback, SEPIC, Ćuk, and Zeta converters) can behave as automatic PFCs when operating in that discontinuous conduction mode, with a nearly constant duty cycle during each cycle of the line voltage.There are also dc/dc converters that, due to multiple diodes and inductors, can operate in different discontinuous conduction modes.A systematic method for studying these three discontinuous conduction modes was recently presented.This article extends that method to using the aforementioned dc/dc converters as part of an ac/dc converter with low harmonic injection in the line, identifying when the converters behave as "ideal automatic resistor emulators" (i.e., configuring ideal automatic PFCs) and when they behave as "quasi-ideal automatic resistor emulators" (i.e., as quasi-ideal automatic PFCs).As an example, the article examines a SEPIC converter used as a resistor emulator.In this case, three discontinuous conduction modes are possible, if the inductance of the input inductor is low enough to allow the input bridge rectifier diodes to stop conducting when the transistor is OFF.The study allows us to determine of the line current waveform when the converter operates in any of the possible discontinuous conduction modes.The results show that quasi-ideal automatic PFC behavior can be achieved in discontinuous conduction modes with low inductance values.Moreover, the results for the SEPIC can be easily extended to the Ćuk converter operating in the same manner.Finally, the theoretical predictions for the line current from the proposed study were verified through simulation using PSIM (in the case of both the SEPIC and Ćuk topologies), and through experimentation (in the case of SEPIC).

I. INTRODUCTION
P OWER factor correctors (PFCs) are circuits in charge of en- suring low line distortion in single-phase ac/dc converters.Active PFCs use a dc/dc converter with a nonlimited dc conversion ratio placed between the line rectifier and the capacitor that stores energy during half-periods of the line voltage.This converter must operate as a resistor emulator (RE), meaning that it exhibits a resistive input impedance in such a way that the load seen by the line rectifier appears to be a resistor.The value of this resistor must match the power demanded by the converter from the line.There are two main ways to achieve this behavior (Fig. 1).They are as follows.
1) Providing the converter with an input current feedback loop that ensures that the input current is proportional to the input voltage.This requires adjusting the proportionality constant that determines the RE's input resistance, depending on the power demanded from the line.This is achieved using an analog multiplier that modulates the amplitude of the waveform used as reference for the current loop [1], [2].As Fig. 1(a) shows, this multiplier has two input signals: 1) a waveform proportional to the input voltage (and, therefore, variable over time); and 2) a signal that must remain almost constant each line period.As this signal comes from the output-voltage feedback loop, this loop must be slow enough to exhibit this behavior.This type of control can be used in any converter conduction mode, the only condition being that the converter dc conversion ratio must be nonlimited.2) Implementing a very simple control that maintains a constant duty cycle in each line period, while operating in a special mode that achieves the desired proportionality between the input voltage and the input current [see Fig. 1(b)].This behavior can be achieved when the dc/dc converter operates in discontinuous conduction mode (DCM) [3], [4], [5], [6], [7], [8] or when it is a resonant converter operating at a specific operation point [9].As in the previous control, the dc/dc converter must also exhibit an unlimited dc conversion ratio.Although this control mode offers the advantage of extreme simplicity, it does have a drawback: these modes increase the current stress on some semiconductors.Despite this drawback, this is an attractive control strategy for low-power and low-cost applications.The single-phase ac/dc converters that implement this control are called automatic PFCs in this article.As noted above, using some dc/dc converters operating in DCM allows us to build automatic PFCs.Therefore it is very important to determine when a converter operates in this mode.
In conventional dc/dc converters with a single diode, there are only two possible conduction modes: 1) the aforementioned DCM; and 2) continuous conduction mode (CCM).The boundary between these two modes is well known [10].The extension of this study to converters that behave as REs was found in [11].That study also focused on converters with only one diode and therefore with only one DCM.
On the other hand, some dc/dc converters with several diodes can exhibit several DCMs.A general method for studying these converters was presented in [12].That paper examined the use of a Versatile Buck-Boost converter.This same method was applied in [13] to address the case of SEPIC and Ćuk converters with an additional diode in series with their input inductors.In all of these cases (Versatile Buck-Boost and the modified versions of the SEPIC and Ćuk converters) three DCMs are possible, and their main characteristics were correctly identified and verified in both papers.It should be noted that in all these cases, the converters operated as conventional dc/dc converters, and their operation as REs in an ac/dc converter has so far not been addressed.Some dc/dc converters with only one diode (and, therefore, only one DCM) can be designed to always operate in DCM, even when they are used as an RE in an ac/dc converter [11].In the case of the Buck-Boost, Flyback [4], SEPIC [5], Ćuk [6], and Zeta [8] converters, designing them to always operate in DCM allows these converters to be used as ideal automatic REs.This is because they exhibit proportionality between the line current (averaged in a switching period) and the input voltage if the converter duty cycle remains constant each line period.Thus, very simple REs can be implemented using those topologies always operating in DCM.
However, the situation is very different for converters with several DCMs, including implementations of SEPIC and Ćuk converters with low inductance values.In this case, the first question to answer is whether the converter can be designed to always operate in one of the DCMs (or in several of them) when it is working as part of an ac/dc converter.As Fig. 1(b) shows, the converter will be placed in between a line rectifier (which means full-wave rectified sinusoidal input voltage) and a bulk capacitor (which means constant output voltage), and its duty cycle will be kept constant each line period, thus implementing an RE.If the converter can be designed to always operate in one or several DCMs in these conditions, the next question to answer is the state of the line current.If it is a perfect sinusoid, then the final converter will work as an ideal automatic PFC.On the other hand, if the line current exhibits some distortion, then the final converter will work as a quasi-ideal automatic PFC.Moreover, if the distortion is high enough, using the converter as an automatic RE will not be possible.It should be noted that these remain open questions.The main objective of the present article is to propose a systematic method that will allow these questions to be answered.
In summary, the main objective of this article is to provide a general method to evaluate the performance of any dc/dc converter with multiple DCMs as a potential automatic RE in an ac/dc power conversion scheme, as the one given in Fig. 1(b).The interest in studying the case of multiple DCMs is for two main reasons as follows.
1) Operation in DCMs is always associated with low inductor values, which in general means a smaller converter size for a given switching frequency.2) As Fig. 1(b) shows, the control scheme for an automatic RE is very simple.However, the line current waveform corresponding to operate following a given sequence of DCMs has not yet been addressed.The quality of the line current waveform obtained following the proposed method determines whether the converter can work as an ideal or quasi-ideal automatic RE, or must be discounted as an automatic RE.The rest of this article is organized as follows.Section II provides a brief review of three important issues: 1) the study of the conduction mode boundaries in dc/dc converters with only one DCM that are operating as conventional dc/dc converters; 2) the study of the conduction mode boundaries in dc/dc converters with only one DCM that are operating as PFCs; and 3) the study of the conduction modes of dc/dc converters with three DCMs that are operating as conventional dc/dc converters.Section III proposes a general method for studying the conduction modes of dc/dc converters with three DCMs that are operating as PFCs, which is the main objective of the article.Section IV provides example cases where the proposed method is applied to several implementations of PFCs based on SEPIC and Ćuk topologies, designed with low enough values of input inductance to generate three DCMs.Section V describes verification of the predicted operation modes and of the line current waveforms, using simulation and an experimental prototype of the SEPIC converter.Finally, Section VI concludes this article.

II. REVIEW OF CONDUCTION MODE BOUNDARIES
This section presents a brief review of the study of the boundaries between conduction modes in dc/dc converters.Three different situations are considered as follows.
1) DC/DC converters with only one diode (and therefore only one DCM) working as conventional dc/dc converters (i.e., with constant output voltage, input voltage changing in quite a limited range of variation, and controlled by fast changing the converter duty cycle when the input voltage and/or the load change).2) Converters with only one diode (and therefore only one DCM) working as ideal REs [11] (i.e., with constant output voltage, input voltage continuously changing from zero to the peak value of the line voltage, and controlled in such a way that the input current is proportional to the input voltage).The two main implementations for achieving this behavior are shown in Fig. 1. 3) Converters with two diodes that remain in inductive branches when the transistor is OFF (and therefore converters with three DCMs), working as conventional dc/dc converters [12], [13] (i.e., as in the first case, constant output voltage, limited input voltage variation, and fast duty cycle variation characterize their operation).

A. DC/DC Converters With Only One DCM Working as Conventional DC/DC Converters
Conventional dc/dc converters with only one diode have only two possible conduction modes: 1) DCM; and 2) CCM.The boundary between these two modes is well-known [10].First, the dimensionless conduction parameter k is defined: where L is the value of the inductance of the converter inductor, R is the load resistance, and T s is the switching period.The critical value of k that defines the boundary between CCM and DCM in closed-loop, k crit_cl , is a function of the ratio M , which is the dc conversion, defined as M = V o /V g .The converter operates in CCM when and in the DCM when The conduction mode can be easily analyzed by placing the values of k and k crit_cl on a straight line, as shown in Fig. 2(a).
When the load value changes, then the value of parameter k also changes, as shown in Fig. 2(b), and the conduction mode can change.

B. DC/DC Converters With Only One DCM Working as Resistor Emulators
The extremely simple method described in the previous subsection was proposed for converters operating as conventional dc/dc converters.Expanding that study to converters that behave as REs was reported in [11].That study also focused on converters with only one diode and consequently, only one DCM.
The key for that study is that both the converter dc conversion ratio and the load seen by the converter are not constant in this case (although R is constant), but instead continuously and synchronously change according to the line angle ϕ [11].The variation of the dc conversion ratio with ϕ allows us to redefine it as m(M π/2 , ϕ) where M π/2 is the value of the converter dc conversion ratio at the peak value of the line voltage, V g If the converter operates as an ideal RE due to a control scheme such as in Fig. 1(a), then its input current can be expressed as where I g is the peak value of the RE input current for a certain load value R. The power balance between the converter input and output ports for each line angle yields Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.In (7) Therefore, ( 6) and (7) can be expressed as Using (10), the load that the dc/dc converter sees before the capacitor C B can be defined as follows: The main quantities involved in the operation of an RE are shown in Fig. 3.
As the load seen by the converter changes according to line angle ϕ, then parameter k also changes according to ϕ.Therefore, k can be redefined as follows: The conduction mode of an RE with only one DCM will be the CCM for the values of ϕ and R that satisfy For the sake of simplicity, this inequality can be rewritten as follows: Conversely, the conduction mode of the RE with only one DCM will be the DCM for the values of ϕ that satisfy: As a result of these inequalities, an RE with a single diode that supplies power to a certain load R can operate in the following three possible modes.1) Always in the CCM, if (14) is satisfied for the entire range of ϕ. 2) Always in the DCM, if (15) is satisfied for the entire range of ϕ. 3) Partially in CCM and DCM, if (14) is satisfied for values of ϕ around the peak value of the line voltage and, conversely, (15) is satisfied for values of ϕ around the zero-crossing of this voltage.Of course, this situation can change when the load R changes.Fig. 4(a) shows the relative situation of k(R, ϕ) and k crit_cl (M π/2 , ϕ) when the converter has been designed to operate in CCM.In Fig. 4(b), the converter is still operating in CCM when 0 < ϕ < π/2.The idea of the movement of both k(R, ϕ) and k crit_cl (M π/2 , ϕ) when ϕ decreases from π/2 to 0 (or increases from π/2 to π) is represented in Fig. 4(c), where the converter is operating in CCM at ϕ = π/2.Finally, the situation corresponding to operating in DCM by increasing the load resistance up to R max is shown in Fig. 4(d).In all cases, the values of k and k crit_cl reach their maximum values at the peak of the line voltage, and they tend to zero when the line voltage also tends to zero.
The design of an RE with a single diode can be such that it always operates in DCM (for any range of variation of input voltage and load).This type of design allows it to be used as the core of an automatic PFC.As mentioned previously, in Buck-Boost, Flyback [4], SEPIC [5] and Ćuk [6], [7], and Zeta [8] converters operating in DCM, RE behavior is achieved when the converter duty cycle is kept constant during each line cycle.This means that the simple control strategy shown in Fig. 1(b) can be used in these cases.In summary, ideal automatic PFCs can be built from these topologies once they have been designed to operate in DCM.This means that the control circuitry can be dramatically simplified.A Boost converter can operate as a quasi-ideal automatic PFC if it operates in DCM and works at constant frequency [3].To work as an ideal automatic PFC, it must operate just in the boundary between CCM and DCM [14] (also known as critical conduction mode).

C. DC/DC Converters With Three DCMs Working as Conventional DC/DC Converters
Let us consider conventional dc/dc converters, but now with two diodes and two inductors (L 1 and L 2 ).If the two diodes remain in two inductive branches (made up of inductances L 1 and L 2 or a combination of the two) when its transistor is in OFF state, then the converter will have four conduction modes, one CCM and three DCMs [12], [13], [15], [16].An example of the current passing through the converter diodes is shown in Fig. 5.The possible conduction modes in the case of three DCMs are shown in Table I, where the diode conduction states are represented by logical values.Thus, the ON state of a diode at the end of the switching period corresponds to logical level 1, whereas the OFF state of a diode at the end of the switching period corresponds to logical level 0. For example, operation in DCM2 implies that diode D 1 is OFF and diode D 2 is ON at the end of the switching period.In summary, converter conduction modes can be easily identified by observing the conduction state of each diode at the end of the switching period.
When the converter is working in closed loop and the input voltage remains constant, both the input and the output voltage  are constant.Consequently, the slopes of the current passing through the converter inductors remain also constant.Therefore, the slope of the current passing through the diodes during the transistor OFF period also remains constant.If the converter is operating in the CCM [see Fig. 5(a)] and the load decreases, then the average current passing through the inductors and diodes must decrease.The converter will operate in the CCM at constant duty cycle until one of the diode currents reaches zero just at the end of the switching period.If this current is i D1 , then the converter works in the boundary between the CCM and DCM2 [see Fig. 6(a)].If the load continues decreasing, the average value of i D1 must decrease.As the slope remains constant, the converter duty cycle must decrease, leading to operate in DCM2 [one example of the waveform corresponding to this mode is given in Fig. 5(c)].An additional decrease of the load implies an additional decrease of the converter duty cycle.The operation mode corresponding to zero load will depend on the converter Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.under study.Thus, the converter can either continue in DCM2 or change to DCM3 when reaching zero load.
Obviously, a similar process will take place if i D2 is the current that reaches zero just at the end of the switching period when the load decreases from operation in the CCM.In this case, the converter will evolve from CCM to DCM1 [see Fig. 5(b)].As in the previous case, an additional decrease of the load until zero can imply either to continue in DCM1 or to enter in DCM3.
A very special situation is represented in Fig. 6(b).In this figure, both diode currents reach zero just at the end of the switching period.This situation is the boundary between the four conduction modes.As will be explained later, this boundary is of primary concern when analyzing and designing the converter.
To study the conduction modes, a plane is established from parameters k 1 and k 2 [12], which are defined as usual The operation of the dc/dc converter can be characterized by a family of maps plotted in the k 1 k 2 plane, such as in Fig. 7.Each map contains the regions of conduction modes for a particular value of the dc conversion ratio M .Each region corresponds to a specific conduction mode.The boundaries between adjacent conduction modes are curves drawn in this plane.The shapes of these curves are arbitrary in Fig. 7 because this map does not correspond to a specific converter.However, there are several general rules regarding the location of the conduction modes in the map.Since operation in CCM implies larger inductors than operation in any of the DCMs, the CCM region is the one farthest from the origin of the k 1 k 2 plane (i.e., the bottom left corner) and from the axes.In contrast, regions corresponding to the DCMs are closer to the origin and the axes.The operation point of the converter moves along a straight line called a "trajectory," which is determined by slope α = L 2 /L 1 .In the example given in Fig. 7, operation point P is in the CCM, on a trajectory defined by α = 1.5.As the load resistance R increases, operation point P moves along the trajectory toward the origin of the k 1 k 2 plane, due to the synchronous variation of parameters k 1 and k 2 according to ( 16) and (17).In the example in Fig. 7, operation point P could move from CCM to DCM2, or even to DCM3 if the increase of R is great enough.When the value of M changes due to a variation of the input voltage, the boundaries between the conduction regions change in the map, resulting in a new map of regions.Therefore, each value of M will have a corresponding map of conduction regions.
The dc conversion ratio for the converter can be expressed using equations that take the following form: 1) In the CCM where M 0 is the value of M in this mode and d is the converter duty cycle.2) In the DCMx where M x is the value of M in this mode.The boundaries between adjacent regions DCMx and DCMy can be easily calculated by equalizing the dc conversion ratios of these regions, M x and M y .The steps to follow are as follows.
1) To replace M x and M y with M in the two expressions in the form (19). 2) Eliminate variable d from the two expressions in the form (19).The equation thus obtained for the boundary between DCMx and DCMy is as follows: As previously explained, an example of current waveforms in one of the boundaries between regions (conduction modes) is shown in Fig. 6(a).Also as previously explained, all the conduction regions (conduction modes) intersect at a single point called the central point, P C .The value of the coordinates of the central point for a given value of M , k 1_P c and k 2_P c , can be determined by using either two equations in the form (20) or three equations in the forms (18) and (19).Therefore, the coordinates of the central point are exclusively functions of M .The current waveforms in central point P C are shown in Fig. 6(b).

A. General Considerations
If we consider a dc/dc converter with only one inductor working at a constant load, then the conduction mode is completely defined by inequalities (2) and (3).This situation is perfectly described by the position of dimensionless parameter k on a straight line, where the boundary k crit_cl also lies (Fig. 2).When the load changes and the dc conversion ratio remains constant, parameter k changes its position along the straight line while k crit_cl remains constant, thus allowing a change in the conduction mode [Fig.2(b)].
The situation is different if that converter is forced to work as an RE in an ac/dc conversion scheme [Fig.1(a)], even if the load R remains constant.In this case, the conduction mode may depend on the line angle, because both the converter dc conversion ratio and the load "seen" by the RE are continuously changing according to the line angle, in spite of having a constant value for R (Figs. 3 and 4).Obviously, the situation becomes more complex if R also changes [Fig.4(d)].
Coming back to the case of a dc/dc converter working as a conventional dc/dc converter instead of working as an RE, the situation is different again if the converter has three DCMs.In this case, two dimensionless parameters k must be defined, determining a plane instead of a line [12].Now, the boundaries between conduction modes are curves instead of a point, making a map of conduction regions.If the load R is constant, then the operation point lies in a specific conduction region of the map.The operation point describes a straight line on the map (the trajectory) if load R changes.The trajectory can pass through different regions (conduction modes) of the map.Now, let us consider the use of this converter, not in a conventional dc/dc conversion scheme, but as a part of an ac/dc converter, working as the RE in this power conversion scheme.To the authors' best knowledge, this scenario has not been studied before.As mentioned previously, the converter must have an unlimited dc conversion ratio (otherwise it cannot operate as an RE).Moreover, let us consider a control strategy as simple as the one shown in Fig. 1(b).In these conditions, we need to determine whether the converter can operate either as an ideal RE or as a quasi-ideal RE, or is a long way from this desirable behavior.None of the existing methods can be directly applied to determine the converter input current waveform, i g (ϕ), for the following reasons.
2) The dc conversion ratio is continuously changing (because of the rectified sine input voltage).
3) The load seen by the RE also changes according to the line voltage.It should be noted that, in this case, the input voltage is continuously changing according to the line angle, whereas the converter duty cycle remains constant.Consequently, the slopes of the current passing through the converter diodes will change (case of currents depending on the line voltage) or will remain constant (case of currents depending on the output voltage, exclusively).Moreover, the conduction mode must always be one of the DCMs for any possible conduction mode and load, in order to enable the possibility of operating as an RE.Therefore, the sequence of DCMs that the converter is going to follow in this case is clearly different from the one previously described for the case of operating as a conventional dc/dc converter.
The objective of this article is to present a methodology for studying the operation of dc/dc converters that involve three DCMs when they are used as automatic PFCs.Particular attention has been paid to input current modeling in order to properly evaluate the performance of the converters in this application.

B. Determining the Converter Input Current Waveform
Let us consider a dc/dc converter with three DCMs and with an unlimited dc conversion ratio.This converter is used as the RE in an ac/dc conversion scheme, like the one shown in Fig. 1(b), where the converter duty cycle is kept constant during each line cycle.In these conditions, the converter input voltage is continuously changing according to a rectified sine waveform, whereas the converter output voltage is kept constant due to bulk capacitor C B .Therefore, the converter satisfies (4) and (5).To normalize the study, a base value for the converter currents can be defined from L 1 , as follows: Similarly, an alternative base value could be defined from L 2 The values of the dimensionless parameters k 1 and k 2 that the converter is seeing can be computed as follows: If the capacitance of capacitor C B [Fig. 1(b)] is large enough to ensure negligible voltage ripple across it, then the current injected by the converter into the output RC B network is By using ( 21)-( 24), (25) becomes and, therefore, the normalized value of i o (ϕ) can be expressed by either of the two following equations: Equations ( 26)-(28) show that the evolution of k 1 (ϕ) and k 2 (ϕ) faithfully reflects the evolution of i o (ϕ).Now, let us establish a power balance between the converter input and output ports.First, this balance is established for each line angle ϕ, averaging the electrical quantities over a switching period.Taking into account (5), the converter input current gives It should be noted that i g (ϕ) is the average value (averaged over a switching period) of the actual input current.Taking into account ( 26), (29) becomes This is a very important equation because it shows that the converter input current can be easily computed once the evolution of either k 1 (ϕ) or k 2 (ϕ) has been determined during a Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
line half-cycle.Moreover, the normalized expressions of i g (ϕ) can be obtained directly from (4) and (30) Extending the power balance between the converter input and output ports to a line half-cycle, and taking into account the electric charge balance in capacitor C B , produces the following equation: Taking into account ( 26), (33) becomes where K 1avg and K 2avg are the average values of k 1 (ϕ) and k 2 (ϕ), respectively, in a line half-cycle From (34), the converter output power can finally be expressed as follows: Equation ( 37) is essential for the converter design, as it relates the converter power to either inductance L 1 through (21) or L 2 through (22).However, the values of either K 1avg or K 2avg must be known to properly design a converter with (37).Therefore, determining the evolution of k 1 (ϕ) (or k 2 (ϕ)) is essential for the following two very important reasons.1) To determine the input current waveform, according to (30).Once this waveform is known, the line current harmonic distortion can be computed, which is a key concern in evaluating the use of the converter as an RE. 2) To properly design the converter, according to (37) and the set of ( 21) and (35), or ( 22) and (36).Finally, K 1avg is of primary concern in producing a smallsignal linear model for any dc/dc converter working as an automatic RE, because this type of model is based on averaging i o (ϕ) in a half-cycle of the line period.After linearizing K 1avg , a canonical first order circuit may be obtained, and a control transfer function can be derived from it.However, the transfer function thus obtained would depend on the particular converter selected to work as an automatic RE.Consequently, a more detailed study of this transfer function is beyond the scope of this article.

C. Determining k 1 (ϕ) Evolution
Before determining the evolution of k 1 (ϕ) it is important to identify the map of the converter's conduction modes when it is working as a conventional dc/dc converter (i.e., when not only is the output voltage constant, but also the input voltage).As noted previously, this map is a function of the dc conversion ratio M .Once this map is known for any possible value of M , the map corresponding to M π/2 (calculated according to (5)) must be selected.This value corresponds to the value of m(M π/2 , ϕ) when ϕ = π/2.The values of the dimensionless parameters k 1 and k 2 in the map corresponding to M π/2 are k 1 (π/2) and k 2 (π/2), respectively.
The first step in determining the evolution of k 1 (ϕ) is to place the operation point P in the map corresponding to M π/2 .This operation point will be called P π/2 .The coordinates of P π/2 in this map are denoted as k 1_P π/2 and k 2_P π/2 in Fig. 8(a).Obviously, to achieve behavior as an RE, P π/2 must be placed in one of the three DCMs.If DCMx is selected, then the value of the converter duty cycle d DCM can be easily obtained from (19) after the following transformations.
2) k 1 and k 2 must be replaced with k 1_P π/2 and k 2_P π/2 , respectively (known).3) d must be replaced with d DCM (unknown).The final equation is It should be noted that the value of d DCM thus obtained is kept constant while M π/2 and R are also constant.Once P π/2 is placed in the map corresponding to ϕ = π/2 and, therefore, k 1_P π/2 , k 2_P π/2 and d DCM are known, the next step is to determine the value of k 1 (ϕ) for different values of ϕ.Due to the symmetry of v g (ϕ) with respect to ϕ = π/2, we can select either the interval from ϕ = π/2 to ϕ = π or the interval from ϕ = π/2 to ϕ = 0 to study the evolution of k 1 (ϕ).For the sake of simplicity, the second option is selected here.
When ϕ decreases from π/2 towards 0, less current is injected by the RE into the output RC B network, which means that i o (ϕ) decreases and therefore the value of k 1 (ϕ) also decreases, as (26) shows.As L 2 = αL 1 , k 2 (ϕ) = αk 1 (ϕ), which means that the operation point goes down along the trajectory [see Fig. 8(b) and (c)].The operation point corresponding to each value of ϕ is called P ϕ .
For each value of m(M π/2 , ϕ), a new map should be drawn [see Fig. 8(b) and (c)], because the boundaries between conduction regions depend on the converter dc conversion ratio, which is m(M π/2 , ϕ) now.If the operation point P ϕ remains in DCMx, then the value of k 1 (ϕ) can easily computed from (19) again, but now after the following transformations.
2) d must be replaced with d DCM (known).
3) k 1 must be replaced with k 1 (ϕ) (unknown).4) Once k 1 (ϕ) is known, k 2 (ϕ) = αk 1 (ϕ), is also known.The final equation is This equation gives the value of k 1 (ϕ) while the converter remains in DCMx.Due to the movement of both the operation point (along the trajectory) and the boundaries when ϕ decreases, the converter can reach other DCMs, e,g" DCMy.
In general, the equation corresponding to the boundary between DCMx and DCMy can be easily computed from a modified version of (20), obtained by replacing M with m(M π/2 , ϕ), k 1 with k 1 (ϕ) and k 2 with k 2 (ϕ).The final equation is The value of ϕ corresponding to this boundary can be computed from (39) and (40), taking into account that k 2 (ϕ) = αk 1 (ϕ).
The value of ϕ thus obtained is denoted as ϕ x−y Once the operation point is placed in DCMy, the evolution of k 1 (ϕ) can be obtained from an equation similar to (39), but valid for DCMy This process is repeated until k 1 (ϕ) = 0, at ϕ = 0.The DCM corresponding to this final state may be any of the three DCMs, depending on the position of P π/2 on the map corresponding to M π/2 .In fact, the complete evolution of k 1 (ϕ) will depend strongly on this position, and in consequence, the line waveform (and its distortion) will depend on it.Therefore, the position of P π/2 in the map corresponding to M π/2 is a primary concern when analyzing the converter design.
The set of maps of conduction modes corresponding to values between ϕ = 0 and ϕ = π/2 can be summarized in a unified map in the k 1 (ϕ)k 2 (ϕ) plane [see Fig. 8(d)], where the boundaries between regions continuously change as a function of ϕ.These boundaries always correspond to equations in the form (40).
A flowchart describing the procedure for determining the evolution of k 1 (ϕ) is shown in Fig. 9.

D. Design Procedure
The input data for the design will be the output voltage and current, V o and I o , and the peak value of the line voltage, V g .Consequently, M π/2 is input data as well (see ( 5)).
1) The first step in the design procedure is to select the position of P π/2 on the map corresponding to M π/2 , according Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.to several possible criteria (line distortion, conduction, and switching losses, etc.), but always in a DCM.Once the coordinates of P π/2 are known, the value of α is fixed.Using (38), the value of d DCM can be obtained.
2) The second step is to determine the evolution of k 1 (ϕ) from ϕ = 0 to ϕ = π (in fact, determining evolution from ϕ = 0 to ϕ = π/2 is enough, due to the waveform symmetry).The value of K 1avg will be obtained using (35).
3) The third step is to compute the value of I base1 from (34).
This value allows us to determine the value of L 1 for a given value of switching period T s , according to (21).Obviously, L 2 = αL 1 .A flowchart describing the design procedure is shown in Fig. 10.

IV. EXAMPLE OF USING THE PROPOSED METHOD: THE SEPIC
AND ĆUK CONVERTERS WORKING AS AUTOMATIC RES Fig. 11 shows several implementations of PFCs based on the SEPIC and Ćuk topologies.The converter shown in Fig. 11(a) is the classical implementation based on the use of the SEPIC topology and a full-wave rectifier at the input [5], [7].It should be noted that if the inductance of L 1 is relatively low, the current passing through inductor L 1 tends to reverse during the transistor OFF state, but cannot reverse due to the diodes in the full-wave rectifier.
This circuit can be modified to avoid using the full-wave rectifier (bridge rectifier), thus obtaining the bridgeless SEPIC topology shown in Fig. 11(b) [17].In this case, the topology avoids the voltage drop across one of the bridge rectifier diodes, at the expense of having two transistors.During the positive line half-cycle, transistor S 1 is always in the ON state, whereas transistor S 2 is switching.After analyzing a switching period in this line half-cycle, it can be observed that diode D B2 is connected in series with inductor L 1 during transistor S 2 OFF state.Therefore, an additional DCM can occur in the current passing through inductor L 1 , besides the one essentially due to inductor L 2 , leading to three DCMs.Obviously, a similar situation occurs in the negative line half-cycle due to diode D B1 , when transistor S 2 is always in the ON state, transistor S 1 is switching and the current passing through inductor L 1 has the opposite direction.The only difference between this and the previous case [Fig.11(a)] is that i g (ϕ) (which is the value of the current passing through inductor L 1 averaged over a switching period) is always positive, whereas i g (ϕ) [see Fig. 11(b)] changes its direction each line half-cycle (i.e., it is an ac current).
All of these considerations can be extrapolated to the classical Ćuk [see Fig. 11(c)] [6], [7] and the bridgeless Ćuk [see Fig. 11(d)] [18].Moreover, other bridgeless PFCs based on SEPIC and Ćuk topologies have been proposed [19], [20], [21], [22], [23], [24], [25], [26].In many of them, DCM operation is forced to achieve automatic PFC operation.In spite of having several diodes and inductors, only one DCM is considered, because the value of some inductors is high enough to avoid multiple DCMs.In this case, the method proposed here allows us to evaluate the operation of these converters with lower inductor values.
The study of PFC implementations based on the SEPIC topology [see Fig. 11(a) and (b)] with three DCMs must start by examining how this topology behaves working as conventional dc/dc converter, but with an additional diode at the input port [see Fig. 12(a)].This converter has been already studied in [13].Its main current waveforms appear in Fig. 12(b).The map of conduction mode regions for M = 0.6 is shown in Fig. 13.Two different trajectories have been drawn in this figure: α = 1 and α = 0.3.The expressions that define the dc conversion ratios for each conduction mode [expressions in the forms ( 18) and ( 19)], are as follows [13]: where  The boundaries between conduction regions, obtained from (44)-( 47) are [13] which is the boundary CCM-DCM2, valid when k 2 > k 2_P c .
which is the boundary DCM1-DCM3, valid for when which is the boundary DCM2-DCM3, also valid for As demonstrated in [13], (42)-( 51) are also valid for a Ćuk converter with an additional diode at its input port.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
The operation of the REs shown in Fig. 11(a) and (b) must be addressed from the operation of the converter given in Fig. 12(a) (just described), but considering that the dc conversion ratio is continuously changing.As the input voltage follows a rectified sine waveform, central point P C and the boundaries between conduction regions will also change according to the line angle ϕ.The set of ( 44)-(48) will be now transformed as has been previously explained, the final result is as follows.
1) Boundary CCM-DCM1 which is also valid for 0 < k 1 (ϕ) < k 1_P c (M π/2 , ϕ).The map corresponding to M π/2 = 0.75 and ϕ = π/2 is given in Fig. 14(a).The coordinates of central point P C can be easily obtained from (57) The maps corresponding to other specific values of ϕ are shown in Fig. 14(b)-(d), where the movement of the region boundaries and of central point P C can be observed.In Fig. 15, these maps are collected in a map that summarizes the information given in the previous maps.This map also shows the movement of central point P C when ϕ changes.The equation that describes this movement on plane k 1 (ϕ)k 2 (ϕ) can be easily obtained by eliminating sin(ϕ) in the set of (57) To study the evolution of the boundaries between conduction regions, let us describe the evolution of the straight line that defines the boundary between DCM1 and DCM3 when ϕ changes.From (57), the slope of this straight line is As (64) shows, the slope of the DCM1-DCM3 boundary becomes vertical when ϕ approaches zero.This conclusion is extremely important to understanding converter operation, as will be explained below.
As the proposed method establishes, the positioning of point P π/2 on the map corresponding to k 1 (π/2)k 2 (π/2) is a key point for analyzing converter operation.Let us draw a straight line from point P C to the origin.This straight line meets the boundary between DCM1-DCM3.From (64), the slope of this straight line is As the slope of the trajectory is α and P π/2 must be placed in any of the DCMs, then two possible situations must be taken into consideration (Fig. 16) as follows.1) Case 1: α < M π/2 .In this case, point P π/2 is placed in DCM1.2) Case 2: α > M π/2 .In this case, point P π/2 is placed in either DCM2 or DCM3.If the converter is designed in Case 1, the operation point will remain in DCM1 when line angle ϕ changes from π/2 to 0 (or from π/2 to π), due to the movement of central point P C (see Fig. 15).Consequently, the evolution of k 1 (ϕ) can be computed Taking into account ( 21) and (66), and that i g (ϕ) is obtained by averaging inductor L 1 current over a switching period, then (30) becomes where i L 1 (t, ϕ) is the current passing through inductor L 1 .This result demonstrates that the converter operates as an ideal automatic RE when designed in Case 1.As a pair of the input diodes shown in Fig. 11(a) or one of the input diodes in Fig. 11(b) are always conducting, the result is consistent with the description given in [5] and [17] for the same converters with a single DCM.
To prevent the converter from operating in CCM when ϕ = π/2, it is derived from (43) that the following condition must be satisfied: On the other hand, P π/2 is placed in either DCM2 or DCM3 in Case 2. If placed in DCM2, the value of k 1 (ϕ) while the converter remains in this mode is easily deduced from (54), the result is A comparison of (66) and (69) allows us to predict that the evolution of i g (ϕ) in this mode does not correspond to a sinusoidal evolution.
As the angle moves away from π/2, the operation point also moves along the trajectory until it reaches a certain value of ϕ, labeled ϕ 2−3 , corresponding to leaving DCM2 and entering Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.DCM3.The value of this angle can be computed from (61) and (69) and the definition of α, obtaining where Once the operation point enters the region corresponding to DCM3, the value of k 1 (ϕ) is determined by ( 55) and (56).However, the operation point always enters DCM1 when ϕ continues decreasing.In other words, the converter always operates in DCM1 near the line zero crossing.This is due to the slope of the curve described by P C (see (64)), which is vertical near the line zero crossing.When the slope of the straight line that defines the boundary DCM1-DCM3 is steeper than the slope of the trajectory, then the converter starts operating in DCM1.From (60) and the definition of α, we obtain where ϕ 3−1 is the value of ϕ corresponding to this boundary.As the converter is operating in DCM1, k 1 (ϕ) is calculated again using (66).
In order to prevent the converter from operating in CCM when ϕ = π/2, inequality (68) must be satisfied.Furthermore, if the objective is to ensure that the converter operates in DCM2 at ϕ = π/2, the determination of the duty cycle value at the DCM2-DCM3 boundary becomes critical.From (54) and (61), we obtain the value of the duty cycle needed to design the converter just in that boundary Therefore, the following inequality must be verified to place On the other hand, P π/2 is placed in DCM3 if According to the proposed method and the equations already obtained for the SEPIC REs given in Fig. 11  In the first (Fig. 17 69) when operating in DCM2, it must be obtained from ( 55) and (56) in DCM3, while it is (66) in DCM1.Once the evolution of k 1 (ϕ) is completely determined, the normalized line current i gn1 (ϕ) is directly obtained from (31).Line current waveform i line (ϕ) can be easily built from i g (ϕ), which is a rectified version of i line (ϕ).A normalized version of i line (ϕ) can be defined as The waveform obtained for this quantity is shown in Fig. 17(b).
In the second example (Fig.   Both examples show that low distorted line current waveforms can be obtained when the SEPIC converter is designed to operate in Case 2 (α > M π/2 ).This is an important conclusion, because designing in Case 1 implies a large value of inductor L 1 , according to the definition of α.Therefore, quasi-ideal RE behavior can be achieved even if the value of inductor L 1 is similar to the value of inductor L 2 .A detailed analysis of the possible designs as a function of the position of P π/2 in the map of conduction regions is beyond the scope of this article, which mainly focuses on proposing a general method for studying the operation of converters with three DCMs as REs.The SEPIC converter is an example to demonstrate how the method can be applied in a specific case.
As [13] showed, all of the equations that represent the operation of the converter shown in Fig. 12(a) are the same as those corresponding to a conventional dc/dc Ćuk converter with an additional diode at its input port.Consequently, all the conduction maps agree for both converters.Because of that, the variation of the region boundaries with the line angle when the Ćuk converter is working as an RE [according to the control scheme given in Fig. 1(b)], also agree.Therefore, all the considerations for the SEPIC RE can also be applied to the Ćuk converter when used as an RE.

V. VALIDATION OF THE PROPOSED METHOD WITH SEVERAL IMPLEMENTATIONS OF SEPIC AND ĆUK CONVERTERS WORKING AS AUTOMATIC RES
In this section, the proposed method to determine the line current of automatic PFCs based on converters with three DCMs is verified on several examples of SEPIC and Ćuk converters.This verification involved both simulation using PSIM software and experimentation on a real prototype.

A. Validation by Simulation
The first circuit simulated is the one shown in Fig. 11(a), which is the classical implementation of a SEPIC converter used as an automatic PFC.The values of the main components are given in  Table II.It should be noted that both inductors have been selected with the same value, which means α = 1.As the peak value of line voltage is V g = 110 √ 2 V and the output voltage is V o = 77.8V, then M π/2 = 0.5.This means α > M π/2 and, therefore, P π/2 must be placed in either DCM2 or DCM3, according to Fig. 16.Two different options for P π/2 have been selected for the simulations, both in DCM2 (see Fig. 18).They are as follows.
1) Point P π/2−A : P π/2 is located in DCM2, but far from the boundary between this mode and DCM3.This position is achieved with d = 0.33 and R = 73.1 Ω. 2) Point P π/2−B : P π/2 is also placed in DCM2, but very close to the boundary between this mode and DCM3.This position is attained with d = 0.282 and R = 110 Ω.The coordinates of P π/2−A are k 1 (π/2) = k 2 (π/2) = 1.28, whereas those of Theoretical and simulated line current waveforms for the design corresponding to P π/2−A are shown in Fig. 19   the end of the switching period.Finally, Fig. 20(d) corresponds to operation in DCM1, as can be deduced after comparing it with Fig. 12(d).It should be noted that the value of i L1 (t, ϕ) remains slightly positive when i D (t, ϕ) reaches zero, according to the operation in DCM1.
Similarly, theoretical and simulated line current waveforms for the design corresponding to P π/2−B are shown in Fig. 21 23.These waveforms agree with those in Fig. 20 for the same line angles, the only difference being that i L1 (t, ϕ) is negative when the line voltage is also negative, as expected.
Finally, the Ćuk PFC shown in Fig. 11(c) was simulated in the same conditions as the SEPIC PFC given in Fig. 11(a).The results for the line current during a line period and for currents i L1 (t, ϕ) and i D (t, ϕ) during a switching period agree with those for the SEPIC PFC.

B. Validation by Experimental Results
A prototype SEPIC PFC was used as testing bench to verify the method proposed in this article for studying the operation Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.This prototype was initially designed to operate as ideal automatic RE, i.e., in Case 1, meaning α < M π/2 and P π/2 placed in DCM1.To achieve the operation at this point, L 1 = 3.22 mH, R = 20.9Ω and d DCM = 0.3.Fig. 25 shows the line current waveform in these conditions, whereas Fig. 26 shows the waveforms corresponding to i L1 and i D for ϕ = 90 • and ϕ = 15 • .As predicted, placing P π/2 in DCM1 means operating in this mode for the entire line angle.This can be easily deduced by comparing Figs. 26 and 12(b).As expected, the line waveform was an almost perfect sinusoid.In fact, the measured THD was 4.4%.traces in the experimental results) are both on the transformer primary side, whereas i D is placed on the transformer secondary side.Therefore, i D values (blue traces in experimental results) must be 1/0.318= 3.145 times as high as i D (green traces in simulations).In all cases, there was excellent agreement between simulated (Fig. 20) and experimental (Fig. 28) results, helping to validate the method proposed in this article, not only by simulation, but also by experimental results.These comments can be extended to the waveforms shown in Figs.21 and 29 for the converter operating at point P π/2−B .

VI. CONCLUSION
This article presents a general, systematic method for studying the operation of dc/dc converters that involve three DCMs when they are used as automatic PFCs.This study enables accurate determination of the line current, which is essential for evaluating converter performance in this application.When a dc/dc converter is used for this purpose, the converter duty cycle is kept constant during the line period, the input voltage is a rectified sinusoidal waveform, and the output voltage is kept constant due to a bulk capacitor connected at the output port.In this situation, determination of the input current waveform is a primary concern for evaluating the feasibility of the converter as an automatic PFC.
The procedure to analyze the feasibility of a given dc/dc converter with three DCMs to be used as automatic PFC starts with a thorough study of the converter as a conventional dc/dc converter operating in a closed loop.To that end, two dimensionless parameters k 1 and k 2 must be defined.Moreover, a map of four conduction mode regions (one CCM and three DCMs) can be drawn in a plane called the k 1 k 2 plane.For any value of the converter dc conversion ratio, a map of conduction regions can be drawn.The operation of the converter at a given constant dc conversion ratio and load corresponds to placing the operating point (defined by the values of k 1 and k 2 ) in the proper conduction region of the appropriate map.If the dc conversion ratio changes and the load remains constant, then the operating point remains constant, but the map changes and therefore the operating point may be placed in a different conduction mode region.On the other hand, if the dc conversion ratio remains constant and the load changes, then the map remains constant, but the operating point moves along a straight line called the "trajectory," determined by α = L 2 /L 1 , (the ratio of inductances).Consequently, the operating point may again be placed in a different conduction mode region.
After this thorough study of the converter working as a conventional dc/dc converter, we can determine: 1) the value of the dc conversion ratio in each conduction mode as a function of k 1 , k 2 , and the converter duty cycle; 2) the mathematical equations that determine the boundaries between conduction modes in the k 1 k 2 plane, i.e., on the map.
Once these sets of equations are obtained for operation as a conventional dc/dc converter, the study of it as a part of an automatic PFC can be addressed.That must consider the following: 1) the converter dc conversion ratio is continuously changing according to line angle ϕ, because the input voltage is a rectified sinusoidal waveform.Therefore, the map of conduction regions is also continuously changing according to ϕ, even if the peak value of the line voltage is constant; 2) even with a constant load connected at the converter output, the load seen by the dc/dc part of the automatic PFC (i.e., the RE in Fig. 1) is continuously and synchronously changing according to line angle ϕ, thus moving the converter operating point along the trajectory from a given point to zero.Therefore, the two dimensionless parameters k 1 and k 2 must be replaced with k 1 (ϕ) and k 2 (ϕ).
After taking into account these continuous, synchronous variations and the conditions for working as an automatic PFC (constant duty cycle, rectified input voltage, and constant output voltage), we can finally determine the evolution of k 1 (ϕ) (and k 2 (ϕ) = αk 1 (ϕ)) along a quarter of the line period.The evolution of k 1 (ϕ) during the entire line period can be easily deduced due to line current symmetries.The values of k 1 (π/2) and α determine the converter's starting operating point on the trajectory, which is a key concern in converter analysis and design.To work as an automatic PFC, the point with coordinates k 1 (π/2) and αk 1 (π/2), called P π/2 in the article, must be placed in a DCM.
As demonstrated, the evolution of k 1 (ϕ) is the key point in determining the converter input current, and therefore the line current.In fact, the article demonstrates that the input current is proportional to k 1 (ϕ)/|sin(ϕ)|.The article included an example using the proposed method: SEPIC and Ćuk converters used as automatic PFCs.The study shows that by placing P π/2 in DCM1, ideal automatic PFC (sinusoidal input current) is achieved, which is a well known result.However, converter behavior when P π/2 was placed in either DCM2 or in DCM3 (lower value of the input inductor) had not been determined before.Applying the proposed method, the input current waveform was calculated in these cases, showing that the design in these conditions leads to low distortion in the line current, and therefore quasi-ideal automatic PFC can be achieved.These analytical conclusions were validated by simulation and experimental results, verifying the predicted line current and diode waveforms in several significant line angles (90 • and line angles corresponding to conduction mode changes).

Fig. 1 .
Fig. 1.Implementations of active PFCs based on the use of DC/DC converters working as RE: (a) Control based on the use of an analog multiplier.(b) Control when the DC/DC works as an automatic RE.

Fig. 2 .
Fig. 2. Graphical determination of the conduction mode: (a) Converter operating in the CCM.(b) Change of conduction mode when load resistance R increases up to R max .

Fig. 3 .
Fig. 3. Main quantities involved in the operation of an RE.

Fig. 4 .
Fig. 4. Graphical evolution of the conduction mode of a converter with only one DCM when it is working as ideal RE: (a) Situation corresponding to operate in the CCM when ϕ = π/2.(b) Situation corresponding to operate in the CCM when 0 < ϕ < π/2.(c) Movement of k(R, ϕ) and k crit_cl (M π/2 , ϕ) when 0 ≤ ϕ ≤ π/2.(d) Change of conduction mode when load resistance R increases up to R max .

Fig. 5 .
Fig. 5. Example of waveforms corresponding to the current passing through the diodes in a DC/DC converter with one CCM and three DCMs: (a) CCM.(b) DCM1.(c) DCM2.(d) DCM3.

Fig. 6 .
Fig. 6.Waveforms corresponding to the current passing through the diodes in two examples of boundary conditions: (a) Boundary between CCM and DCM2.(b) Central point P C .

Fig. 7 .
Fig. 7. Example map of conduction modes for a given value of M .

Fig. 15 .Fig. 16 .
Fig.15.Conduction map that summarizes the information given in the maps in Fig.14.
(a) and (b), the normalized line current waveform can be obtained.Two design examples are shown in Fig. 17 . In both examples, P π/2 is placed in DCM2.

Fig. 18 .
Fig. 18.Design points used for validating the theoretical predictions.
(a) and (b), respectively.The theoretical line waveform (in normalized version) was derived by evaluating k 1 (ϕ).The values of line angles where the conduction mode changes are ϕ 2−3 = 56.38 • and ϕ 3−1 = 30 • , obtained from (70)-(72).Fig.20shows simulated i L1 (t, ϕ) and i D (t, ϕ) waveforms during a switching period corresponding to several significant line angles.As expected, the waveform shown in Fig.20(a) corresponds to operation in DCM2 (i.e., i L1 (t, ϕ) reaches zero before the end of the switching period, when i D (t, ϕ) is still positive).Operation in the boundary between DCM2 and DCM3 is observed in Fig.20(b), also as predicted.It should be noted that this boundary is achieved when i D (t, ϕ) reaches zero just at the end of the switching period, as Fig.20(b) shows.Fig.20(c)  shows the boundary between DCM3 and DCM1, where i L1 (t, ϕ) and i D (t, ϕ) reach zero at the same time and remain at zero until Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
Fig. 21.Line current waveforms corresponding to the SEPIC PFC shown in Fig. 11(a) working in design point P π/2−B : (a) Predicted normalized waveform.(b) Simulated waveform.
A Systematic Method for Studying the Use of DC/DC Converters With Three Discontinuous Conduction Modes as Automatic PFCs Duberney Murillo-Yarce , Member, IEEE, Juan Rodríguez , Member, IEEE, Marta M. Hernando , Senior Member, IEEE, Aitor Vázquez , Member, IEEE, and Javier Sebastián , Life Senior Member, IEEE , i o (ϕ) is the current injected by the dc/dc converter into the parallel circuit made up of the bulk capacitor C B (designed to filter the current component of twice the line frequency) and the load resistor R. It should be noted that bulk capacitor C B is large enough to ensure that voltage V o remains constant in spite of the double-line frequency instantaneous power mismatch.

TABLE II PARAMETER
VALUES USED IN SIMULATIONS AND EXPERIMENTAL RESULTS