Fast-Processing Capacitor Voltage Balancing Algorithm for Single-End Five-Level NPC Converters Based on Redundant Level Modulation

Five-level neutral point clamped (5L-NPC) topologies have been proposed for the medium-voltage grid and drive applications since the 1990s. However, their practical implementation has been hindered due to the inherent capacitor voltage drift issue, especially in a single-end configuration. This work proposes a fast-processing, carrier-based voltage balancing algorithm to address this issue, which is based on the latest redundant level modulation (RLM) concept. The proposed approach is fully based on closed-form expressions and basic logic operations, which can be straightforwardly programmed in microcontrollers, as enabled by a fully transparent mathematical model. In contrast, the existing methods treat it as a black box problem, which requires mandatory PI/PID controllers that complicate the implementation. This method shows effective and superior voltage balancing performance against existing methods without affecting the converter output capacity throughout all operating conditions. The fundamental principles and analysis of the capacitor operation are presented to enable a better understanding of the problem and its solution. This work also evaluates the increased switching actions as a side effect of the RLM operation, which is the mandatory cost for all known modulation-based voltage balancing approaches for 5L-NPC converters. For comparison across different systems, a new normalization term is proposed to quantify the capacitor voltage ripples for evaluation with the switching frequency factored in.


Fast-Processing Capacitor Voltage Balancing
Algorithm for Single-End Five-Level NPC Converters Based on Redundant Level Modulation Jun Wang , Member, IEEE, Wenzhi Zhou , Member, IEEE, Wei Xu , Student Member, IEEE, and Xibo Yuan , Senior Member, IEEE Abstract-Five-level neutral point clamped (5L-NPC) topologies have been proposed for the medium-voltage grid and drive applications since the 1990s.However, their practical implementation has been hindered due to the inherent capacitor voltage drift issue, especially in a single-end configuration.This work proposes a fast-processing, carrier-based voltage balancing algorithm to address this issue, which is based on the latest redundant level modulation (RLM) concept.The proposed approach is fully based on closed-form expressions and basic logic operations, which can be straightforwardly programmed in microcontrollers, as enabled by a fully transparent mathematical model.In contrast, the existing methods treat it as a black box problem, which requires mandatory PI/PID controllers that complicate the implementation.This method shows effective and superior voltage balancing performance against existing methods without affecting the converter output capacity throughout all operating conditions.The fundamental principles and analysis of the capacitor operation are presented to enable a better understanding of the problem and its solution.This work also evaluates the increased switching actions as a side effect of the RLM operation, which is the mandatory cost for all known modulation-based voltage balancing approaches for 5L-NPC converters.For comparison across different systems, a new normalization term is proposed to quantify the capacitor voltage ripples for evaluation with the switching frequency factored in.

I. INTRODUCTION
M ULTILEVEL converters have been actively researched in past decades as the solution for medium/high-voltage conversion systems for grid applications.Given the limited rating of power semiconductors, voltage source converters need to be constructed in multilevel topologies to enable the handling of a medium/high voltage.The family of multilevel topologies traces back to 1979 when the three-level neutral point clamped (NPC) topology was first brought up in [1].To cope with a higher voltage at upstream sections of the power grid, a higher number of voltage levels is required.As possible solutions, modular multilevel converters and cascaded H-bridges [2], [3] can be stacked to achieve a higher voltage handling capability, while their power density tends to be low due to the single-phase, bulky capacitors and a higher count of devices.Alternatively, NPC topologies with higher voltage levels have been explored as derivations of three-level NPCs, such as the four-level π-type [4], [5] and four-level active NPC (ANPC) converters [6], because they benefit from the common dc-link capacitor configuration and lower count of both active and passive devices offering better power densities.
Five-level NPC (5L-NPC) converters can be utilized in medium-voltage applications (e.g., 4, 6.6, or 10 kV), such as motor drive [7], [8], [9] or grid-connected converters for MVDC [10] and STATCOM [11], [12] systems.Various 5L-NPC topologies have been proposed, such as the diode-clamped [7], [8], [13] and E-type [14] configurations.Fig. 1 illustrates a generic 5L-NPC structure that outputs five voltage levels from one phase leg.However, as reported in [10], [15], and [16], the voltage drifting is an inherent issue for 5L-NPC topologies, especially in a single-end configuration with a passive front end, which has been hindering their applications.To function as intended, the four capacitor voltages need to maintain at a quarter of the dc link, while they completely drift away under regular sinusoidal pulsewidth modulation (SPWM).There are several approaches to address this issue.The first category is to install auxiliary voltage balancers [7], [8], [13], [14] to regulate the capacitor voltages.However, this approach suffers from the additional hardware and power devices, which contradicts the reliability, efficiency, and power density targets.
The second category is modulation-based voltage balancing approaches without introducing additional circuits.There are a few common degrees of freedom to realize modulation-based voltage balancing.The first option is the redundant switching state, which is commonly effective in ANPC topologies, such as [17].However, there is no such redundancy in a 5L-NPC converter.The second option is the zero-sequence signal injection (ZSI) [18], [19], which is equivalent to the nearest three vector [20], [21], [22] approach in space-vector modulation (SVM), utilizing the redundancy in between phase voltages that cancels out in the line voltages.The ZSI approach is widely used in three-level converters [18], [19], while it is reported to significantly lose its effectiveness in a single-end 5L-NPC converter under a high power factor cos ϕ and a high modulation index M, as demonstrated in [12] and [23].As a solution to ease the problem, the active-front-end (back-to-back) configuration is applied to extend the operating range of a 5L-NPC converter [9], [10], [15], [24], [25], [26].However, this approach still cannot reach the full operating range (e.g., M > 0.94 and cos ϕ = 1) [26] and it limits the application of 5L-NPC converters in the systems with a passive front end.
As a contribution, this article proposes a fast-processing algorithm to solve the fundamental voltage balancing issue in 5L-NPC topologies to enable their practical implementation.This work utilizes and extends a timely concept, RLM proposed in the authors' previous work [32], [33], [43] for four-level NPC converters.In the context of a 5L-NPC, this work presents a complete analysis explaining the necessity of applying RLM and a transparent mathematical model of the solution leading to an optimized utilization of the redundant level thanks to the fully identified boundary conditions of duty ratios, which does not exist in the literature.As a result, the proposed approach is easy to implement with regular level-shifted carriers and outperforms other alternatives, which offer the following features.r Mathematically expressed boundary conditions to maxi- mize the dynamic performance without violating the modulation rules.
r Addressed level-skipping problem by appropriately limit- ing the boundary conditions of duty ratios r Effective over the full operation range of modulation index (M = 0-1.15),power factor (cos ϕ = 0-1), low fundamental frequency, and low switching frequency

A. Operation Principle of a 5L-NPC
The operation principle of a 5L-NPC is illustrated in Fig. 2 with PWM through level-shifted carriers.As the dc-link voltage is split to four quarters by the four capacitors in series (C1-C4), the converter phase leg outputs five voltage levels (L1-L5) to synthesize the fundamental-frequency component commanded by the sinusoidal reference voltage V ref .

B. Neutral Point Currents and Capacitor Voltage Variation
As the 5L-NPC converter outputs currents, it draws neutral point (NP) currents (i N4 , i N3 , i N2 ) from the dc-link NPs.For example, when one phase leg output v xN is tapped onto L4, the load current of this phase i x is drawn from the corresponding NP contributing to i N4 .The NP currents lead to the charge or discharge of the dc-link capacitors, causing their voltages to vary during the converter operation.The deviations (ΔV Cn , n = 1, 2, 3, 4) of the capacitor voltages are defined as follows: Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
where ΔV Cn-ref is the reference capacitor voltage, which normally equals a quarter of the dc-link voltage V dc .In one switching cycle T sw , the effect of NP currents on the capacitor voltages can be derived into three sets as follows.
The NP currents are the sum of all phase legs, with their average value within one switching cycle expressed as follows: ) where D nx is the original duty ratio of level n (n = 1, 2, 3, 4, 5) of phase x (x = a, b, c in a three-phase system).The abovementioned expressions represent the capacitor voltage variation as a function of the load current.

C. Capacitor Operation and Voltage Balancing Problem
To understand the operation of capacitors in a 5L-NPC, this work proposes to analyze it through capacitor operation diagrams (CODs) as illustrated in Fig. 3.When the power factor is unity, the most problematic issue is ΔV C3+C2 , because it witnesses the discharge (red) area throughout a fundamental cycle without any charge (blue) area.Without any control scheme or auxiliary circuits, V C3+C2 will collapse to zero.In contrast, the CODs show that the dc-link capacitors are self-balanced regarding V C3−C2 and V C4−C1 over fundamental cycles.The charge and discharge of V C3-C2 only occur when the third level (L3) is utilized.These observations can inform the priority of control objectives to balance these capacitors.When an unbalance is present, there are three control objectives (OA, OB, and OC) to regulate the capacitor voltages by pulling back their deviation within one switching cycle as follows: where the minus sign indicates the compensation of unbalance.OA is the top priority according to the analysis in this section.

III. RLM IN 5L-NPC
To solve the challenging voltage balance problem in 5L-NPC topologies, an extra degree of freedom needs to be utilized, which is referred to as the RLM.Without violating the average output voltage in one carrier cycle, RLM introduces additional voltage levels to enable extra control on capacitor voltages.Fig. 4 illustrates examples of converter output voltage patterns in one switching cycle with the equal average voltage (volt-second Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE I COMPUTATION OF DUTY RATIOS AND CONSTRAINTS
product) V x_avg established.The additional voltage levels are not required for synthesizing the fundamental-frequency component, hence they are "redundant," while they can offer extra controllability over capacitor voltages for balancing purposes.RLM is introduced in a three-level NPC inverter [29] or a fourlevel NPC inverter [33] to introduce one extra voltage level when needed to achieve voltage balancing control in these topologies.This operation results in three voltage levels appearing in one switching cycle, as illustrated in Fig. 4(b), instead of two voltage levels in regular modulation [Fig.4(a)], which is named RLM-3 in this work.However, in the case of a 5L-NPC converter, RLM-3 can only reduce the discharge period (i.e., the red area in Fig. 4), while it cannot introduce any charging period.As analyzed in Fig. 3(a), under a unity power factor, this still leads to the complete discharge/voltage drift of C3+C2.
Therefore, in the 5L-NPC case, it is necessary to introduce another additional level, i.e., the fourth level, to enable a bidirectional control by gaining a charge period (i.e., the blue area) in one switching cycle.Therefore, this operation is named RLM-4.This special modulation only alters the output voltage pattern on a switching cycle basis and subsequently alters the highfrequency output behavior of the converter without affecting the fundamental-frequency output.The downside of it is the additional switching actions, which lead to increased switching loss and high-frequency harmonics, as reported in [29] and [33].This is a mandatory running cost for balancing the capacitor voltages in the 5L-NPC, given the above-mentioned theoretical analysis.
Note in this case the average voltage in one carrier cycle is still maintained the same, e.g., 0.3 p.u., throughout the three cases illustrated in Fig. 4.This rule is guaranteed by introducing two offset values ΔT 1 and ΔT 2 to the duty ratios in the manner of ( 7)- (10), considering V ref is between 0 and 0.5 as an example.
where D n is the original duty ratio of level n (n = 1, 2, 3, 4, 5); and D' n is the altered duty ratio.This alteration also ensures that all duty ratios add up to unity.As the fundamental constraint, all the altered duty ratios should be greater or equal to zero to avoid modulation errors.For example, when V ref is between 0 and 0.5, these constraints are The computation of duty ratios under different V ref is summarized in Table I along with the constraints.The optimal offset values ΔT 1 and ΔT 2 are found in the control algorithms below as it becomes a 2-D problem.

A. Regulate C3 and C2 (Middle Capacitors) Through RLM
As analyzed in Section II, the top control priority is Objective A to regulate the voltage sum of C 3 and C 2 .For an individual phase leg in a three-phase converter, this control objective can be considered as one-third of the total target for simplicity.Since the RLM-4 operation also alters the duty ratio of the middle-level D 3x , the desired value of D 3x can be found in Objective B, which concerns the neutral current I N3.Note this manipulation of duty ratio is for each phase independently, which means the process is individually repeated in each phase.
With two unknowns, the above-mentioned two equations can be solved to yield the closed-form solutions for ΔT 1 and ΔT 2 as follows: Note this method factors in both the polarity and amplitude of the load current i x and the measured voltage unbalance, so it simplifies the algorithm by avoiding looking up a table that is indexed by the polarity of the load current and the capacitor voltage deviation as applied in [36].Moreover, the compensation level is quantitatively worked out from the load current level and the control objectives through the models, in contrast to a Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.fixed compensation strength (e.g., a fixed dwell time in [36]).This means the proposed method achieves precise control of the control objectives that do not over/under-compensate the imbalance of capacitor voltages.As an illustration, the COD becomes Fig. 5 when equal charge and discharge of C2+C3 is achieved by RLM in each switching cycle.

B. Boundary Conditions of ΔT 1 and ΔT 2 in RLM
The retrieved reference values ΔT 1-ref and ΔT 2-ref can be unrealistic because they attempt to pull back the voltage unbalance within one carrier cycle, which may cause modulation errors.Therefore, ΔT 1-ref and ΔT 2-ref need to be limited to comply with the constraints listed in Table I.Without violating the constraints in (11), the achievable combinations of ΔT 1 and ΔT 2 values are a 2-D pool, which can be illustrated as an area in Fig. 6.
As can be solved from (11), the coordinates can be expressed as follows: Hence, the boundary conditions of ΔT 1 and ΔT 2 can be mathematically expressed in each switching cycle, e.g., by f 1 and f 2 in Fig. 6.Note that Objective A only concerns ΔT 1 as expressed in (12), which needs to be prioritized.Therefore, ΔT 1 should be selected before proceeding to find ΔT 2 .For example, if ΔV C3+C2 needs to be charged, a ΔT 1 is selected first in the blue area (e.g., ΔT 1 = 0.4) in Fig. 6 following (14).Then, between the upper bound and the lower bound at ΔT 1 = 0.4, a ΔT 2 is then selected following (15).Example 1 in Fig. 6 shows a ΔT 1 of 0.3 leading to a charging area equal to the discharge area for ΔV C3+C2 , which reflects the output voltage pattern in Fig. 4(c).

C. Regulate C4 and C1 Through ZSI
Once C2 and C3 are regulated, the voltage balance between C4 and C1 can be solved by utilizing another degree of freedom, ZSI.The principle of ZSI is injecting a zero-sequence signal V ZSI into the reference voltages The added zero-sequence component is canceled out in the line-to-line voltages hence.By injecting a V ZSI , the charge/discharge status of the capacitors can be manipulated to serve the purpose of voltage balancing.The V ZSI is selected out from the constrained range as follows to avoid over-modulation: As expressed in (6), Objective C concerns the sum of all the NP currents.When there is a zero-sequence signal, the altered duty ratios lead to the NP currents as follows: By iteratively traversing all possible V ZSI values within one carrier cycle, an optimal V ZSI can be found that yields the smallest objective function to track the control target, which is the difference between the altered sum of NP currents and the reference as follows: (22) This "optimal searching" approach for selecting V ZSI is similar to the common approach in a three-level converter [29], [44], which can be implemented in real-time microcontrollers with a fixed step size or a fixed number of trial attempts.

A. Carrier-Based RLM
The proposed RLM can be implemented through regular level-shifted carriers.The alteration of duty ratios can be achieved by two steps: (1) split the original modulating wave into four waves corresponding to the four carriers; and (2) introduce two offsets V RLM1 and V RLM2 for each phase's reference voltages individually corresponding to the two variations ΔT 1 and ΔT 2 , respectively.The reason for introducing two offsets is to add two extra redundant levels, instead of one offset to Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.achieve one extra level (RLM-3) in [33].Note the "split" function in the first place does not affect the original duty ratios.The relationship between the duty ratio variation and the offset values can be found as follows:

TABLE II SPLIT FUNCTION AND RLM ALTERATION THROUGH OFFSETS
The split functions and introduction of offsets are achieved by the expressions summarized in Table II.The effect of this operation is visualized in Fig. 7.As the figure shows, in one carrier cycle, the offset values V RLM1 and V RLM2 lead to an alteration of duty ratios to realize the desired ΔT 1 and ΔT 2 , while the synthesized average output voltage of this cycle remains equal.Fig. 7(b) corresponds to Example 2 in Fig. 6, in which an overall charge of V C3+C2 is achieved.
This carrier-based approach has been implemented in threelevel [28], [29] and four-level NPC converters [33] achieving an RLM-3 operation, while this work extends it to achieve an RLM-4 operation as required by a 5L-NPC topology.Note it is possible to translate the proposed carrier-based implementation into an SVM, since the equivalence between them has been well established in [45].Although, the vector space in a three-phase 5L-NPC converter is 125 vectors, which can be complex to apply in SVM.Additionally, while it is more complex to expand SVM for a multiphase system due to the number of vectors growing exponentially, the proposed carrier-based approach can be extended straightforwardly, because the closed-loop RLM-4 operation is independent between phases.

B. Closed-Loop Control and Modulation Scheme
For the RLM stage, Fig. 8 illustrates the closed control loop to regulate C3 and C2 that tracks the control Objectives A and B. After computing the desired ΔT 1-ref , a saturation stage (Sat.1 in Fig. 8) is applied as below to retrieve the feasible ΔT' 1 as follows: After a ΔT' 1 is selected, it informs the computation of the boundaries for ΔT 2 following the pool in Fig. 6 expressed by the mathematical functions defined in (16).Note that the correct boundary conditions are important to achieve the full voltage balancing capability.As the contribution of this work, these boundary conditions are expressed mathematically through closedform expressions.If the boundaries are limited, the converter  may lose bidirectional controllability.For example, if the selection of ΔT 1 is limited to the red area in Fig. 6, the control loop is not able to charge C3+C2.In other words, a full utilization of the whole range in Fig. 6 results in the optimal duty ratio toward the voltage balancing commands.
The flow of the control scheme and the alteration of modulating waves is illustrated in Fig. 9. Starting from the original sinusoidal modulating waves, the algorithm first alters the waves by injecting a zero-sequence signal to track the control objective C. The next step is to split the waves as a preparation for the carrier-based implementation of RLM.With the control loop shown in Fig. 8, the variations of duty ratios and the offsets are found and applied in the waves.Eventually, the altered waves are fed to the block with level-shifted carriers to generate the gate signals and control the converter behavior.

C. Over-Modulation Strategy
The ZSI block contains two stages -the first stage optionally injects the below ZSI component V ZSI-3rd into the original sinusoidal waves, which is a common third-order harmonic term, e.g., implemented in [28], to extend the maximum modulation index M to 1.15.
On top of the waves containing the third-order harmonics, the second stage of this block performs the "searching" algorithm in Section III-C to find an "additive" zero-sequence component V ZSI to achieve the control toward Objective C to balance the C4/C1 voltages.After these two stages, the modulating waves are modified as follows: By design, the voltage balancing stage does not undermine the third-order harmonic injection stage, which is achieved by working out the range of V ZSI after the third-order harmonic is injected, as shown in the following equation: Hence, this overmodulation strategy enables the converter to achieve the maximum output voltage range (M = 1.15).

D. Level-Skipping Problem and Implementation of Dwell Levels
Fig. 10(a) illustrates the case where the selection of ΔT 2 falls on the boundary, which leads to the altered duty ratio of the L3 reaching zero.In this case, the converter output voltage skips level 3, which is undesirable considering the switching loss, device voltage stress, and harmonic performance, similar to the "minimum-energy" operation in [15].
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.A dwell time T dwell can be implemented by slightly revising the boundary conditions for ΔT 2 after a ΔT 1 is selected, as shown in Fig. 11.
The coordinates for the altered boundaries are where T sw is the period of one carrier cycle.Shrinking the boundary conditions for ΔT 2 ensures that the altered duty ratios ( 7)- (10) are always greater than zero, which avoids the levelskipping problem.As shown in Fig. 10(b), this approach can effectively result in a dwell level in the output voltage.

A. Voltage Balancing Under Various Operating Conditions
To evaluate the effectiveness of the proposed voltage balancing algorithm, a simulation model is developed in MAT-LAB/Simulink with the parameters listed in Table III given a medium-voltage (4 kV) single-end inverter for grid applications.The performance of the control scheme is shown in Fig. 12. Fig. 12(a) shows the case where the converter operates under a range of modulation index M and fundamental frequency f 0 .This figure demonstrates that the proposed control method performs well -it not only maintains the capacitor voltages around the reference values, but also suppresses the ripples to high-frequency components on a switching cycle basis.Fig. 12(b) shows the performance under various modulation index and power factor angle ϕ.In the worst case where a high modulation index M and a high-power factor cos ϕ are in place, the control scheme offers satisfactory voltage balancing capability.Meanwhile, it is visible that the C4/C1 voltages show larger ripple under a low power factor, which is caused by the limitations of the ZSI method that is applied to balance the C4/C1 voltage -a similar observation is made in the existing method [35].When there is a step change of the operating point, e.g., modulation index, the control loop offers a seamless transition with no observable distortion.Fig. 12(c) demonstrates the validity of the proposed approach under the maximum modulation index M = 1.15 achieved with third-order harmonic injection in the ZSI stage.In short, the proposed scheme is effective and versatile under all operating conditions.However, low-frequency oscillations can still appear in the outer capacitor C4/C1 voltages when the power factor is low due to the limitations of the ZSI approach under such an operating point, which is similar to the case in a three-level NPC converter.
Additionally, the proposed approach is evaluated in the case of nonlinear loads, e.g., a three-phase diode rectifier with an RC load.The performance of the converter is shown in Fig. 13 in this case.The nonlinear load introduces significant odd-order, low-frequency harmonics in the converter output phase current, while the proposed algorithm still performs very well, because it can successfully suppress the capacitor voltage ripples down to high-frequency ripples as a result of the cycle-by-cycle voltage balancing, which is not influenced by the low-order components in the load current.The proposed scheme is also effective in the case of nonlinear loads containing rich even-order harmonics as evaluated in simulation.
A zoomed-in view of the steady-state capacitor voltages is shown in Fig. 14, which shows the capacitor voltage ripples are all suppressed to high-frequency ripples.

B. Power Loss and THD in a Five-Level E-Type NPC
The power loss and THD performance of the proposed method are evaluated in a five-level E-type NPC (5L-ENPC) converter, shown in Fig. 15(a), in this section.As references, the results are compared against (1) a two-level counterpart as a baseline; (2) Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.an ideal 5L-ENPC converter with four ideal dc sources in series to form the dc-link, for which the ordinary SPWM is applied; and (3) a 5L-ENPC converter equipped with an auxiliary voltage balancing circuit (voltage balancer) shown in Fig. 15(b), which is an alternative to balance the capacitor voltages [13] and commonly implemented as buck-boost circuits.Note if the proposed modulation-based scheme is implemented, there is no need to install the auxiliary circuits.In the case of employing

TABLE IV POWER DEVICE SELECTION FOR THE 4 KV 5L-ENPC CONVERTER
the voltage balancer, standard SPWM modulation can be applied with a simple ZSI stage to balance the middle NP N as implemented in [13].The selected power devices are listed in Table IV.
Silicon-based IGBT devices from Infineon are selected in this case for the evaluated 4 kV application.As the baseline, both the switching voltage and static blocking voltage are the full dc-link voltage in a two-level topology.Hence, a 6500 V rated  device (FZ250R65KE3) is selected to leave a >50% margin for the switching voltage.For the reference case with the voltage balancer, the power devices are implemented with 3.3 kV rated power devices FZ825R33HE4D.
The power loss of the converter is estimated in Simulink/PLECS with the proposed RLM-4 algorithm applied and the specifications listed in Table III.The two-level converter case applies regular SPWM.Fig. 16 shows that the 5L-ENPC converter can offer an efficiency of above 96% when the modulation index is close to unity across various currents.
Fig. 17 shows a breakdown of the loss distribution among devices.It can be seen that the switching loss is the dominant loss mechanism in this case, which is typical in a medium-voltage converter.
Fig. 18 shows a comparison of phase leg power loss of the 5L-ENPC (RLM) case against the alternative options.The 5L-ENPC (RLM) case shows a nearly halved loss compared with the two-level case.Although the switching voltage in the five-level converter is only 25% of a two-level counterpart, the loss reduction is only 50% due to the side effect of the RLM operation to balance the dc-link capacitor voltages.Compared Fig. 18.Phase leg loss versus output power (cos ϕ = 0.9, M = 0.9, f sw = 5 kHz).Fig. 19.Converter loss versus converter switching frequency (cos ϕ = 0.9, M = 0.9, output power = 400 kW).
with the ideal case, the switching loss is tripled by the RLM-4 operation, because it introduces four additional switching transitions in each switching cycle compared with SPWM as illustrated in Fig. 4.This side effect applies to all the other existing modulation-based methods (e.g., [36] and [35]) due to the principles of applying the RLM-4 pattern that is mandatory in a 5L-NPC converter.Note the ideal case is for theoretical comparison only and not feasible in real applications.Additionally, this drawback on increased switching transitions can be moderated by applying low-switching-loss wide-bandgap power devices, e.g., Silicon Carbide MOSFETS, as pointed out in [46].Fig. 19 shows the comparison of loss on a converter level.Another reference case with the auxiliary voltage balancer is provided.The charging inductors L B2 and L B1 are sized as 5 mH, similar to [8], to limit the charging current to <100 A under a switching frequency f bsw of 5 kHz.Acting as an independent part, the dc-link voltage balancer leads to power losses adding on top of the overall converter loss of an ideal case, as plotted in the yellow curve.When the phase leg f sw is lower than 3.5 kHz (depending on the balancer's design), the RLM case still shows better efficiency overall,  since the auxiliary circuit introduces comparable conduction and switching losses.Note this evaluation only considers the power device losses with the inductor (L B2 and L B1 ) losses neglected.
Fig. 20 shows a comparison of the harmonics performance of the converter output line voltages in the evaluated cases.Despite the usage of redundant voltage levels, the 5L-ENPC case still shows an improved THD of 39% compared to 60% in the two-level case, with the significant harmonics at the switching frequency (5 kHz) moderated.In comparison, Fig. 20(c) shows that the configuration with an auxiliary balancer can yield the lowest THD and lower harmonics at multiples of f sw, since the converter is able to output the regular five-level waveforms through SPWM without introducing additional redundant levels.Overall, the proposed modulation-based voltage balancing scheme can achieve a comparable performance as auxiliary voltage balancer circuits while it avoids the additional hardware circuits, which increase the cost, complexity, and size of the converter.

C. Comparison With Existing Methods
To provide a comparison, Table V summarizes the fundamental differences between this work and the existing methods in literature with the key points explained as follows.The methods in [7], [8], and [14] are based on auxiliary balancing circuits or back-to-back structures that introduce additional hardware.For modulation-based approaches [35], [36], [41], although the implementation appears different, these approaches fundamentally utilize redundant voltage levels to achieve voltage balancing, which is similar to the RLM-4 concept introduced in this work.Thanks to the fully resolved model, the proposed algorithm in this work uniquely involves only closed-form equations and logical operators and does not require mandatory PI/PID controllers, which achieves fast processing of real-time signals for closed-loop control.In contrast, Wang et al. [35] adapt PI controllers to process the measured voltage balance into the variation of duty ratios, treating it as a black box problem that does not consider the load current amplitude due to the lack of a complete analytical model.While [36] does not require a linear controller, its compensation values (e.g., ΔT 1 and ΔT 2 ) are found through a stepped lookup table leading to voltage vectors with a fixed dwell time.In contrast, the proposed approach dynamically calculates the duration of voltage levels following the measured level of unbalance and load current to offer a precise control without an under/over-compensation.
Regarding the steady-state performance of voltage balancing, as a metric, a normalized value describing the peak-to-peak capacitor voltage ripples ΔV C_norm is proposed in this work as a function of the actual voltage ripple ΔV C , the load current I rms , capacitances C, the switching frequency f sw and the fundamental frequency f 0 to quantify the evaluation across various systems for a fair comparison.Compared with the common normalization Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.term in [47], the proposed approach factors in both f sw and f 0 , while the classic term fails to capture the impact of f sw.For both f sw and f 0 , the higher they are, the easier the voltage balancing task is.As demonstrated in [29], in the case where the low-frequency oscillation is eliminated by the balancing scheme, a higher f sw can still lead to lower amplitude of the high-frequency NP voltage ripples due to the balancing action achieved on a cycle-by-cycle basis.
For example, in this work, a peak-to-peak voltage ripple of 2.46 V is observed for C4/C1 in the waveforms shown in Fig. 14.With other specifications listed in Table III, the ΔV C_norm is worked out as 9.7 in this case.Based on the disclosed waveforms in [36] and [35], a quantified comparison is conducted and shown in Table VI.Comparing the normalized capacitor voltage ripples, it can be seen that the proposed method in this work yields the best performance, e.g., with a ΔV C_norm of 9.7 compared to 54.7 [35] and 92.3 [36].
Regarding the dynamic performance of voltage balancing, in [35], the variation range of duty ratios is limited to <10% of the original duty ratio (i.e., ±10% of x 1 as visualized in Fig. 11), which effectively limits its dynamic performance.As a comparison, when the reference voltages see a step change, Fig. 21 shows that it takes 25.0 ms for the limited control scheme to track the control command of Objective A, while the full-range scheme proposed in this work only needs 12.5 ms.For Objective B, Fig. 21 Regarding the complexity of implementation, the work in [35] and [41] is based on irregular "overlapped" carriers, which are not straightforward to reproduce.The work in [36] is based on SVM, which is complex for the five-level converter case, and requires predefined lookup tables for voltage balancing purposes.In contrast, the proposed scheme can be adapted with regular level-shifted carriers with the balancing scheme realized in modular blocks as shown in Fig. 9 to alter the modulating waves step-by-step.Overall, the proposed algorithm features a simple and fast-processing implementation with regular carriers while it offers the most effective and versatile control capability.

VI. EXPERIMENTAL VALIDATION
To validate the proposed approach, a 5L-ENPC prototype is built as shown in Fig. 22, and tested in a downscaled test rig.The specifications of the prototype and test rig are listed in Table VII.
The four capacitor voltages are sensed through sensors LV-25P and the three-phase load currents are sensed by LA-25.The control algorithm is developed in a digital signal processor F28335 from Texas Instrument.As Fig. 23 shows, the single-end Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.inverter can successfully achieve voltage balancing under a nearunity power factor (cos ϕ = 0.998) and a high modulation index, which can steadily output five voltage levels.In a zoomed-in view in Fig. 24, the phase output voltage shows four voltage levels as intended by the RLM-4 operation without skipping any levels.
When a step change is applied on the reference voltages for the four capacitors, the control loop can well track the command and demonstrates a decoupled, bidirectional control capability on individual capacitors as shown in Fig. 25.In summary, the effectiveness of the proposed approach is validated in the experiment.

VII. CONCLUSION
This article proposes a fast-processing algorithm to address the voltage balancing issue in a single-end, 5L-NPC converter.As the key concept, the RLM is utilized to gain extra control of the capacitor voltages, for which the principle is explained with the aid of the capacitor operation diagrams (CODs).A closed-loop control scheme is developed and implemented with regular level-shifted carriers.As a result of fully transparent mathematical models and boundary conditions of duty ratios, the proposed approach can achieve maximum controllability without involving opaque PI/PID controllers treating the system as a black box, which makes it straightforward to reproduce in prototyping.Both qualitative and quantitative comparisons are conducted to validate the superiority of the proposed method against existing approaches.An improved normalization term with the switching frequency included is proposed to quantify the voltage ripples for the evaluation of voltage balancing performance across different systems.The authors hope that this easy-to-implement, modulation-based voltage balancing algorithm can enable the 5L-NPC topology to be better adopted in the medium-voltage grid and drive applications.
As a side effect, the RLM-4 operation is found to result in increased harmonics and switching loss due to the tripled switching actions in one carrier cycle, which is considered the mandatory cost for balancing the capacitor voltages in a 5L-NPC converter without introducing additional hardware.In future work, this side effect could be improved through constraining the usage of RLM-4 in the control/modulation flow.

Fig. 9 .
Fig. 9. Flowchart of the control and modulation scheme with visualized modulating waves.
(a) takes 7.5 ms to reach the steady state, while Fig. 21(b) only takes 3.5 ms, which demonstrates the superiority of the proposed scheme.It can also be observed that there are larger voltage ripples in Fig. 21(a) due to the limited controllability.

TABLE VI COMPARISON
OF ΔV ˙norm UNDER A NEAR-UNITY POWER FACTOR