Lossless Clamp Circuit With Turn-OFF Voltage and Current Reduction in High Step-Up DC–DC Converter With Coupled Inductor

A high power density, high voltage gain soft-switching pulsewidth modulation dc–dc converter with a tapped inductor is proposed in this article as a front-end for low-voltage sources in energy generation systems. The leakage inductance is incorporated into the resonant tank, decreasing the component count. The use of the boost capacitor connected in series with the secondary windings of the tapped inductor causes high voltage gain at the low turn ratio of the coupled inductor. By incorporating a resonant passive clamp circuit, not only the voltage spikes on the transistor are restrained, but zero-voltage switching of the transistor and zero-current turning-off of the diodes are obtained. The resonant operation results in low power losses in the switches, providing high efficiency in a wide output power range. Owing to soft-switching operation, the transistor can be driven with a high switching frequency, providing a consolidated design of the high power density converter. The principles of operation of the converter were also analyzed theoretically. Finally, the converter is validated through a laboratory model with a power rating of 300 W and a switching frequency of 200 kHz.

dc for single-phase grid systems to assure grid-inverter operation [1].
In the conventional boost converter, which maintains high efficiency, it is not possible to obtain high voltage gain and high output power simultaneously for several reasons.In the conventional boost converter, high voltage gain requires an extremely high duty cycle; thus, conduction losses increase significantly.Besides, transistor voltage stress is almost equal to the output voltage.Therefore, a transistor with a higher voltage rating and higher R DS(on) needs to be used.Moreover, in a conventional boost converter, a significant reverse recovery current of the output diode can be observed, which additionally increases the overall converter's switching losses.
There are a lot of methods to achieve high voltage gain in nonisolated converters: SEPIC converter under resonant operation voltage multiplier cell, switched inductor, coupled inductor, and others [2], [3], [4], [5], [6], [7], [8].Thanks to the coupled inductor and switched capacitor techniques converging, there is a possibility to achieve both high voltage gain and high efficiency while using a low number of components [1], [9], [10], [11].In a basic tapped-inductor step-up converter, the reverse recovery problem of the output diode is alleviated by the leakage inductance, which limits the slope of the output diode current during the turning-ON of the transistor.On the other hand, the leakage inductance causes voltage overshoots across the switch during turn-OFF.To prevent it in step-up converters with tapped inductors, a snubber circuit is applied.There are several clamp techniques [12], [13], [14] that recover the leakage energy and allow the use of switches with a low voltage rating.
In [5], [6], [8], [10], [15], [16], [17], [18], and [19], the nonisolated step-up converter with a tapped inductor and passive clamp circuit are presented.In these topologies, the passive clamp circuit consists of the diode and the capacitor.In this circuit, the voltage overshoot on the transistor is reduced, and the leakage energy is recovered.Thus, for the transistors driven with the pulsewidth modulation (PWM) technique, their switching conditions are improved.However, the transistor remains switching with nonzero voltage, which results in increased switching losses.In the active clamp technique, an additional switch allows leakage energy recovery and also reduces voltage overshoots on the main transistor [20], [21], [22].Moreover, in that circuit, the zero voltage switching (ZVS) technique may be applied.In this scenario, the effective duty cycle is decreased, and a coupled inductor with a higher turn ratio is required to compensate for this effect.One of the main problems in boost converters with a coupled inductor is the high input current ripple, which requires the use of additional input filters.This problem is solved in interleaved converters [11], [14], [21], [22]; however, such systems require the employment of many more components, and it can be unprofitable in applications with power in the range of hundreds of watts.
In [23], [24], and [25], converters with a coupled inductor and resonant capacitor connected in series with the secondary winding are presented.In such circuits, reverse recovery problems are eliminated.These converters operate in critical conduction mode (CRM) or discontinuous conduction mode (DCM), where conduction losses are high, restraining the efficiency and rated output power.Soft switching may be obtained in the converters with zero-voltage transition, zero-current transition, or active edge-resonant [26], [27], [28] cells.However, in these techniques, an additional active switch is required to achieve soft switching of the main transistor.
High voltage gain can also be achieved in three-winding coupled inductors [7], [29], [30].However, in such circuits, there is a greater problem with recovering energy from the leakage inductance.This means that a larger number of semiconductor and reactance elements must be used in the system to achieve proper operation.
This article presents a high step-up soft-switching PWM dc-dc converter with a tapped inductor (see Fig. 1).In the proposed converter, the passive resonant circuit is used to achieve zero voltage turn-OFF of the transistor, whereas, in a similar topology presented in [10], the transistor is turned-OFF in hard switching conditions.A similar soft-switching technique was used in the SEPIC converter presented in [3] and in the buckboost presented in [2].However, in these circuits, the voltage gain is low because of the absence of a coupled inductor.The novel resonant passive clamp circuit allows for soft-switching operation, enables zero-voltage turn-OFF of a transistor, and improves the efficiency of the converter, maintaining high voltage gain.Similarly, like in [16], the transistor current slope during turning-ON and diode D current slope during turning-OFF are limited by the leakage inductance.This provides ZC turning-ON of the transistor and ZC turning-OFF of the diode.Moreover, clamp diodes D c1 and D c2 do not conduct during the transistor turn-OFF process, and the reverse recovery currents of all diodes are reduced.This article is structured as follows.After a brief introduction, the operation of the converter is described based on the theoretical waveforms and mathematical equations.Furthermore, the design procedure, allowing proper selection of the components, is presented.Eventually, experimental results of the laboratory model are presented to confirm the performance of the proposed converter, and this article is summarized in the last section.

II. PRINCIPLE OF OPERATION
In Fig. 1, the topology of the analyzed converter is depicted.The input circuit is composed of the magnetizing inductor L m with a leakage inductor L Lk and the transistor S. Primary and secondary windings of the coupled inductors, whose turns ratio is N 2 /N 1 , are wound on the same magnetic core.The passive regenerative snubber consists of the resonant capacitor C r , and diodes D c1 and D c2 .Capacitor C c is the switched capacitor.The output filter circuit is formed by the rectifier diode D and the filter capacitor C. The converter can work in two different modes, depending on the capacitor C r charge state during transistor S turn-ON time.The theoretical waveforms shown in Fig. 2 present both the cases when capacitor C r is fully discharged and when a certain amount of charge remains in capacitor C r .
A different theoretical approach was applied depending on the charge remaining in the resonant capacitor C r during transistor turn-ON.The condition that should be met to discharge the resonant capacitor is described in Section IV-B of this article.Fig. 3. Illustrates the converter topology with highlighted current flow paths through the components in different modes of operation during a single switching cycle T S .
The following assumptions were made to simplify the theoretical analysis of the proposed converter: magnetic components are considered ideal apart from the leakage inductance of the tapped inductor; the current in the magnetizing inductance L m in a single switching period is constant; the voltage drops on forward-biased diode D and resistance R DS(on) of the transistors are neglected; parasitic parameters of all components are omitted; the voltages of capacitors C and C c are constant during the single switching period.Mode 1 [t 0 -t 1 , Fig. 3(a)]: For t < t 0 , the current flows through the input voltage source V in , the coupled inductor, capacitor C c , diode D, and the load.At t 0 the transistor S turns ON and the diode D current decreases to 0, the transistor S current rises with a slope determined by the leakage inductance L Lk .The energy is transferred from the input voltage source V in to the inductor.In Mode 1, a voltage drop on the leakage inductance is equal The time span of Mode 1 covers the period when diode D current decreases from I D to 0 and can be defined as Mode 2 [t 1 -t 2 , Fig. 3(b)]: Diode D is reverse-biased at t 1 .The leakage inductance determines the slope of the diode's D current rise; it suppresses the reverse recovery current.The diode D C2 is forward-biased, and capacitor C r discharges resonantly.The energy from the input voltage source V in continues to be transferred to the coupled inductors.The capacitor C c is charged while the transistor S remains ON.The input current and capacitor C c current in Mode 1 are equal to where ω r1 = 1/(n(L Lk C r ) 1/2 ) is the resonant pulsation and Z 1 = n(L Lk /C r ) 1/2 is the resonant impedance.The voltages on the capacitor C r and the leakage inductance L Lk in Mode 2 are The voltage on the capacitor drops to 0 V at the end of the considered interval, leading to obtaining the ZVS condition.Based on (1) and ( 6), 0 V condition on capacitor C r at time t 2 can be written as (7) Therefore, the considered interval is given by If an otherwise certain amount of charge remains in the capacitor C r during Mode 2, it determines the half-period discharge of capacitor C r and is equal to Mode 3 [t 2 -t 3 , Fig. 3(c)]: Mode 3 occurs only if the capacitor C r was completely discharged during Mode 2. At t 2 , the diode D c1 is forward-biased, and the input current i in decreases linearly down to the level of I D (n+1), whereas capacitor C c is charged.In Mode 3, the current of coupled inductors' secondary windings i Cc rises linearly i Cc (t 2 ) = − (v Lk (t 1 )/Z 1 ) sin ω r1 t 2 − t 1(a) .(10) Solving (10) leads to determining the span of Mode 3 (t 2 -t 1 ) The voltage on the leakage inductance is accordingly equal Mode 4 [t 3 -t 4 , Fig. 3(d)]: In this mode, the energy is stored in a magnetic field of the coupled inductors.The current stops flowing through the secondary windings.In t 3 , the diodes D C1 and D C2 are reverse-biased.Similarly, like in Mode 2, the leakage inductance suppresses their recovery currents.
Mode 5 [t 4 -t 5 , Fig. 3(e)]: The transistor S is turned-OFF at t 4 .Forward-biased diode D c1 starts to conduct, and capacitor C r is charged with constant current i in (t 1 ) = I D (n + 1), reaching the voltage level when diode D starts to conduct.If the capacitor C r was completely discharged during Mode 3, the transistor S would turn-OFF at ZVS condition.The instantaneous voltage at t 5 can be defined as If the capacitor C r was completely discharged in Mode 3, the span of Mode 5 is given by and otherwise Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
Mode 6 [t 5 -t 6 , Fig. 3(f)]: In t 5 , the diode D is forward-biased.The current of the diode D rises while both secondary windings current and capacitor C r current decrease.Capacitor C r is resonantly charged during a quarter of the resonance period.Thus, the time span of Mode 6 is equal The instantaneous voltage of the capacitor C r in t 6 transient is equal to its voltage at t 0 and t 1 transients Mode 7 [t 6 -t 7 , Fig. 3

(g)]:
The energy stored in a magnetic field of the coupled inductors in Mode 7 is transferred to the output consisting of the capacitor C and the load resistance R o .

A. Voltage Gain Formula When Capacitor C r is Completely Discharged in Mode 2
In the converter, load current I o is equal to the average current of diode D. Simultaneously, the average current of the capacitor C c in a single switching period is constant at steady-state conditions and equal to 0. Consequently, in period (t 1(a) < t < t 3(a) ), the average current of the capacitor C c flows in the opposite direction than the current in period (t 5(a) < t < t 7 ) and is equal to I o .
The input current at transistor turn-ON is the sum of current I D (n + 1) and a current that flows through capacitor C c in a period of (t 0 < t < t 3a ) multiplied by the turns ratio of the tapped inductor given as: where T S is a period of transistor driving signal and D is the duty cycle.Assuming that the input current within the period of (t 5(a) < t < t 7 ) is equal to current I D and is equal to the capacitor C c current, the input current at transistor turn-OFF transient can be expressed as Therefore based on (1)-( 19), the voltage gain can be expressed as and V Cc to V o ratio can be thus resolved as −2π(n+1

B. Voltage Gain Formula When Capacitor C r is Not Completely Discharged in Mode 2
Assuming the average current of the capacitor C r is equal to zero across a single switching period, the input current in the period of (t 4 < t < t 6 ) is equal to I o .The voltage gain formula can be determined by applying the output power to the input power proportion as (22) In the considered case, V Cc to V o ratio can be expressed as .
(23) Fig. 4 depicts the voltage gain in the function of duty cycle D at four different conditions, which are defined by two different values of f s /f r and R o /Z 1 ratios accordingly.Analysis of Fig. 4 reveals that the voltage gain function is merely dependent on the parameters of the resonant circuit itself.Moreover, the load resistance change has a slight impact on the voltage gain providing steady operation of the proposed converter in a wide range of the output power.

A. Diodes D c1 , D c2 Reverse Recovery Current Reduction
To minimize the power losses in the converter by lowering the maximum voltage across the switch S, transistor turn-ON time should be kept equal or higher than (t 0 < t < t 3 ) period.In case of complete discharging of the capacitor C r at Mode 2, neglecting a short period of (t 0 < t < t 1 ), the minimal value of the duty Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.cycle can be resolved as f s f r1 (24) where + n + 2 . (26)

B. Zero Voltage Transistor Turn-off Region
The transistor can be turned-OFF at zero voltage only if the voltage of capacitor C r is zero at the transistor turn-OFF transient.In this case, the capacitor C r should be discharged in less than a half-wave of the resonant period.This condition is met when Therefore, the condition can be expressed as The condition (28) allows for determining soft-switching regions of the power devices, which are depicted in Fig. 5 for different operating points determined by four f s /f r1 ratios.Analyzing Fig. 5, it is evident that to reduce the power losses in the converter, transistor S should be driven in a way to maintain the soft switching region.Fig. 5 shows that soft-switching operation is possible in a wide range of output power.Even if the converter works in the transistor's hard turn-OFF region at light loads (high values of R o /Z 1 ratios, i.e., low output power), the switch turning-OFF voltage and switching losses remain low.The turn-OFF voltage of the transistor in the hard turn-OFF region (see Fig. 5) is equal to the capacitor C r voltage at t 3 (see Figs.  and 3).Transistor turn-OFF voltage to the output voltage V o ratio can be described by: V. CONDUCTION MODE Operating under continuous conduction mode (CCM) is preferable for lowering input current ripple and reducing conduction losses in converter components.Simultaneously, operation under DCM allows achieving turning ON the transistor at zero voltage.However, thanks to leakage inductance, in CCM, the transistor is turning ON at zero currents.That is why, in the presented converter, DCM operation, for highefficiency and high-frequency applications is not a necessity.In CRM, the maximum input current is two times higher than the average current in magnetizing inductance.In that case, to calculate the CRM region, which determines the region between DCM and CCM, input and output power should be compared where Based on (30), CRM mode can be described as follows: where The curves presented in Fig. 6 can be useful to select a value of inductance for a specific switching period and output resistance.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

A. Voltage Stress
At t 6 the maximum voltage stress across the transistor S, which is equal to the maximum voltage on diode D c1 , is given by (32) The maximum value of the diode D reverse voltage is equal to V out , whereas the maximal reverse voltage of the diode D c1 is in the (t 0 < t < t 1 ) period.Normalized voltage stress of the diode can be defined as

B. Current Stress
The RMS values of the transistor S current, the input current I in , secondary windings' current I Cc , and diode D c1 average current are given in ( 2)-( 40), and they were determined presuming 2nv Lk (t 1 ) = v Cr (t 0 ), with the assumption of the transistor S working in the boundary region of soft-switching.

A. Laboratory Model of the Converter
To verify the theoretical considerations, the laboratory model of the proposed converter was developed and tested (see Fig. 7).Table I collates the main parameters of the converter as well as its component list.
The dimensions of the converter laboratory model are 54 mm × 75 mm × 53 mm.The high power density of 14 kW/dm 3 was achieved thanks to the high switching frequency (f s = 200 kHz).The converter operates in an open-loop system.

TABLE I PARAMETERS AND COMPONENT SELECTION OF THE LABORATORY MODEL
The converter transistor is controlled via TC4451 gate driver, with the power supply voltage at 0-12 V.

B. Coupled Inductor
The design of the tapped inductor was based on an Eshape Sendust magnetic core, which was developed to work with the switching frequency range of hundreds of kHz.To determine the power losses of the magnetic core, current ripples of the magnetizing inductance L m , and the peak input current were calculated as ΔI Lm = 5.3 A and I in_peak = 10.5A assuming: V in = 50 V, G v1 = 7.6, ƞ = 0.9, f s = 200 kHz, and R o(min) = 480 Ω.For a given input current ripple, L m is designed for 24 μH.Primary and secondary windings were wound on the core with Litz wire.Their effective cross-sections were 2.12 mm 2 and 071 mm 2 , respectively.For high-gain converters, one of the major concerns related to high efficiency is to minimize primary winding's RMS conduction losses.To meet this requirement, primary windings of coupled inductors were designed to have a low resistance of 12 mΩ.The turns ratio of 3.2 was dictated by two constraints.The first one is the required voltage gain (see Fig. 4), which ensures the output voltage of 380 V and the range of duty ratio of 0.3 to 0.6 to cover the whole input voltage range.The second constraint is to ensure proper work in the soft switching region (see Fig. 5).

C. Resonant Circuit
To minimize the RMS currents in the converter components, the resonant frequency should be as low as possible but higher than 1/(t 7 -t 4 ), which is reciprocal of the transistor turn-OFF time.Based on Fig. 5 and considering the converter's parameters, frequency f s /f r1 = 0.7 was selected.Resonant impedance affects the maximum voltage stress of the transistor but, on the other hand, decreases the range of the output power where the transistor is soft-switched while turning OFF.The assumption was made to achieve full soft switching of the transistor for 50% of the output power and beyond, which corresponds to the resonant impedance Z 1 equal to 27.7 Ω.The parameters of the resonant circuit were calculated based on the selected resonant frequency and resonant impedance.The leakage inductance was 1.48 μH, and the capacitance of the resonant tank was 19.8 nF.In the proposed circuit, a relatively high coupling coefficient allowed for the utilization of the leakage inductance, whereas in the conventional circuits, another magnetic component would need to be used, increasing the overall component count of the converter.

D. Capacitors
The capacitance of the capacitors C c and C should be as low as possible; on the other hand, low capacitance has an impact on the voltage ripples, especially regarding the output capacitor C. Assuming constant output current I o during one switching cycle, and based on the analysis of the capacitor C C current when the transistor is turned-OFF, voltage ripples on capacitor C C can be described as follows: To calculate the voltage ripples on capacitor C, considering interval t 0 -t 6 , and assuming the square shape of the input current in interval t 4 -t 6 where t 6 -t 4 = T S /G V .According to (41) and (42), the maximum voltage ripple on capacitor C C for data presented in Table I is around 1.8 V, whereas the maximum voltage ripple on capacitor C is around 2.6 V.

E. Experimental Results
The experimental waveforms of the proposed converter were captured to confirm the theoretical considerations.The experimental tests were carried out from 75 W to 300 W of the output power for three different input voltages of 30 V, 40 V, and 50 V at constant V out = 380 V.The converter operates outside the soft-switching region (f s /f r1 = 0.7 curves in Fig. 5) for the output power of around 160 W and below.For higher power (i.e., 200 W and 300 W), the transistor is turned-OFF at zero voltage; thus, the operating point of the converter is located within the soft-switching region.According to the theoretical assumptions, transistor S is turned on at zero current and turned-OFF at zero voltage.At the rated power (300 W), the peak transistor steady-state voltage was around 120 V. Fig. 8 shows the waveforms of the converter working under V in = 40 V and three different output power P out = 100 W, 200 W, and 300 W. The waveforms for P out = 200 W and P out = 300 W show transistor soft-switching operation when the transistor S is soft-switched at zero-voltage.Waveforms shown in Fig. 8(a)-(c) in show diode D transient waveforms in its soft-switching mode of operation.In the steady state, while the diode is reverse-biased, the maximum reverse voltage approaches the output voltage.Fig. 9 presents the calculated power loss distribution at full load conditions.In the proposed converter, conduction losses caused by RMS currents are dominant power losses.The power loss breakdown outlines that at the rated output power, around 43% of power is dissipated within the coupled inductors.It can be noted that the remaining 57% of losses are more equally distributed between all switching components (11% to 16%).With this approach, total power losses reach 6.33 W at full load.Power losses in converter components presented in Fig. 9 were calculated based on the (34)-(40), and using I x(RMS) 2 R x relation for the transistors and the inductors; and I x(RMS) 2 R x + I x(AV) V x(F) for the diodes.The parameters of the components are as follows: transistor on-resistance R DS(on) = 9.1 mΩ, coupled inductor primary winding resistance R PW = 12 mΩ, secondary winding resistance R SW = 100 mΩ, diode D c1 series resistance R Dc1 = 40 mΩ forward voltage V F(Dc1) = 0.6 V and diode D c2 and D series resistance R Dc2,D = 128 mΩ and forward voltage V F(Dc2, D) = 0.9 V.For the power semiconductors, the data have been collected on the basis on the datasheets for the temperature of 75 °C.Losses in the core of the coupled inductor were calculated using Oliver's formula, the calculated ripples in the magnetizing inductance are ΔI Lm = 3.8 A, and the core data from the datasheet.

VIII. PERFORMANCE COMPARISON
Table II contains the comparison of the proposed converter with six other topologies with coupled inductors.Converters described in [15] and [16] have the same topology as the converter presented in this article, however, in [15] and [16] the capacitance of the clamps capacitors is much higher than in the proposed converter.Thus, it causes a low voltage ripple on capacitor C r ; the transistor turn-OFF voltage is higher than V in /(1 -D), and a transistor is hard turned-OFF.On the other hand, in the proposed converter, the resonant capacitor is completely discharged at the soft-switching region (see Fig. 5), which allows the transistor to be turned-OFF at zero voltage.Resonant operation increases the maximum voltage on capacitor C r which also increases the maximum voltage on the transistor.However, the voltage increase is slight, and the proposed converter is free of transistor voltage spikes during turning OFF.In other converters described in the literature [5], [8], [15], the voltage ripples across the clamp capacitor are low, and the transistor is hard turning OFF and thus exhibits substantial voltage overshoots.In the proposed converter, switching losses are decreased due to the reduction of transistor turn-OFF voltage.The overall percentage of transistor power loss (16%) is significantly smaller Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.  in the presented converter (see Fig. 9) than in the hard-switched converter in [16], where it is 28%.The converter described in [15], unlike [16], includes an efficiency-oriented design, which is why that reference is listed in Table II.Besides, the converter in [15] achieved high efficiency at wide input voltage and output power, even compared to its newer counterparts.This is due to using a coupled inductor with high volume on the EE-55 core, which allows for reduced losses in the core and inductor wire.Furthermore, the high volume of the inductor made it possible to obtain a high turns ratio and, as a consequence, to reduce the duty ratio and maximum voltage of the transistor, as well as improve the efficiency.Additionally, the capacitance values were much higher.Fig. 10 presents the results of efficiency measurement at the output voltage of 380 V and three different values of the input voltage: 30 V, 40 V, and 50 V.Efficiency was measured for the  proposed clamp circuit and a basic clamp [15] using the same converter and adding 4.7 μF film capacitor in parallel to C r .The comparison was made to verify the efficiency improvement by using the proposed resonant clamp technique.The switching frequency is the same for both cases (f s = 200 kHz).For the proposed resonant clamp circuit, the peak efficiency ƞ = 96.9% was reported at the output power of around 125 W and the input voltage V in = 50 V.The lowest efficiency was 94.7% at the output power of 265 W and input voltage V in = 30 V. When the efficiency between the proposed and conventional clamp circuits is compared; it can be seen that the efficiency of the proposed clamp circuit is much higher.E.g. for 40 V and maximum output power, the measured efficiency of the converter with resonant clamp is 96.4%, whereas for the basic clamp, it is just 94.1%.This is mostly caused by better turn-OFF transistor conditions, thanks to using the resonant operation of clamp capacitor C r .Only for input voltage V in = 30 V and power lower than 200 W the efficiency of the converter with a basic clamp is slightly higher than the case with the proposed resonant clamp circuit.The difference does not exceed 0.5 p.p.
The converter described in [5] consists of a similar structure with a passive clamp circuit to the one presented in the paper and exhibits the same component count.However, the components of the converter are connected differently, which reduces its voltage gain to (n + 1)/(1−D) instead of (n + 2)/(1−D) as in the case of the proposed converter.In the converter from [5], capacitor C r forms the resonant circuit with the leakage inductance.That allows for a quasi-sinusoidal shape of the transistor current and windings of the coupled inductor, which reduces transistor and inductor current stresses and transistor turning-OFF current.However, in [5], unlike in the proposed solution, the resonant operation has little effect on the clamp capacitor voltage ripple.Therefore, the transistor is hard to turn-OFF, which significantly increases converter switching losses compared to the proposed resonant passive clamp circuit.The converter in [5] achieved higher efficiency compared to the presented solution primarily because of two reasons.First, in [5], the converter is controlled with a much lower frequency of 90 kHz compared to 200 kHz in the presented prototype, which reduces switching losses, especially transistor turning-OFF losses, and also minimizes the losses in the inductor core.Second, in [5], a more expensive transistor (IRFP4668PBF with V DSS = 200) was used than in the presented solution (AOT2500L with V DSS = 150), which enables the use of a transistor with higher V DSS voltage at similar R DS(on) .Therefore, a coupled inductor with a much lower turn ratio of 1.72 could have been used in [5], despite the fact that output and input voltages are very similar for both cases.A lower turn ratio of the coupled inductor results in lower resistance of the inductor wire, lower root-mean-square current in the converter components, and the possibility of using a smaller core.Yet, as was mentioned, it comes at the cost of higher transistor voltage.
Overall, despite switching the transistor with a much higher frequency and using a worse transistor in the proposed solution, the difference in efficiency is minor.This is due to employing the proposed novel resonant clamp technique with a completely discharged clamp capacitor, eliminating the turning-OFF losses.The maximum output power of the converter in [5] is 400 W and is higher by 100 W compared to the prototype presented in this article.For 300 W operation, the efficiency of the converter in [5] is higher by 0.5% for the established maximum input voltages.Additionally, using a higher switching frequency enables the use of smaller passive components and improves the power density of the converter.The dimension base of the proposed converter is 54 mm × 75 mm, whereas for the converter in [5], it is 110 mm × 107 mm, which is a substantial improvement.
The converter described in [8] achieved a high efficiency of 96.4% at nominal output power.However, the circuit consists of two additional multiplier cells with two additional capacitors and two additional diodes; this is why the circuit is characterized by a higher voltage gain.However, voltage gain is only slightly higher, despite the fact that two additional voltage multiplier cells are used, which makes the converter less competitive to the proposed circuit.Furthermore, the efficiency of the converter is high.However, it is caused by using a transistor with a very high current rating of 300 A (very low R DS(on) ) with a low output Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
power of 200 W, as well as two times lower switching frequency than in the presented converter (equal to 100 kHz).
In [21], an interleaved converter with an active clamp along with a voltage multiplier cell is presented.Thanks to using an interleaved structure, high output power 768 W was achieved, despite using an active clamp with an additional clamping transistor.The obtained efficiency at nominal output power is not higher than in the converter with the passive clamp.This is due to the fact that in all converters with coupled inductors, thanks to the leakage inductance, the transistor is turning ON at zero current.Thus, using a zero-voltage technique reduces the switching losses slightly.A main advantage of such a structure is the low input current ripple, which is an advantage of all interleaved converters.
The converter presented in [22] consists of an additional inductor at the input to reduce the input current ripples.Besides, a two-winding coupled inductor, two voltage multiplier cells, and an active clamp are used in the circuit.Moreover, a resonant technique to reduce switching losses is employed.Such a circuit is highly complicated and consists of many components; however, the voltage gain is high.The converter achieved a maximum efficiency of 93.8% at nominal output power P o = 250 W despite low switching frequency.
In [29], a converter with a three-winding coupled inductor, voltage multiplier cells, and an additional input inductor, is presented.Using a three-winding coupled inductor increases the voltage gain; however, the circuit requires an additional voltage multiplier cell for proper operation, which increases the component count.The converter at the nominal output power of 200 W and voltage gain of around 10.5 achieved a lower converter efficiency of 95.5% than the proposed converter, despite that the switching frequency was four times lower and equal to 50 kHz.
The converter presented in this article and those in [5], [8], and [15] are characterized by high input current ripple.Input current ripple can be lowered by using an interleaving structure [21] or an additional input inductor [22], [29].In both methods, the component count is increased, and the converter becomes more complex and with reduced efficiency.In the presented converter and in [5], [8], and [15], the input current ripple can be reduced by using an additional LC filter at the input.The volume of such an input filter depends on the power, input current ripple, and switching frequency.In such a type of structure, the input current ripple can be lowered by using a coupled inductor with a lower turn ratio.To achieve high voltage gain with a low turn ratio, more voltage multiplier cell structures must be used, like in [8], which again increases the component count.
The presented converter and the converters described in [5] and [15] are characterized by the same component count.Furthermore, the clamp circuit in [5] is also resonant, akin to the proposed solution.That is why a more accurate, general comparison of the presented converter with the proposed resonant passive clamp against a clamp in converter [5] and [15] is carried out.
Fig. 11 shows a comparison of the input current and clamp capacitor voltage transient shape in the proposed converter with the converters described in [5] and [15].Comparison is made assuming that the transistor duty ratio, output, and magnetizing Fig. 11.Comparison of the input current and voltage across the clamp capacitor for the proposed converter and converters in [5] and [15].currents are the same and converters operate in CCM.Following the waveforms in Fig. 11, input current ripples were determined in the three compared converters, assuming equal input and output conditions and equal resonant frequency for the proposed converter and the converter shown in [5].To determine the input current ripple, it can be assumed that Area 1 and Area 2 in Fig. 11 are equal, and (Area 1 + Area 2)/T S = (Area 1 + Area 3)/T S = nI o .The input current ripple in each considered converter is substantial due to the use of a coupled inductor.The input current ripple in the converter with the proposed resonant clamp circuit can be described as The input current ripple in [15] can be described as The input current ripple of the converter in [5] can be described as An input filter is a necessity to apply the proposed converter for renewable energy applications since the current ripples are notable.Still, as can be seen in Fig. 12, the input current ripple of the converter with the basic clamp circuit [15] is higher than in the proposed converter and the converter described in [5].It is due to a quasi-resonant shape of input current during turning ON the transistor in both solutions.Ripples of the proposed converter and the converter described in [5] are similar, but still somewhat lower in the proposed solution for the nominal conditions.Overall, using the resonant passive clamp circuit reduces the input current ripples, which makes it possible to use an input current filter of lower volume, and renders this solution superior to its counterparts.Furthermore, when the capacitors and their voltage ripples are considered, the proposed converter also shows advantages.In all the converters from the references, as well as in the proposed converter, the capacitors are charged and discharged alternately at the time when the transistor is either ON or OFF.Moreover, the mean currents of the capacitors during the turning-ON and/or turning-OFF of the transistor are proportional to the output current.Therefore, the voltage ripples on the capacitors are mainly bound to the switching frequency and the capacitance values.Since in the proposed converter, the operating frequency is higher; it is possible to achieve lower voltage ripples than in the converter with another clamp circuit [5], [15] operating with a lower frequency.Thus, it can be assumed that the capacitor voltage ripples are generally lower in the proposed converter.
As can be seen in Fig. 11, a significant part of the time when the transistor of the converter described in [5] is on, in opposite to the presented solution and the converter described in [15], the input current is equal to 0. Thus, the voltage gain of the converter in [5] is lower.A comparison of the voltage gain of the three analyzed converters is shown in Fig. 13.The impact of the resonant impedance and output resistance on the voltage gain formula in the proposed converter is minimal (see Fig. 4), and thus it has been omitted.To achieve the same voltage gain of the converter in [5] as in the presented converter, the transistor must be controlled with a higher duty ratio.Simultaneously, the maximum voltage across the transistor in [5] during turning OFF, omitting the overshoots, is equal to V in /(1 -D); higher voltage gain increases the maximum voltage on the transistor.On the other hand, in the presented converter, the maximum voltage across the transistor is increased due to the resonance after turning OFF the transistor (see Fig. 2, t 5 -t 6 ).However, that voltage increase is not significant, and since the transistor is turned OFF at zero voltage, there is no additional voltage via overshoots.In contrast, in [5] and [15], transistors are hard to turn-OFF, which in reality leads to increases in maximum voltage Fig. 13.Comparison of voltage gain of the proposed converter and the converters in [5] and [15].For the proposed converter, the turn-OFF voltage remains 0 V at the range below around 50% of the rated output power.For higher output power, it is more than two times lower compared to the other compared converters.Therefore, a passive clamp helps to alleviate the turn-OFF voltage stress of the transistor, which also affects the turn-OFF switching power losses.Please note, that in the case of the converter in [5], it was assumed that the transistor turning-OFF voltage of the converter with the resonant clamp circuit presented in [5] is equal to V in /(1-D), as even though V DS(off) is equal to the clamp capacitor voltage during the turning OFF of the transistor, and the clamp Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
capacitor resonates with the leakage inductance, which increases V DS (OFF) voltage.However, the resonant impedance of that resonant circuit, due to high capacitance, is very low compared to the presented converter.Thus, the voltage ripple across the clamp is low, and its impact on V DS( OFF ) may be omitted.
According to Figs. 11 and 14, the turn-OFF current and voltage in [15], and turn-OFF voltage in [5], are much higher than in the proposed solution, which affects the power losses in a great manner, especially for high-frequency operation.Thus, in that regard, the proposed converter seems to be the superior solution.
In summary, utilizing the resonant operation while turning ON the transistor has no negative impact on its conduction losses.Moreover, RMS currents in the components remain low.All diodes are turned-OFF at zero current.Transistor turn-OFF voltage is zero in the soft switching region and much lower than in [15] and [16] in the hard switching region (see Fig. 5).The proposed converter achieved similar efficiency and voltage gain to the converter described in [5], however, in the presented converter with resonant passive clamp, the resonant frequency is 200 kHz versus 90 kHz [5].As a consequence, the dimensions of the proposed converter are much lower.Similar parameters were also achieved for the converter presented in [8].However, its maximum output power is lower (200 W), and an additional voltage multiplier cell and a transistor with very high current ratings are used.
Compared to all its counterparts, the proposed converter is distinguished by the following.
1) Reduced transistor switching losses, possibility to operate with the higher switching frequency thanks to transistor turning OFF at zero voltage and turning ON at zero current.2) Leakage inductance is incorporated into the resonant tank.3) Merely equal power loss distribution across the active components predestines the proposed converter to apply in high power density designs.4) Improved efficiency compared to conventional clamping circuit.5) Full soft switching of all converter switches.

IX. CONCLUSION
This article presents and discusses a novel approach to utilize the resonant features of the passive clamp circuit in a PWM boost converter with a coupled inductor and switched capacitor.The new resonant clamp circuit enables zero-voltage turn-OFF of the transistor and improves efficiency compared to known clamp circuits described in the literature.Detailed mathematical analysis and the characterization of operation principles of the proposed converter with an appropriate selection of the converter components are presented in the article.
Mathematic analysis was verified on the 300-W laboratory model of the converter, achieving a high efficiency of 96.9% with 200 kHz of switching frequency and even power loss distribution across the active components.
In conclusion, the proposed high-power density and highefficiency soft-switching topology of the dc-dc converter allows efficient utilization of the power components, is robust to the output power variation, and is a worthy competitor to other stateof-the-art converters.

Fig. 1 .
Fig. 1. High step-up DC-DC converter-a schematic of the topology.

Fig. 6 .
Fig. 6.Curves of the conduction mode of the proposed converter in function of the duty cycle.

Fig. 9 .
Fig. 9. Power losses in the converter's components at P o = 300 W and V in = 40 V.

Fig. 10 .
Fig. 10.Efficiency of the converter with basic clamp and proposed resonant clamp circuits.