Three-Phase ARCP Inverter Using Soft-Switching With a Single Shared Inductor

Soft-switching in power inverters for drive and grid applications can both enhance the efficiency by reducing switching losses and improve electromagnetic interference (EMI) due to lower switching speeds with their associated <inline-formula><tex-math notation="LaTeX">$\mathrm{d}v/\mathrm{d}t$</tex-math></inline-formula>. An advantageous topology is the well-known auxiliary resonant commutated pole (ARCP) inverter. The development of such power electronic inverters often focuses on reducing weight, volume, and cost. Considering a three-phase ARCP system, this article presents a novel single shared inductor <inline-formula><tex-math notation="LaTeX">$(\mathrm{S}^{2}\mathrm{I})$</tex-math></inline-formula>-ARCP approach to reduce the passive component count in the auxiliary circuit from three to one. The simultaneous use of the shared inductor by more than one phase must be detected and avoided by the control algorithm. A frequency analysis of such occurrences is performed, and a method for avoiding them by shifting the switching edges is presented. The proposed <inline-formula><tex-math notation="LaTeX">$\mathrm{S}^{2}\mathrm{I}$</tex-math></inline-formula>-ARCP topology together with an appropriate control algorithm is implemented and validated at 10 kW with an 800 V dc-link. Efficiency measurement results indicated a significant loss reduction under soft-switching operation by more than 38% compared with hard-switching, with a peak efficiency value of 99.58%. It is demonstrated that a mere adjustment in the control signal generation can save two resonant inductors without significant disadvantages.

Three-Phase ARCP Inverter Using Soft-Switching With a Single Shared Inductor Thomas Lehmeier , Adrian Amler , Yan Zhou , and Martin März Abstract-Soft-switching in power inverters for drive and grid applications can both enhance the efficiency by reducing switching losses and improve electromagnetic interference (EMI) due to lower switching speeds with their associated dv/dt.An advantageous topology is the well-known auxiliary resonant commutated pole (ARCP) inverter.The development of such power electronic inverters often focuses on reducing weight, volume, and cost.Considering a three-phase ARCP system, this article presents a novel single shared inductor (S 2 I)-ARCP approach to reduce the passive component count in the auxiliary circuit from three to one.The simultaneous use of the shared inductor by more than one phase must be detected and avoided by the control algorithm.A frequency analysis of such occurrences is performed, and a method for avoiding them by shifting the switching edges is presented.The proposed S 2 I-ARCP topology together with an appropriate control algorithm is implemented and validated at 10 kW with an 800 V dc-link.Efficiency measurement results indicated a significant loss reduction under soft-switching operation by more than 38% compared with hard-switching, with a peak efficiency value of 99.58%.It is demonstrated that a mere adjustment in the control signal generation can save two resonant inductors without significant disadvantages.

ARCP Related Parameters
I boost [A] Commutation current at the start of the transition.I ramp [A] Auxiliary inductor current at the start of the transition, (I ramp = I load + I boost ).I th [A] Threshold for auxiliary circuit activation.T act [s] Auxiliary circuit activation time.T com,acsc [s] Auxiliary circuit supported commutation duration.T com,csc [s] Capacitive self-commutation duration.T dead [s] Main switch dead-time.T lock [s] Auxiliary circuit reactivation lockout-time.T p [s] Pulse cycle, (T p = T sw /2).T ramp [s] Auxiliary current ramp-up/ramp-down time.T zvs [s] ZVS precision tolerance.P rel [%] Relative collision rate in relation to fundamental period.Q tot [As] Total charge stored in snubber capacitors.

I. INTRODUCTION
H IGHER efficiency, less heat to be removed, lower electro- magnetic interference (EMI), less noise emission, better controllability, simplified power module design, and smaller passive components are among the main goals when designing power electronic systems.On one hand, for drive or grid inverters in the medium to high kilowatt power range, a high switching frequency is beneficial for waveform quality, controllability, and the design of passive components.On the other hand, EMI requirements, the semiconductors, and the power module design limit the switching speed [1], [2].
In the 1990s, the constraints of the available power semiconductors, such as early insulated gate bipolar transistors (IGBTs) or gate turn-OFF-thyristors (GTO) were especially prevalent.To improve the efficiency and raise the switching frequency, topologies realizing soft-switching were developed [3], [4], [5], [6].Soft-switching reduces the dependency of the losses on the switching speed.This gives an additional degree of freedom to the system design.Realizing higher switching frequencies may increase the efficiency of electric motors [7], whereas active and passive circuit components can be utilized to their full potential [8].A limited voltage slew-rate reduces the stress on bearings and the isolation system of electric machines, as well as overvoltages at the machine terminals [8], [9].Moreover, EMI properties can be improved [10], [11].Although there are better power semiconductors available today, the issue is still prevalent as new, more demanding application areas emerge, such as solar-to-grid inverters or drive inverters for electric vehicles (EVs).These systems require high efficiency and an increased power density without exceeding the limits for EMI and dv/dt.Therefore, the full potential of available wide band-gap power semiconductors and even IGBTs cannot be utilized using the standard hard-switching two-level voltage source inverter (VSI) topology [12].So, it is appropriate to consider soft-switching concepts for the mentioned applications.
Methods for realizing soft-switching in two-level VSIs can be classified into three categories.First, there are the "load resonant" systems, as mentioned in [13].They employ only inherent components of the circuit, namely the load inductance and the parasitic switch capacitance, for realizing a soft transition.Only certain combinations of the switching direction and the load current can be loss-relieved.Thus, a high current ripple is necessary for continuous soft-switching, which is impractical for high-power and drive applications [6].Second, in systems with a "resonant link" or "quasiresonant link" an auxiliary circuit is added to the dc-link to reduce the link voltage at the bridge inverter temporarily, thus achieving zero-voltage switching (ZVS).Examples of this category are the resonant dc-link inverter [5] or the active clamped resonant dc-link inverter [4], [14].However, high switching overvoltages and oscillations are among the problems of topologies in this category [15].It is also necessary for the auxiliary circuit to conduct the load current continuously, thus causing significant additional losses [6].Systems with a "resonant transition" or "resonant snubber" belong to the third category.Suitable examples are the auxiliary resonant commutated pole (ARCP) [3], the zero-current transition inverter [7], or the zero-voltage transition inverter with its derivatives (e.g., coupled inductor, single switch, or single inductor) [8], [16], [17].These topologies are advantageous as the auxiliary circuit only conducts current while supporting a commutation process, and traditional modulation schemes, such as space vector modulation are generally applicable [6], [9].
For the mentioned reasons, the "resonant transition" concepts are preferable for modern drive or grid applications.In particular, the ARCP principle offers comparatively higher efficiency [17] and also avoids an excessive number of components or complex components, such as coupled magnetics [8].Research interest on ARCP has increased recently and different applications for dc/dc converters [18] and EV drives [9] and implementations considering semiconductor properties [19], EMI [20], topological modifications [5], [21], [22], [23], and control schemes [24] have been discussed.
However, the ARCP topology has the potential to further reduce the number of passive components, particularly the potentially bulky and heavy resonant inductors.This has not been adequately addressed in literature.As the current flows in the inductors only for a fraction of a switching cycle, the same inductor could be used for the different phases of a multiphase system.Gong et al. [23] proposed the use of two inductors for the two commutation directions in a three-phase system, thus sparing one inductor.The number of inductors can be further reduced if only a single shared inductor is used for a three-phase system, as proposed in this article.The topological reduction and its implementation, as suggested in the pending patent [25], is analyzed in detail in this article.The suggested topology versus the conventional topology is shown in Fig. 1.
The inverter consists of a VSI bridge-type inverter with its six main switches (three high-side switches S HS and three lowside switches S LS with their snubber capacitors C sn ) and three bidirectional auxiliary switches (S aux,p for the positive auxiliary current direction and S aux,n for the negative auxiliary current direction), all connected to the only auxiliary inductor L aux .As mentioned, it is advantageous for an inverter topology, especially in grid and drive system applications, to enable all common modulation schemes without limiting the modulation degree, the direction of the power flow or the phase angle.Therefore, without using an adapted modulation scheme, such as in [18] and [23], situations can arise in which more than one phase requires the simultaneous use of the shared auxiliary inductor.This article analyzes the probability of such "collisions."Possible collision avoidance methods are discussed, as a dc-link short due to an inadequate control of the main and auxiliary switches must be avoided.The functioning of the presented concepts is verified by the implemented single shared inductor (S 2 I)-ARCP inverter, realizing a power transfer of 10 kW from an 800 V dc-link.
The rest of this article is organized as follows.An introduction into drive inverters and into the considered topology is given in Section I. Section II contains a detailed analysis of the voltage and current waveforms during the auxiliary circuit supported switching.This is the base for analyzing the constraints and possible control methods of the S 2 I-ARCP topology in Section III.Section IV presents an experimental realization of the proposed circuit.The discussion in Section V looks into the measured results and insights into the implementation.Finally, Section VI concludes this article.

II. GENERAL CONSIDERATIONS FOR ARCP
The ARCP principle of operation, timing, and analytical description has for the most part already been dealt with in detail in the past literature, for example [3], [26], and [27].Therefore, only the basic and most important relationships are recalled while introducing the used operational strategy to allow a more in-depth understanding of the S 2 I-ARCP behavior and its collision rate results in Section III.

A. Operation Principle and Timing
This section describes the operation principle of the ARCP circuit and thus applies to both the conventional ARCP and the S 2 I-ARCP.For this purpose, a single-phase two-level ARCP circuit diagram is shown in Fig. 2. The depicted clamping diodes (illustrated in dashed lines) are optional and do not take part in the normal commutation process.They can be introduced as a precautionary measure, limiting the voltage in case of a mistimed S aux -switch-OFF with a current-carrying L aux [20] or in case of excessive parasitic oscillations between L aux and the output capacitance of the auxiliary switches [28].
For a better system performance, a load dependent "variable timing" control for the auxiliary circuit is used, similar to [24], [22], [29], and [30].Depending on the load current level and direction, the operation of the ARCP can generally be divided into two different operational modes with three different cases.Fig. 3 shows the different cases for both commutation directions.The upper half plane corresponds to rising edge transitions with commutations from LS-switch to HS-switch, whereas the lower half plane corresponds to falling edge transitions with commutations from HS-switch to LS-switch.
Assuming a commutation direction from LS to HS, case (Ia) is applied at positive load currents with the support of the auxiliary circuit, in the following referred to auxiliary circuit supported commutation (ACSC).Negative currents at light load conditions also demand ACSC for an accelerated commutation and are described by case (Ib).Commutation case (II) is used for high negative load currents when switching from LS to HS.In this case, the auxiliary circuit is not needed and the snubber capacitors self-commutate automatically with the given load current, referred to capacitive self-commutation (CSC).The boundary between ACSC and CSC is reached at the threshold current level I th .The threshold current represents an additional control parameter and leads to an increase in the control complexity compared with pure ACSC operation [30].But the losses in the disabled auxiliary circuit are reduced significantly with the combination of ACSC and CSC operation, which is therefore also applied in this work.Case (Ia) must be swapped with case (Ib)+(II) for the inverse commutation direction.ACSC is now necessary for a high negative I load , while CSC is applicable for a high positive I load .The implementation of the control Fig. 4. Timing diagram with switching signals, current and voltage waveforms, and voltage slew-rate for the three different cases during rising edge transitions (corresponds to a commutation from LS-switch to HS-switch).Note that the scaling of the x-axis and the y-axis is valid for all cases.I load(II) is not displayed.The current and voltage waveforms for a HS → LS commutation would each be mirrored vertically.strategy used and the choice of control parameters will be discussed in more detail in a later section.
To simplify the following analysis of the commutation process, several common assumptions and simplifications are made.
1) The split dc-link capacitor is perfectly balanced and its midpoint 0 is used as reference potential.
2) The power semiconductors are assumed ideal (in particular voltage independence of C sn , no forward voltage drop, infinitely short switching times) as well as the passive components.
3) The load current is constant in time i load = I load during the short commutation process, thus neglecting the current ripple under the consideration of a high load inductance.Fig. 4 shows the three discussed commutation cases in a timing diagram with all relevant switching signals as well as voltage and current waveforms, including the voltage slew-rate dv/dt.The stages of ACSC operation for case (Ia) and case (Ib) can be described as follows.
1) Initial state {t < t 0 }: T LS is turned-ON and I load is flowing through T LS in the reverse direction.2) At t 0 : T aux,p is turned-ON under zero-current switching (ZCS) condition.3) Pre-charging stage {t 0 < t < t 1 }: As v aux is equal to V dc /2, i aux ramps up linearly to the level of I load , while the current through T LS simultaneously decreases to zero.4) Boosting stage {t 1 < t < t 2 }: i aux continues to ramp up linearly to accumulate more energy for boosting the following commutation process; the current direction through T LS reverses and increases in the forward direction.5) At t 2 : T LS is turned-OFF at i aux = I ramp and i LS = i ΣC,sn = I boost , causing the controlled triggering of the resonant transition.6) Resonant commutation stage {t 2 < t < t 4 }: L aux resonates with C sn of both switches; the voltage across the HS-switch swings down to zero in a slow, smooth, and sinusoidal manner until the conduction condition of the antiparallel diode is reached while the voltage across the LS-switch swings up to V dc ; the dv/dt curve clarifies the "S-shape" of the voltage transition; the maximum dv/dt occurs at t 3 ; the vertical jumps at t 2 and t 4 are smoothed in practice due to the nonlinear output capacitance of the switches and the finite switching speed.7) Clamping stage {t 4 < t < t 5 }: D HS starts to conduct at t 4 and clamps the voltage across the HS-switch; as v aux is now equal to −V dc /2, i aux ramps down linearly to the level of I load while the current through D HS simultaneously decreases; during this stage T HS is turned-ON under ZVS condition and takes over the current from D HS in the reverse direction.8) Discharging stage {t 5 < t < t 6 }: The current direction through T HS reverses at t 5 and increases in the forward direction while i aux continues to ramp down to zero.9) Final state {t > t 6 }: T HS takes over the full load current at t 6 while i aux drops to zero and S aux,p can be turned-OFF Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE I OVERVIEW OF THE IMPORTANT ARCP VALUES FOR EACH CASE
under ZCS condition (whereby the exact turn-OFF time after time instant t 6 is not that relevant).Note that the precharging and discharging stages are not present in case (Ib).The effective subcircuits for each stage presented in [3] may be of interest to readers seeking further explanation.Regarding the operational strategy, if the load current falls below zero, described by case (Ib) in Fig. 3, I ramp continues to decrease linearly until a minimum ramp duration T ramp,min is reached.T ramp,min is introduced to ensure a clean switching transition and a clear distinction between ACSC and CSC operation.Thus, the turn-ON of the auxiliary switch at t 0 should always precede the turn-OFF of the main switch at t 2 .From this point on, I boost linearly increases automatically to compensate for the rise of I load in the negative direction, since T ramp cannot be further reduced.
Case (II) under CSC is shown on the right-hand side of Fig. 4.During a capacitive commutation, the voltages transition linearly since only the C sn of both main switches are involved in the commutation process and these are charged and discharged by a constant I load .Therefore, the dv/dt is constant and generally unequal to cases (Ia) and (Ib).
The area below the i ΣC,sn curve between t 2 and t 4 corresponds to the total charge Q tot stored in the snubber capacitors C sn , which must be charged and discharged at each commutation.C sn comprises the parallel connection of the switch output capacitance, parasitic structure-related capacitances, and, if needed, another discretely connected capacitor.It can be estimated as follows: The area below the dv/dt curve is proportional to Q tot and is equal to the value of the voltage transition ΔV = V dc , which is identical in all three cases.Therefore, short commutation times results inherently in a high dv/dt.For further analysis, the characteristic ARCP values for each case are given in Table I.

B. Analytical Description
The following analytical expressions are valid for both polarities of I load and for both commutation directions.The equivalent circuits during the resonant stage under ACSC and during CSC with the given initial conditions, according to Table I, are shown in Fig. 5.

1) ACSC Operation:
The LC resonant circuit under ACSC operation is driven by V dc /2 and influenced by I load , wherein both C sn act in parallel.The circuit can be represented in a second order differential equation without attenuation.The solution for the inductor current during the resonant stage t 2 ≤ t < t 4 as well as the ramp stages t 0 ≤ t < t 2 and t 4 ≤ t ≤ t 6 can be expressed as follows: with whereby i ΣC,sn is the total current charging and discharging the snubber capacitors.During the linear ramp-up interval t 0 ≤ t < t 2 and ramp-down interval t 4 ≤ t < t 6 , i aux rises with a slope of di aux /dt = V dc /2L aux and falls with di aux /dt = −V dc /2L aux .Z r and ω r are the characteristic impedance and the angular frequency of the resonant circuit, respectively.They solely depend on the components L aux and C sn involved in the resonance In the precharging and boosting stage i aux ramps up to I ramp during the auxiliary current ramp interval The current through the auxiliary inductor at t 4 in Fig. 4 and thus at the end of commutation is equal to the start value of the resonance at t 2 .Solving (2) for i ΣC,sn (t = t 2 ) = i ΣC,sn (t = t 4 ) yields the resonant commutation duration T com,acsc .With help of tan (x/2) = (1 − cos x)/ sin x follows: Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
The resulting total activation time of the auxiliary switch and hence the auxiliary circuit can be given by (6) with its maximum value T act,max at I load,max .
The clamping phase is the time range in which the main switch can turn-ON under ZVS condition.This time range corresponds to the switching precision tolerance duration for ZVS operation, which is denoted as T zvs and is given for both ACSC cases in the following: For a practical selection of T zvs , it is essential to consider the switching times of the power semiconductor switches, the clock cycle of the microcontroller, and the expected current ripple to enable complete ZVS at every switching instant.Further considerations regarding the parameter selection are discussed in the later Section IV-B.Case (Ia) results in the tallest and widest i aux pulses during the fundamental period.Its amplitude I aux,max occurs in Fig. 4 at t 3 and can be calculated with (2) by I aux,max is relevant for short-term maximum component current stress and, if necessary, for designing an appropriate magnetic circuit.The shape of the voltage during the resonant commutation stage (t 2 ≤ t < t 4 ) can be derived through differentiating i aux by time.This again leads to a sinusoidal expression for the voltage across L aux and hence for all voltages, e.g.v LS (t), involved in the commutation cell The resulting slew-rate of all voltages can be obtained by differentiating once again (11) The maximum dv/dt occurs at t = t 3 = t 2 + T com,acsc /2, which marks I aux,max and the intersection of the voltages 2) CSC Operation: As already discussed in the previous section, the auxiliary circuit can be disabled for transitions with certain load conditions.CSC operation should only be used when |I load | > |I th | to keep the commutation duration within acceptable limits.Using Fig. 5(b), the commutation duration can be derived as follows: However, the dv/dt is no longer controllable under CSC and differs from ACSC, since T com,csc depends on the load current level during commutation.Therefore, the dv/dt is greatest at the load current peak.

III. DISTINCTION BETWEEN S 2 I-ARCP AND CONVENTIONAL ARCP
While the considerations of the previous chapter are generally applicable for all single and multiphase ARCP systems, the implications of sharing the same resonant inductor in a multiphase S 2 I-ARCP topology must be discussed further.In principle, an S 2 I-ARCP inverter behaves similarly to the conventional ARCP with multiple inductors.The voltage and current waveforms are identical during the resonant transition.However, special attention must be paid to the component stress, power losses, and the control algorithm.
The voltage across the auxiliary switches can be V dc at maximum during commutation of another phase in the case of S 2 I-ARCP, whereas the maximum component stress is ideally only V dc /2 for conventional ARCP.For this reason, the blocking voltage of the auxiliary switches can be chosen lower in conventional ARCP compared with S 2 I-ARCP.However, a new issue then arises because oscillations between L aux and the parasitic capacitances of the auxiliary switches can reach amplitudes of V dc , which are higher than the blocking voltage of the switches.To avoid damage, measures such as saturable cores to damp the oscillations [31] or clamping diodes [28] are required.Therefore, not being able to reduce the blocking voltage of the auxiliary switches is no major disadvantage for S 2 I-ARCP.
Regarding the losses in the auxiliary switches for the S 2 I-ARCP topology, the conduction losses are the same compared with the conventional ARCP, assuming the same switching devices are used.However, higher switching losses are to be expected during ZCS turn-ON since the effective parasitic output capacitance of the auxiliary switches connected in parallel is considerably higher.On the other hand, the rms current in the single inductor of the proposed topology is only √ 3 higher than the rms current of one resonant inductor in conventional ARCP.Therefore, when using the same inductor, the total losses for the three phases are identical, but two inductors are saved.When using the same amount of material for the auxiliary inductor(s) in conventional ARCP and S 2 I-ARCP, for the latter, the total inductor losses are lower.
To control the S 2 I-ARCP soft-switching inverter, the switching signals for the main switches can be generated utilizing common pulsewidth modulation (PWM) methods, such Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 6.Single collision between phase R and S. Note that t R3 , t S3 , and t T3 correspond to time instant t 3 in Fig. 4.
To avoid additional conduction losses in the auxiliary circuit and to reduce the current stress of the semiconductor devices, a variable timing control scheme for the auxiliary circuit, as already assumed in Fig. 3, can be implemented [24], [27].For this case, I ramp as well as T ramp and hence, I aux,max as well as T act are variable in time and are determined by the instantaneous value of i load (t) in each output phase.I boost and thus also T com,acsc is kept fixed to generate identical voltage transitions throughout the whole fundamental cycle T el .The control of I boost , together with the predetermined values of C sn and L aux , determines the voltage waveform calculated by (10) and its corresponding frequency spectrum during the commutation process [20].In addition, the maximum dv/dt is actively controlled with (12) under the usage of ACSC and can be set to a predefined value throughout T el .Since variable timing control depends on I load , additional calculations are required in the microcontroller compared with fixed timing control.Still, variable timing control is preferred for the aforementioned reasons.
The control of the S 2 I-ARCP topology is more complicated compared with the well-known conventional ARCP topology.This is because the three phases can interfere in a collision with each other when activating the auxiliary circuit.It must always be ensured that only one phase occupies the auxiliary circuit at a certain time stamp, otherwise a short circuit between at least two phases can occur.Fig. 6 shows a sample case for a single collision between the close adjacent edges of phases R and S.
The asterisks mark the edges where the use of ACSC is desired.Both rising edges of v R0 and v S0 are so close together in time, that the activation intervals of both phases overlap in time and cause a collision.The rare case of an activation interval overlap of all three phases is henceforth called a double collision.

A. Collision Rate Analysis
The issue of collisions is very crucial in S 2 I-ARCP.Its consequences for the control and practical implementation must be further analyzed in depth.To gain a more profound understanding of the collision mechanism and dependencies, a series of different calculations are performed at different operating points.For this purpose, the relative collision rate P rel is defined, which indicates the fraction of switching cycles requiring collision avoidance within a fundamental period.The analysis is based on sinusoidal modulation with a ratio of switching frequency to fundamental frequency f sw /f el = 600.The dependencies are shown in Fig. 7.
The ARCP design parameters L aux and C sn are varied in Fig. 7(a).As can be seen, P rel rises with ascending values for L aux and C sn .This can be explained with ( 4)- (6).Larger parameter values lead to longer time durations and thus increase the probability that the activation intervals of different phases overlap.Note, that the arctan characteristic of the T com,acsc calculation is recognizable in the plotted curves.Fig. 7(b) describes the dependency of P rel when varying phase angle ϕ load and modulation index m a .Most collisions occur in the case of resistive loads and least for inductive or capacitive loads.The most significant change in behavior occurs at around ϕ load = ±45 • .As will be shown later in Fig. 8, collisions do not occur randomly, but at certain times during the fundamental period.The reason for the mentioned transition is that the current of one phase involved in the collision changes its polarity and no longer requires ACSC operation.It can also be observed that P rel increases hyperbolically with descending values of m a .A low modulation index results in small duty cycles with edges very close to each other and hence in high collision rates.The dependence of I load and I boost on the collision rate is examined in Fig. 7(c).The results can be explained with ( 4)-(6) as well.The higher I load , the longer the ramp phases last and the more collisions will occur.Increasing boost currents lead to a longer T ramp but decreases the commutation duration.The arctan characteristic of the T com,acsc calculation is again recognizable in the plotted curves.In the case of I load = I boost = 0, the ramp duration becomes zero and T act is given by (14) which is unequal to zero.Therefore, collisions can still occur at a low rate.Last to note, the steps in the P rel curves result from the finite ratio between f sw and f el combined with a synchronous pulse pattern.The location of collisions in the space vector diagram is examined in the next step, which is shown in Fig. 8 for two different load conditions.Fig. 8(a)-(c) represent low load conditions with ascending phase angles.Once again, the strong dependence of the collision rate on ϕ load can be observed.Collisions (displayed in red) occur primarily in a rotationally symmetric arrangement at the sector transitions of the space vector diagram (multiples of 60 • ).This can be explained in the time domain, where the output voltages of two phases intersect at the sector transitions.The duty cycles of both phases are identical at this point and lead to a similar situation, as shown in Fig. 6.The collision region around the sector transitions becomes smaller as the phase angle  increases, with collisions now occurring predominantly at a small modulation index [compare also with Fig. 7(b)].
Fig. 8(d)-(f) show the results for high load currents.The collision area around the sector transitions expands noticeably with resistive loads.However, for ϕ load = 45 • , fewer or no collisions can be observed at higher modulation degrees.It is further observed that very small m a with very close edges always lead to collisions regardless of the load.

B. Collision Avoidance Method
To prevent a short circuit between two phases or even three phases, a method for handling the aforementioned collisions Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.needs to be implemented.Conceivable methods are described in [25].This includes shifting the switching edges of the phases involved in the collision to ensure sequential access to the auxiliary circuit.Fig. 9 shows the procedure.In Fig. 9(a), the rising edge of phase R is shifted to the left by at least the overlap time of both auxiliary circuit activations.To keep the required duty cycle constant, the falling edge is also corrected by the same shift to the left.The distortion caused by the small, uniform displacement of both edges can be neglected in practical operation.Other exemplary cases of a single and double collision are shown in Fig. 9(b) and (c).In rare cases, e.g., due to compliance with the minimum pulse duration, the shifting of a switching edge is not possible or would cause a deviation of the duty cycle.Then, the minor deviation of the duty cycle could be disregarded, hard-switching could be performed on this edge, or colliding space vectors, as shown in Fig. 8, could be avoided.

IV. PRACTICAL REALIZATION OF THE PROPOSED TOPOLOGY
A three-phase 10 kW S 2 I-ARCP inverter prototype was built to verify the proposed topological reduction to a single shared auxiliary inductor.The prototype and the experimental setup with the stages of pulse generation are shown in Fig. 10.
It consists of a control board with a microcontroller and a dclink voltage measurement, of three-phase current sensors, and of the main circuit board with the auxiliary circuit and a resonant inductor designed as an air coil on the top and the B6-topology with its main switches on the bottom.The auxiliary circuit can be disconnected for a fair comparison with hard-switching tests.A sinusoidal modulation is used to generate the PWM gate signals for the main switches.Besides the dead-time generation and collision avoidance, the signals are not further modified and are directly forwarded to the gate drivers.A variable timing control scheme, as previously described, and a collision avoidance algorithm are implemented for the auxiliary switches.Both control algorithms run sequentially on the microcontroller.Variable timing control relies on the online calculation of T ramp with the phase current sampling and the dc-link voltage measurement at the start of each pulse cycle T P .The polarity of I load determines whether S aux,p or S aux,n must be turned ON.

A. Implementation of the Collision Avoidance Algorithm
The flow chart of the implementation of the proposed collision avoidance algorithm, as presented in Section III-B, is shown in Fig. 11.
The algorithm starts with the edge timing t R3 , t S3 , and t T3 calculated by the modulation scheme (here SPWM) and the current sampling of each phase.Next, the number of voltage edges within a pulse cycle T P using ACSC needs to be determined.If ACSC is required for only one edge, the control algorithm is continued by placing the edges as originally requested.If two or three edges require ACSC operation, it is also necessary to determine the edge sequence of the three phases when calculating the activation times of each ACSC edge.Next, collision detection takes place for both cases.If no collision is detected, the control algorithm is continued by placing the edges as originally requested.the case of a single collision between two one edge is shifted ACSC always be activated for both edges.If the first and second edge causes the collision, the first edge is shifted to the left by at least the overlap time [see Fig. 9].If the single collision is caused by the second and third edges, the third edge is shifted to the right by at least the overlap time.In the case of a double collision between three phases, the first edge is at least shifted by the overlap time to the left and the third edge is at least shifted by the overlap time to the right.Thus, ACSC can be activated for all edges.When the shift is complete, the control algorithm continues with the new edges and outputs the collision-free pulse pattern.
The algorithm is executed once within T sw , whereby the collision-free pulse pattern is output in the following switching cycle.The algorithm here is optimized for a short execution time of the avoidance algorithm within the limited resources of the microcontroller.Therefore, a minor deviation of the edge placement is possible, especially in the rare case of double collisions, which can lead to an altered duty cycle and modulation index.For the considered operating points, no significant impact can be observed in Fig. 13, and no double collisions occurred.But if a more precise realization of the originally calculated pulse pattern is required, other collision avoidance methods as previously mentioned can be applied.

B. Component and Parameter Selection
The selection of the correct components and design parameters is very essential for the correct operation of the S 2 I-ARCP inverter and is discussed in the following.An overview of the results is given in Table II.
The design of the parameters I boost , L aux , C sn , and I th for S 2 I-ARCP is similar to that for conventional ARCP, described in detail in [27], [30], and [32].However, when selecting a proper value for the parameters in S 2 I-ARCP, the collision rate should also be considered.This leads to the following parameter design.
To ensure complete ZVS in every switching instant over the whole fundamental cycle, two conditions must always be met The dead-time of the main switches is set to T dead = 150 ns, which leads to a maximum permitted commutation time T com,acsc,max = 150 ns according to Fig. 4 and (15).The choice of a relatively low dead-time is possible due to the design with very low gate resistor values, which is particularly advantageous for the S 2 I-ARCP topology to keep the collision rate low.The phase currents are sampled at the start of each pulse cycle to obtain the current value of the fundamental.Complete ZVS should also be provided in case of a deviation of the actual current from the regular sampled value due to current ripple and in case of imprecise timing because of finite clock frequencies of the microcontroller.Since mainly the load current ripple I ripple limits the precision of the timing, it is essential to consider it in the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 12. Design of L aux , C sn , and I boost under the constraint of complete ZVS in all switching instants over the whole fundamental cycle.V dc is assumed to be 800 V, T dead = 150 ns, T com,acsc,max = T dead , and I ripple = |±2 A|.

TABLE II MAIN DESIGN PARAMETERS AND COMPONENTS OF THE PROTOTYPE
design.According to the measurement, I ripple is at most about |± 2 A|.Furthermore, two cases must be distinguished in this context.If the instantaneous load current is lower by I ripple , I ripple adds to the desired I boost , resulting in a minimum commutation duration T com,acsc,min and maximum tolerance duration T zvs,max .If the instantaneous load current is higher by I ripple , I ripple subtracts from the desired I boost , resulting in a maximum commutation duration T com,acsc,max and a minimum tolerance duration T zvs,min .
The two cases must always satisfy the ZVS conditions specified in (15).Fig. 12 shows the solution space as a function of L aux and C sn , which fulfills the constraint for complete ZVS.
The procedure is as follows.At first, I boost is calculated so that T com,acsc,max equals T dead resulting in the key figures T com,acsc,min , T com,acsc,max , I boost , T zvs,min , T zvs,max , dv/dt min , and dv/dt max .Solutions that do not meet the conditions are hidden in the next step.Finally, a valid design point is selected.
I boost should not be selected too high to limit the conduction losses [30], the maximum short-term component current stress [see (9)], the maximum dv/dt, and specifically in S 2 I-ARCP the collision rate [see Fig. 7(c)].The design of L aux is again a tradeoff.The upper bound is restricted by the collision rate [see Fig. 7(a)] and conduction losses in the auxiliary circuit.The lower bound is limited by the maximum di/dt and its EMI behavior and by the capability of the microcontroller.The Infineon XMC 4700 is based on the ARM Cortex-M4 processor core, with a clock frequency of 144 MHz (≈7 ns clock cycle).The clock cycle limits the precision of I boost .If the current rises too fast, the timing of the switch turn-OFF at t 2 , as shown in Fig. 4, can no longer be maintained accurately enough.
T com,acsc is significantly influenced by C sn , which in turn is the most important parameter for shaping the voltage edges and influencing the resulting dv/dt [34] to attenuate the highfrequency content.But C sn should not be selected too high to keep the collision rate, the peak current and the conduction losses in the auxiliary circuit low.Therefore, C sn is selected as low as possible by using only the output capacitance of the semiconductors and the parasitic structure-related capacitances and avoiding additional discretely connected capacitors.It can be estimated to C sn = 300 pF.
Considering the mentioned tradeoffs and constraints, the design marked with an X in Fig. 12 was originally selected.The design parameters then were I boost = 3.2 A and L aux = 5.7 μH.As will be discussed later, the effective C sn in ACSC operation is actually somewhat higher than in the first rough estimate and amounts about 500 pF.L aux was originally realized with 5.2 μH leading to the design marked with the circles O in Fig. 12.The resulting key figures are given in Table II.
This leads to a characteristic impedance Z r = 72 Ω and a resonant frequency f r = 2.2 MHz of the resonant circuit.Based on the choice of the design parameters V dc , L aux , C sn , I boost , the maximum load current I load,max = √ 2 • 14.4 A, and ( 4)-( 6), the maximum ramp time is T ramp,max = 330 ns, the resonant commutation duration is T com,acsc,max = 150 ns, and the maximum activation time is T act,max = 810 ns.The activation time should be a small fraction of the switching cycle T sw .By selecting the switching frequency to be 30 kHz, the maximum activation time of the auxiliary circuit amounts to 2.4% of T sw .In addition, an auxiliary circuit reactivation lockout-time of 100 ns is introduced for safety precaution to avoid the joint activation of the auxiliary circuit by different phases.
Finally, the maximum permissible commutation time of 100 ns under CSC operation results with (13) in a selected threshold current level I th = 5 A. C sn is again assumed to be 300 pF for simplicity.However, it is important to note that the effective C sn under CSC operation differs from ACSC operation.
Six 1200 V/50 A/30 mΩ SiC MOSFETs GeneSiC G3R30MT12K constitute the B6-topology with its six main switches.The SiC MOSFETs were selected for their low conduction losses at low load compared with IGBTs.Six 1200 V/25 A IGBTs (without freewheeling diodes) Infineon IGW25N120H3 with separate antiparallel 1200 V/10 A SiC Schottky diodes Infineon IDK10G120C5 form the auxiliary switches.The auxiliary switches only have to carry the current for a short period of time and can therefore be rated for a much lower continuous current load than the main switches.However, the selection should consider that the peak current load in the auxiliary switch is higher than in the main switch.The selected SiC Schottky diodes and IGBTs are highly overloadable for a short time.The choice of power semiconductor components used is based on availability and already considers future experiments with power transfers above 10 kW.The IGBTs were chosen because of their low cost and simpler control, since a bidirectional switch based on IGBTs naturally turns OFF at time instant t 6 when i aux changes its polarity.Hence, the exact turn-OFF time of S aux is not relevant.Conventional fast recovery Si diodes resulted in significant forward recovery losses in practical tests and were therefore replaced by SiC Schottky diodes.

V. EXPERIMENTAL RESULTS AND DISCUSSION
The previously discussed inverter design is experimentally verified at the operating point given in Table III unless otherwise specified.
The modulation index is chosen to 0.82, which corresponds to a phase rms voltage of 230 V.The three-phase resistive load is

A. Results Over Two Fundamental Cycles
Fig. 13 shows the filtered phase voltages, the collision detection signal, the phase currents, and the auxiliary inductor current over two fundamental cycles using soft-switching.
Series of collisions occur in 60 • intervals at the intersection points of two phase voltage curves, which corresponds to the sector transitions of the space vector diagram [see also Fig. 8(a) and the explanations in the previous chapter].The collisions are correctly detected and eliminated.The avoidance algorithm causes hardly any distortions, which proves its working principle.The phase currents are in phase with the phase voltages and reach a peak value I load,max = 20 A. Corresponding to (9), i aux reaches its peak at I load,max with I aux,max = 25.8 A. Similar to the collision detection signal, the envelope of i aux is 60 • periodical due to the sharing of the single inductor by the three phases.Therefore, the usual absence of i aux pulses for CSC operation, as shown in [27], can no longer be observed.I load and thus T act of the two phases are maximum in sum at the intersections of the phase currents, which for ϕ load = 0 • coincides with the collision region and therefore confirming the highest collision rate P rel observed in Fig. 7(b).Looking into the switching edges for the presented operating point, 2097 out of 3600 edges required ACSC operation.In 600 switching cycles within a fundamental period, about 60 collisions occurred, which all had been fully resolved by the edge shifting algorithm.Therefore, the resulting collision rate is 10%, which coincides well with the theoretical calculation from Section III-A and Fig. 7(a) predicting a collision rate of about 9%.

B. Switching Transition Waveforms
The proposed S 2 I-ARCP with its collision avoidance algorithm through edge shifting is verified in the following.For this purpose, the switching transition waveforms and the timing for an ACSC transition [case (Ia)], a CSC transition [case (II)] and, Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.for comparison, a hard-switching transition as well as an ACSC collision case are shown in Fig. 14 .
The operation point under ACSC operation in Fig. 14(a) is I load = 15 A, T ramp = 290 ns, T com,acsc = 95 ns, and T act = 675 ns.According to (5), this indicates an effective snubber capacitance of 500 pF under ACSC operation.Furthermore, the resulting maximum dv/dt max is about 9 kV/μs.The occurring parasitic oscillation in the auxiliary circuit is caused by L aux and the output capacitance of the six auxiliary switches with their antiparallel diodes.The frequency is about 3.4 MHz, indicating an effective capacitance of 420 pF in the auxiliary circuit.The excitation of this oscillation after the auxiliary switch turn-OFF Fig. 15.Measured efficiency results and total power losses under softswitching and hard-switching as a function of output active power.
is an inherent characteristic of the ARCP principle and occurs to the same extent in S 2 I-ARCP.If avoiding these oscillations for EMI reasons is desired, damping or saturated inductors [31] could be employed.However, the use of clamping diodes as proposed in [28] is not possible in the S 2 I-ARCP inverter due to the placement of the resonant inductor.The transition waveforms of CSC operation with I load = −16 A are shown in Fig. 14(b).The voltage ramps up linearly within T com,csc = 28 ns, resulting in a constant dv/dt = 29 kV/μs with a voltage overshoot of about 25 V.According to (13), this indicates an effective snubber capacitance of 280 pF under CSC operation, which is lower than under ACSC operation due to the disabled auxiliary circuit.Hard-switching with I load = 15 A is shown in Fig. 14(c).Here, the auxiliary circuit is disconnected and the HS-switch is turned-ON within 36 ns under full voltage (V dc ) causing high switching losses.The dv/dt peaks 67 kV/μs, resulting in high EMI emission with the largest voltage overshot of about 100 V.
The concept of shifting the switching edges to avoid collisions under ACSC operation is validated in Fig. 14(d).A collision between phase R and S, as assumed in Fig. 6, is detected by the algorithm.It then calculates the collision-free pulse pattern with the shifted switching edges under the compliance of T lock = 100 ns and outputs the pulse pattern in the immediately following switching cycle.According to Fig. 13, collisions can be observed when two phase currents are approximately ±10 A, which corresponds to the intersections of phase voltages for pure resistive loads.Note that the slightly higher current level of i load,R results in a slightly longer turn-ON duration of S R,aux .

C. Efficiency and Power Loss Analysis
An efficiency measurement was performed using the precise power meter Yokogawa WT5000.The auxiliary circuit was disconnected for the hard-switching test.Power losses occurring in the sine-wave filter are not included in the measurement results.Short-time operation (<5 s) was used to keep the temperature of the heat sink at room temperature at each measurement point to ensure comparable measurement conditions.Fig. 15 shows the efficiency curves and the power losses for pure resistive loads (ϕ load ≈ 0 • ) against the ac output power under soft-switching and hard-switching.
Soft-switching in S 2 I-ARCP improves the efficiency by about 0.45% at 4 kW and by about 0.25% at 10 kW, which corresponds to a loss reduction of 44% at 4 kW and 38% at 10 kW compared with hard-switching.The efficiency of the inverter peaks at 99.58% in soft-switching operation and decreases very slightly at high loads.At these load conditions, conduction losses begin to dominate over other losses.It can be seen that the improvement in efficiency and the reduction of power losses are even greater at low loads.In addition, an increase in losses can be observed for the hard-switching but not for the soft-switching operation.Depending on the current direction under hard-switching, only one switch of the half-bridge causes losses, while the other turns ON and OFF virtually lossless.At low currents, the turn-ON of the complementary switch is prone to losing the loss-less turn-ON because the capacitively driven voltage transition is too slow.As the switching energy for turn-ON is higher in our setup due to our gate resistor selection, a significant rise in losses could thus be explained at low load.Likewise, this loss increase proves the need for ACSC in case (Ib) in our soft-switching inverter.
Furthermore, a thermographic comparison between softswitching and hard-switching is performed by using a thermal imaging camera FLIR T530.For this purpose, a thermal image was taken under steady-state conditions for both cases.The cooling is provided by natural convection.The results are shown in Fig. 16.
The temperature is measured with two different measurement points at the heat sink of the main switch (1, 2) and at the heat sink of the auxiliary switch (3).With soft-switching, the temperature of the main switch heat sink is about 30 K above room temperature, while for hard-switching it reaches 70 K above room temperature.Thus, minimizing switching losses through soft-switching results in a temperature rise that is less than half that of hard-switching.The temperature at the heat sink of S aux reaches about 40 K above room temperature.However, it should be noted that the heat sink of the auxiliary switches is much smaller than the heat sink of the main switches.Obviously, a part of the saved switching losses is transferred to the losses of the auxiliary circuit.But the power losses are distributed to more electrical components.With the reduction in power losses and with this kind of thermal spreading, soft-switching can enable higher power transfers with the given prototype or allows the choice of a considerably smaller heat sink compared with hard-switching.

D. Discussion
In summary, the presented challenges of implementing an S 2 I-ARCP and its results can be evaluated as follows.The proposed concept can save two of the three resonant inductors compared with the conventional three-phase ARCP.Hence, the single resonant inductor is better utilized through the joint Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.use of the three phases, but brings the problem of collisions.When selecting the design parameters, the number of collisions that occur must also be considered.With consideration of the permissible dv/dt max , C sn should be kept as low as possible to obtain low collision rates, resulting in rather short commutation durations.The parallel connection of additional large discrete capacitors, such as in [21], [24], [26], and [35], to increase the value of C sn , is therefore undesirable in S 2 I-ARCP compared with conventional ARCP.
Determination of the appropriate design parameters should be based on the actual value of the snubber capacitors.Since C sn mainly consists of the output capacitances of the semiconductors and different switching configurations are active during ACSC and CSC operation, the effective value of C sn differs.In addition, the total value is not known sufficiently accurate due to additional parasitic structure-related capacitances.Those originate mainly from the printed circuit board layers (for this prototype 130 pF between node A and DC− and 77 pF between an output terminal R, S, T, and DC−).However, the value of an effective C sn for both operational modes can be easily determined by measurement and recalculation.They are C sn = 500 pF for ACSC and C sn = 280 pF for CSC, respectively.This allows the control parameters, such as T dead , I th , or I boost , to be tuned to an optimized fixed value.To obtain an initial selection of the design parameters, a rough estimate was made using C sn = 300 pF.However, the measurements indicate an actual effective C sn under ACSC operation that is 200 pF higher than originally assumed.
The phase currents are sampled once at the start of each pulse cycle to obtain the fundamental value.The determination of a collision-free pulse pattern, based on sinusoidal modulation, is then performed.The variable ACSC parameters I ramp and hence T ramp are calculated based on the sampled I load .The pulse pattern is forwarded to the output stage in the following pulse cycle.Therefore, the pulse position regarding the output current ripple and the time offset of the current sampling are neglected when calculating the ACSC timing.This leads to a considerable deviation of the sampled current from the actual instantaneous value when the auxiliary circuit is activated.The result is a deviation of the actual I boost from the desired value.The deviation is at most about ±2 A, resulting in different T com,acsc covering a time range of 95-150 ns and thus leading to different voltage slew-rates of about 6.5-9.2 kV/μs.Since T com,acsc does not remain constant over time, the time instant t 4 and t 5 cannot be calculated accurately.However, to ensure complete ZVS over the whole fundamental cycle, a suitable ZVS precision tolerance T zvs and thus I boost were chosen according to the maximum boost current deviation.
Moreover, T act and thus, the time instant t 6 cannot be calculated accurately.For this reason, the S aux turn-OFF is delayed by 80 ns, as shown in Fig. 14(d), to ensure L aux is never turned-OFF at harmful current levels.

VI. CONCLUSION
In this article, a novel three-phase ARCP inverter with a single shared resonant inductor is presented.The topological reduction can lead to a forbidden simultaneous use of the shared auxiliary inductor by the three phases, and thus to collisions when accessing the auxiliary circuit.A collision avoidance algorithm with shifting the switching edges is presented to avoid simultaneous use of the auxiliary circuit by different phases.The dependence of the collision rate on different operating parameters has been analyzed in detail.To verify the functionality of the proposed approach, a three-phase 800 V 10 kW S 2 I-ARCP inverter with the suggested collision avoidance algorithm has been implemented and put into operation.The results of the measurements have confirmed the proposed concept and the analytical theory.Efficiency measurement results indicated a significant loss reduction in soft-switching operation by more than 38% compared with hard-switching, with a peak efficiency value of 99.58%.Overall, the S 2 I-ARCP inverter offers a better alternative to the conventional ARCP soft-switching topology due to its reduced passive component count and the better utilization of the shared resonant inductor without compromising the output voltage quality.The savings in volume (in the case of air coils), weight, and cost (in the case of magnetic cores) outweigh the more complex control.Due to its advantageous characteristics and controllable dv/dt, the S 2 I-ARCP is well suited for applications, such as grid inverters for renewable energy or inverters in traction drives for electric vehicles.

Fig. 1 .
Fig. 1. Circuit diagram of the proposed three-phase two-level ARCP topology with a single shared inductor (solid black line) and the conventional ARCP circuit configuration (dotted green line).

Fig. 5 .
Fig. 5. Equivalent circuit during commutation stage under (a) ACSC and (b) CSC with the initial values at time instant t 2 .

Fig. 7 .
Fig. 7. Single collision rate analysis for different operating points.(a) P rel versus L aux and C sn .(b) P rel versus ϕ load and m a .(c) P rel versus I load,rms and I boost .V dc = 800 V, f sw = 30 kHz, f el = 50 Hz, and f sw /f el = 600 apply to all operating points.

Fig. 8 .
Fig. 8. Location of collisions in the space vector diagram for different operating points.No collisions are marked with the green area, whereas one or more collisions are marked with the red area.(a)-(c) With ascending phase angle in low load condition.(d)-(f) With ascending phase angle in high load condition.V dc = 800 V, f sw = 30 kHz, I boost = 5 A, C sn = 140 pF, and L aux = 5 μH apply to all operating points.

Fig. 9 .
Fig. 9. (a) Single collision avoidance by shifting the rising and falling edge of phase R relative to phase S. Note that t R3 , t S3 , and t T3 correspond to time instant t 3 in Fig. 4. (b) Single collision avoidance by shifting the edges of phase T. (c) Double collision avoidance by shifting the edges of phase R and T.

Fig. 10 .
Fig. 10.(a) Experimental setup structure and the stages of pulse generation for the proposed three-phase ARCP inverter with a single shared inductor.(b) Experimental prototype of the S 2 I-ARCP.

Fig. 11 .
Fig. 11.Flowchart of the implemented control algorithm by shifting the switching edges.
connected to the output terminals of the inverter in wye (Y) configuration via a sine-wave filter.According to Fig.7(b), the choice of a resistive load leads to the highest collision rate and should therefore be examined.The potential of the load-side neutral point is floating.To simultaneously acquire the time signals, a Keysight MXR058A oscilloscope with eight channels is used.A series of three-phase experiments are presented and compared in the following.

Fig. 13 .
Fig. 13.Load-side experimental results (after the sine-wave filter) over two fundamental cycles using soft-switching.(a) Phase voltages and collision detection signal.(b) Phase currents and auxiliary inductor current.

Fig. 14 .
Fig. 14.Switching signals, current and voltage waveforms during rising edge transitions.(a) Rising edge transition under ACSC operation [case (Ia)].(b) Rising edge transition under CSC operation [case (II)].(c) Rising edge transition under hard-switching.(d) Collision avoidance under ACSC operation by shifting switching edges.Note that the propagation delay of the logic signals has been removed for clear displaying purposes.