Stability, Reliability, and Robustness of GaN Power Devices: A Review

Gallium nitride (GaN) devices are revolutionarily advancing the efficiency, frequency, and form factor of power electronics. However, the material composition, architecture, and physics of many GaN devices are significantly different from silicon and silicon carbide devices. These distinctions result in many unique stability, reliability, and robustness issues facing GaN power devices. This article reviews the current understanding of these issues, particularly those related to dynamic switching, and their impacts on system performance. Instead of delving into reliability physics, this article intends to provide power electronics’ engineers the necessary information for deploying GaN devices in the existing and emerging applications, as well as provide references for the qualification evaluations of GaN power devices. The issues covered in this article include the dynamic instability of device parameters (e.g., on-resistance, threshold voltage, and output capacitance), the device robustness in avalanche, overvoltage and short-circuit conditions, the device's switching reliability and lifetime, as well as the device's ruggedness under radiation and extreme (cryogenic and elevated) temperatures. Knowledge gaps and immediate research opportunities in the relevant fields are also discussed.

power semiconductors have been commercialized, i.e., silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) [1]. As compared with Si and SiC, GaN has superior properties, including the larger bandgap and higher critical electric field. Additionally, the AlGaN/GaN heterostructure forms two-dimensional electron gas (2DEG) with very high mobility, which can be further used to construct the high-electron mobility transistor (HEMT). GaN power HEMTs have been recently commercialized with the voltage classes from 15 to 900 V, and they are seeing rapid adoption in power supplies, data centers, Lidar systems, and fast chargers in consumer electronics [2], [3], [4], [5]. Benefitted from the smaller capacitances and charges, GaN power devices have enabled the lighter, smaller, and more efficient power electronics' systems. The market size of GaN power devices is projected to exceed $1.26 billion by 2027 [5].
While GaN devices are currently being deployed in a variety of applications, there are still open questions to be answered regarding their stability, reliability, and robustness. This is largely because the architecture and physics of GaN HEMTs are very different from Si and SiC devices, such as MOSFETs, JFETs, and insultated gate bipolar transistors (IGBTs). GaN HEMT is a lateral device without p-n junction connected between source and drain, and its current is confined in a two-dimensional channel with a thickness of merely a few nanometers. Additionally, many GaN HEMTs are fabricated on foreign substrates, e.g., Si and sapphire, leading to a higher density of defects and traps as compared with Si and SiC devices built on native substrates.
Extensive efforts in academia and industry are ramping up to address the stability, reliability, and robustness issues facing GaN devices. For example, over 300 and 200 articles have been published on the topics of "GaN reliability" and "GaN power reliability" in the year 2021 according to the Web of Science database. In addition, while there has maintained a steady trend of publishing reliability studies on the R&D GaN devices demonstrated in research laboratories, an increase in publication on commercially available devices is observed. This trend converges with the industry's efforts on developing the standards for GaN qualification. For example, the "JEDEC" JC-70 committee has been providing insights into new test methodologies for GaN power devices [6].
In the previous literature, various aspects of GaN power HEMT reliability have been periodically surveyed [7], [8], [9], [10], [11], but most of these articles are from the device physics  perspective and are centric on R&D devices. The processing technology, material, and structure of R&D devices are usually immature compared with commercial devices, and some test conditions for reliability physics' studies are different from the device operations in practical converters. These situations make it difficult for power electronics' engineers to correlate the reliability physics and the nonideal behaviors of commercial GaN devices in converters. This challenge also hinders the further development of the health monitoring, prognosis, and protection systems.
This article attempts to address this gap by summarizing the current understanding on the stability, robustness, and reliability of GaN power devices, with an emphasis on reports of industrial devices. This article also tries to separate stability, robustness, and reliability issues, although in practice they often come interdependently with relatively ambiguous boundaries. Fig. 1(a) illustrates the device electrical stressors in common stability, reliability, and robustness studies in comparison to the device's rating and safe-operating area (SOA). Stability usually refers to recoverable changes in device electrical characteristics as a result of the transient or sustained switching operation within the SOA [10]. Due to carrier trapping and detrapping within the device structure, the device characteristics can deviate from the static ones without leading to device failure.
Reliability and robustness often refer to nonrecoverable device degradation and failure. The stimulus (e.g., current or voltage) stress in reliability and robustness tests is usually near the SOA boundary and outside the SOA, respectively. Fig. 1(b) shows the other angle to differentiate reliability and robustness. Robustness tests often approach the destruction limits of device stimuli with a timescale much shorter than reliability tests. The timescale of robustness tests can be even down to a single cycle of switching, while that of reliability tests is usually at least hours up to weeks, months, and years.
The stability, reliability, and robustness overview for GaN power devices is motivated by three overarching questions.
1) What are additional power losses induced by the device parametric instability in conduction and switching? 2) What information do various device-and circuit-level reliability tests provide for practical applications? 3) What is the device's circuit-level resilience against surge energy, overvoltage, overcurrent, and their concurrence? The answers of these questions ultimately help power electronics' engineers to achieve the desired efficiency in GaN converters and reserve proper margin during the design for desired lifetime of the GaN-based power product.
In addition to the conventional applications, GaN power devices are regarded as promising candidates for space, aeronautical, and defense applications. The devices for these applications are usually required to be rugged against radiation and at extremely high or low temperatures. Hence, the radiation and extreme temperature robustness have become increasingly important for power devices.
The rest of this article is organized as follows. Section II overviews the current commercial GaN power devices and common failure locations. Section III overviews the traditional qualification and reliability test results reported for GaN HEMTs, and Section IV surveys the extended reliability data from major GaN device vendors. Section V presents the stability issues of GaN HEMTs, including the dynamic ON-resistance, dynamic threshold voltage, and output capacitance losses, which are all critical to power applications particularly at high frequencies. Section VI details the robustness of GaN HEMTs in out-of-SOA conditions, such as overvoltage, short circuit (SC), and surge energy. Section VII discusses the research exploring the switching reliability and lifetime of GaN devices in converters and under mission profiles. While GaN HEMTs are discussed in prior sections, Section VIII introduces the robustness of the emerging vertical GaN devices that are being commercialized in the industry. Sections IX and X discuss the radiation and extreme temperature ruggedness of GaN devices, respectively. Section XI lists some immediate research needs. Finally, Section XII concludes this article.
Note that the reliability studies of nonindustrial emerging GaN devices are not covered in this article. Some multidimensional GaN devices [1], such as FinFETs [12], [13] and multichannel HEMTs [14], have demonstrated breakthrough performance in ultralow voltage classes down to a few volts [15], [16] and in higher voltage up to 10 kV [17], [18]. While reliability studies of these devices are ramping up [19], [20], [21], they are still at a relatively early stage of development.

A. Current GaN Power Devices
Four types of device architectures are primarily employed in commercially available GaN products. Two of these include the hybrid-drain gate injection transistor (HD-GIT) and the Schottky p-gate HEMT (SP-HEMT). These technologies are discrete devices and utilize a p-GaN layer in the gate stack to realize the enhancement-mode (E-mode) operation. Their schematics are shown in Fig. 2(a) and (b).
The other two architectures can be considered composite devices where the cascode structure and direct-drive modules utilize multiple semiconductor dies of which the GaN HEMT is usually the depletion mode (D-mode). Fig. 2(c) shows a photograph of a decapsulated cascode HEMT and its schematics [22], [23]. Fig. 2(d) and (e) show the photographs of direct-drive GaN device/module from two different vendors [24]. Fig. 3 depicts the current and voltage ratings of available commercial GaN devices from various vendors. The precommercial vertical GaN field effect transistor (FET) is also included and will be elaborated in Section VIII.
To be cost competitive, the majority of commercial GaN HEMTs are fabricated on Si substrates. Above this substrate includes a transition layer and then the primary GaN buffer layer. An AlGaN layer is deposited above the GaN buffer layer, and it is the interface between the AlGaN and GaN layers that creates the primary channel to conduct current. The lattice mismatch of these two layers creates a piezoelectric effect, which creates a 2DEG channel. The drain, gate, and source terminals are oriented laterally above the AlGaN layer. The p-GaN in the gate stack is key to realization of E-mode operation. This E-mode operation is the preferred choice for power electronics' applications.
The distinction between HD-GIT [see Fig. 2(a)] and SP-HEMT [see Fig. 2(b)] is mainly located in the gate and drain region. The gate metal forms an Ohmic contact to p-GaN in the HD-GIT and a Schottky contact in the SP-HEMT. The AlGaN layer in the HD-GIT is usually recessed, enabling a closer proximity of p-GaN to the 2DEG. The Ohmic contact and AlGaN recess in the HD-GIT favors hole injection into the 2DEG channel, enabling the conductivity modulation. In addition, the HD-GIT includes a p-GaN region connected to the drain, which enables the hole injection into the channel and buffer to alleviate the electron trapping. By contrast, the current conduction in the SP-HEMT only relies on electrons, and minimal holes are injected into the device channel and buffer regions.
In the cascode and direct-drive devices, the traditional highvoltage D-mode GaN devices are oriented with a lower voltage E-mode Si power MOSFET. Through the connection of the two devices [23], [25], a high-voltage E-mode device is created for the cascode device.
The direct-drive devices advance this principle further by incorporating integrated circuit (IC). In this way, a gate driver can be implemented with the power semiconductor to optimize the gate-loop performance and ease the requirements of additional components. Some devices also include sensing and protection ICs for added capabilities.
Overall, these two topologies allow for the use of D-mode HEMT, which usually has a simpler gate stack in comparison to the HD-GIT and SP-HEMT [26]. However, the inclusion of multiple chips in the package brings additional driving challenges as well as the introduction of new failure and instability mechanisms that could be triggered and coupled between the multiple chips [22]. These challenges will be elaborated in the later sections.

B. Usual Failure Locations
Here, we list some common failure modes and locations in GaN HEMTs to provide an abstract, physical reference for understanding results in the following sections. In Si and SiC MOSFETs, there are known issues within the gate-oxide layer due to various stresses from the gate and drain biases [27], [28]. Additionally, the p-n junction of the MOSFET structure has shown various bipolar stability issues [29].
Differently, many reliability issues of GaN HEMTs are predominantly imposed by carrier trapping effects at various interfaces and layers within the device, as illustrated in Fig. 4. Severe trapping can greatly affect the local electric field and current density, thereby impacting the device ON-resistance, breakdown voltage, and capacitances. In addition to trapping, some other physical processes, such as impact ionization, electrothermal failure, and percolation path creation, can also lead to device failure under different stresses. For example, the carriers generated in impact ionization, if not removed efficiently, can induce the destructive device breakdown [30]. In the GaN HEMT, these processes usually occur at the gate region, AlGaN/dielectric interface, GaN buffer region, transitional layers, and Si substrates. In composite-type GaN devices, the failure locations can be more diverse, e.g., in the multichip interconnect or in Si chips.

III. TRADITIONAL QUALIFICATION AND RELIABILITY TEST
As illustrated in Fig. 1(b), traditional accelerated lifetime and reliability tests are designed to help in the qualification of packaged devices for industrial applications by evaluating two primary focuses stressing either the semiconductor-oriented or the packaging-oriented failure mechanisms. While there are international entities that have produced standards for testing semiconductors (e.g., JEDEC, IEC, AEC-Q, MIL-STD, etc.), many qualifications have a foundation from Si technologies. It is now largely an industrial consensus that these standard qualifications (e.g., JEDEC qualification) for GaN devices are necessary but not sufficient and must be followed up by other comprehensive tests. A few industry groups, such as the JEDEC JC-70 Committee [6] and the joint ZVEI European Center for Power Electronics (ECPE) group [31], are actively working to evaluate and update these standards, and provide guidelines for future device evaluations focused on the stresses that GaN devices would experience over the traditional Si transistors.  I  EXEMPLAR LIST OF THE AEC Q101 QUALIFICATION TESTS FOR A 650 V,  50 MΩ GAN CASCODE HEMT Automotive qualification for GaN devices has attracted great traction recently. Traditional automotive qualification routines are usually based on the AEC-Q100/Q101/Q200 family for Si devices. Table I illustrates one of the first reported automotive qualifications for a 650 V, 50 mΩ cascode GaN HEMT based on the AEC-Q101 standard [32]. The AEC-Q101 qualification for other GaN devices (e.g., SP-HEMT) comprises similar tests except for using a positive gate bias (e.g., 6 V) in the relevant gate tests.
The ECPE recently released a comprehensive automotive qualification standard, namely LV324, expanded upon the AEC standard [31]. The standard comprises a large number of tests categorized into three groups, the qualification characterization tests (QC), qualification environment tests (QE), and qualification lifetime tests (QL). The QC consists of tests on the device's parasitic stray inductance, thermal resistance, and SC robustness. The QE tests involve thermal shock, vibration, and mechanical shock. The composition of the QL tests is similar to that shown in Table I.
While good qualification data have been released by many GaN device vendors, it would be still very useful for power electronics' engineers to know possible GaN device degradation under these qualification tests, particularly for the evaluation of future devices. Hence, we briefly summarize the reported GaN device degradation under several representative qualification and reliability tests, including the static dc-bias tests, such as high-temperature reverse bias (HTRB) and high-temperature gate bias (HTGB), as well as switching tests, such as power cycling.

A. High-Temperature Reverse Bias
HTRB experiments used for device qualification usually apply a stress at 80% of the device rating (for some applications, such as the automotive, up to 100% of the rating) [33]. These qualifying experiments can take thousands of hours [34], [35], [36]. Under HTRB stress, a positive shift has been reported in the ON-resistance (R DS,ON ) and threshold voltage (V TH ), but the changes do not reach a failed state [37], [38], [39]. In more accelerated HTRB experiments (where the drain voltage is higher than the rated voltage), the V TH instability in some early GaN HEMTs has shown up to a 50% increase, which is above the notional 20% shift failure boundary but recoverable [40].
Determining the voltage stresses in the accelerated HTRB experiments is a challenge for GaN HEMTs because of their dynamic breakdown voltage [41]; this is in comparison with MOSFETs that have an inherently constant avalanche breakdown voltage [27], [42]. Additionally, when MOSFETs are stressed in HTRB experiments, they show an increase in gate-leakage current (I GSS ) but some GaN HEMTs show a decrease in I GSS and drain-leakage currents (I DSS ) [40], [43]. These shifts in electrical parameters are all related to electron trapping and detrapping [34], [35], [40].

B. High-Temperature Gate Bias
HTGB experiments apply a high static bias onto the gate terminal of the GaN device. Similar tests with a static bias and step-stress processes have been used to determine the gate voltage rating of GaN HEMTs [37], [44], [45], [46], [47], which will be further discussed in Section VII.
HTGB experiments have also shown to cause shifting in V TH and R DS,ON [37], [43], [44] due to trapped charges in the gate stack. The type of contact formed on p-GaN, either Schottky or Ohmic, would impact these drifts [48]. The Ohmic contact is capable of more efficient hole injection in comparison with the Schottky contact, which would minimize the V TH shift [37].

C. Power Cycling
Power cycling experiments are primarily used to stress the packaging of a commercial device and the interface between the device and package. The stress is created through the repeated, (self) heating of the device with ON-state current causing strain in the mechanical layers due to the differences in the coefficient of thermal expansion mismatch [49], [50], [51].
The p-gate GaN HEMTs have been reported to show V TH and R DS,ON increase in power cycling [49], [51]. Depending on the magnitude of the temperature swing, I DSS has also shown to increase as well [49], [52]. While solder fatigue has been reported and does impact the increase in R DS,ON , the changes in V TH and I DSS provide evidence that trapping effects cause further degradation in device [49].
Composite-type devices have a greater susceptibility to degradation and failure within the mechanical interconnections from power cycling stresses. Both Xu et al. [49] and Franke et al. [50] have reported that the cascode devices show an increase in R DS,ON . The V TH , however, was not identified as a sensitive precursor parameter for cascode devices under power cycling experiments [49]. The final failure mechanism was attributed to bond-wire lift-off between the Si MOSFET and GaN HEMT [50].

IV. EXTENDED RELIABILITY DATA BY DEVICE VENDORS
While all GaN power devices from major vendors have passed the JEDEC and AEC-Q standards, additional reports have been published by these vendors to provide data regarding the device stability, reliability, and robustness beyond the Si qualification standards. Table II summarizes these extended test data from major GaN device vendors, including EPC, Infineon, GaN Systems, and Transphorm [53], [54], [55], [56].
As illustrated in the table, the common extended reliability data from various vendors mainly address several aspects: 1) dynamic R DS,ON issue, which is related to device parametric stability and conduction loss in applications; 2) the accelerated lifetime extraction under various stimuli, including the drain-to-source bias (V DS ), gate-to-source bias (V GS ), and temperature; 3) the accelerated lifetime testing under various mission profiles mimicking the device operations in some representative applications. Examples of such switching stress include the hard-switched boost converter, double-pulse-based setup, and soft-switched converters. In some context, such test is named the hightemperature operating life (HTOL) test, and the test circuit topologies include a boost converter [32] and the half-bridge converters with RC load or RL load [57].
The extensive test data manifest the insufficient qualification of GaN HEMTs using the conventional Si standards. However, one can find that the data presented by different vendors are often obtained from different methods, and most of the derived reliability models are vendor specific. For example, the V DS overvoltage robustness is characterized by both dc stress and pulsed voltage by Infineon and only by dc stress by other vendors. Another example is the large variety of circuit topologies used to extract the switching stress lifetime by various vendors. Finally, critical device robustness, such as the SC capability, is only reported by one vendor, and some other parameters, such as avalanche (surge-energy) capability, are not reported by any vendor.
To address these gaps, many studies have been performed by researchers and engineers in the academia and industry to do the following: 1) explore and compare various methods to characterize the stability, reliability, and robustness of GaN HEMTs; 2) identify the common or distinct behaviors that are correlated to characteristic device structures instead of being vendor specific; 3) generalize unified models for device dynamic parameters and lifetimes for various GaN HEMTs. While not all of these gaps have been fully addressed, the summary of current understandings provides useful information for device users. The high-level explanation of the relevant physical mechanisms could help device users understand the potential problems of GaN devices and how they differ from Si and SiC devices. These summaries and explanations will be provided in the next few sections.

V. STABILITY IN SWITCHING
Parametric instability in GaN HEMTs is usually associated with the trapping behavior (trapping and detrapping). The accurate measurement of parametric shifts, particularly in highfrequency switching, is very challenging. This is because the occupation probability of traps depends on its electrical history and the trapping behavior usually spans the time constants over many orders of magnitude [10]. Here, we first scrutinize various measurement methods [58], [59] and clarify the time constant range associated with each method. This allows us to understand how the results from these measurements correlate to device switching operation in practical converters.
Generally, three types of stability and reliability tests have been widely used for power devices, i.e., the dc stress test, pulse I-V test, and circuit test. Table III summarizes the key features of these tests. The dc stress test usually characterizes the relatively long-term parametric shifts after an OFF-state dc stress. It cannot capture the parametric shifts that recover within the poststress measurement time (usually at least ∼10 s). Therefore, the measured shifts are not representative of those present in transient switching. The pulse I-V test can probe the dynamic parametric shifts in a short time (down to 1 μs) right after the switching stress. However, the pulse I-V condition is still different from converters, as it is based on the square wave with a resistive load and has a limited dv/dt. Circuit tests allow for characterization of device's parametric shifts under the application-use conditions. Additionally, benefitted from the small time constant of the stress that can be implemented in circuits, the switching stress of interest is no longer limited to the OFF-state stress but can also accommodate the ON-state stresses (e.g., SC and gate overvoltage). The challenges in circuit tests are on the in situ measurement of the parametric shift of interest with a minimal disturbance on the converter operation. Finally, one should be careful about the parametric shifts evaluated in the single-event and steady-state switching, which could be different due to the distinction in trapping states. This will be further explained in the evaluation of D-R DS,ON and dynamic breakdown voltage.
In the remaining part of this section, we will present three major parametric stability issues in GaN HEMTs during their normal switching operations (i.e., within the SOA).

A. Dynamic ON-Resistance
Dynamic R DS,ON (D-R DS,ON ) is a well-known issue in various types of GaN HEMTs, where the R DS,ON is higher than its measured dc value after high blocking voltage stress. D-R DS,ON leads to undesirable increases in the device conduction loss and junction temperature, yet it is not commonly specified in datasheets. This D-R DS,ON poses serious challenges in designing GaN-based power converters, especially for high-frequency applications. Over the past decade, extensive studies have been devoted toward understanding and addressing different aspects of the D-R DS,ON phenomenon, including its physical origin, dependency factors, characterization method, etc.
1) Physical Origin: D-R DS,ON roots from the trapping effect in various possible regions of the GaN HEMT structure, as shown in Fig. 4. Leakage current electrons injected under high drain bias [60] and hot electrons generated during switching transitions due to the overlap of high voltage and high current [61] could cause charge trapping in the buffer layer, GaN channel and gate region, as well as near the surface and/or in the dielectric. Each of these can decrease the 2DEG conductivity and increases R DS,ON . The physical mechanisms have been thoroughly reviewed in [62] and will not be elaborated in this article. At the device level, various technologies, such as surface passivation optimization [63], elaborately designed GaN buffer [64], and optimal field-plate structure [65], have been proposed to reduce the trapping effects and eliminate the D-R DS,ON issue. Fig. 5 illustrates the typical R DS,ON variation during a switching event of GaN HEMTs. The increase in D-R DS,ON (electrontrapping effect) mainly exists in two stages: the first one is induced in the OFF-state, and the second is related to the hard turn-ON process. In the ON-state, detrapping of these electrons allows the R DS,ON to gradually settle back to its static value. Note that the soft turn-ON process is not expected to induce significant D-R DS,ON in most GaN HEMTs.
As the review [62] published in 2019, many recent studies on SP-HEMTs and HD-GITs have reported consistently new understandings on the D-R DS,ON issue. First, the D-R DS,ON is more strongly affected by the hard turn-ON process than the OFF-state [66], [67], [68], [69]; Second, the OFF-state stress primarily induces electron trapping in the buffer, while the hard turn-ON stress induces electron trapping in both the buffer and the interface between AlGaN and passivation layer [67], [70]. Some studies report the interface/surface trapping to dominate in the hard turn-ON process while observing the impact of buffer region design [66], [67] and drain field-plate design [71] on surface trapping. Studies have also shown that the traps relevant to the hard turn-ON process possess a broadly distributed but relatively shallow energy level [72], [73].
2) Dependency Factors: As D-R DS,ON is caused by the device switching transition, numerous research articles have reported the influence of varying operating conditions in power converters on the D-R DS,ON .
The number of trapped electrons depends very much on the blocking voltage, and a nonmonotonic relation between D-R DS,ON and OFF-state and drain-to-source voltage (V DS,OFF ) has been identified in [74], [75], and [76]. It has been shown that D-R DS,ON increases with V DS,OFF until it reaches a maximum at typically 100-300 V (for a ∼600-V rated device). However, the D-R DS,ON recovers to smaller values at higher V DS,OFF due to partial neutralization of buffer traps [74]. Additionally, the load current (I L ) affects the hot-electron acceleration, and thus trapping efficacy, particularly in the hard turn-ON process. Therefore, a higher D-R DS,ON is observed as I L increases [77], [78]. Switching speed (and duration) determines the quantity of trapped hot electrons, so a larger gate resistance could induce the more serious D-R DS,ON issue [79]. Higher gate current/gate voltage [80] can facilitate a faster detrapping process during the ON-state and contributes to a smaller D-R DS,ON .
As the time constant of trapping behavior can span from nanoseconds to seconds [81], [82], D-R DS,ON is dependent on the switching frequency and duty cycle [83]. The probability of electron trapping and detrapping is also related to junction temperature (T J ). Inconsistent reports are present for various devices that the D-R DS,ON either increase [84] or decrease [85] at higher T J or show more complex dependences [86]. For example, the D-R DS,ON of HD-GITs is found to increase with T J at low V DS,OFF but decrease with T J at high V DS,OFF , which is related to the effectiveness of hole injection in HD-GITs [86]. The dependence between D-R DS,ON on T J may be device specific and impacted by V DS,OFF and switching schemes.
Finally, the D-R DS,ON differs in hard switching (HSW) and soft switching [87], [88], [89], but its dependency could be device specific [90]. Soft switching leads to a lower D-R DS,ON in SP-HEMTs [91] by eliminating the impact by hot-electron effects; in HD-GITs, injected holes from the drain p-GaN layer  [90].
3) Characterization Method and Results: Despite extensive efforts in D-R DS,ON characterizations, large discrepancies have been reported in the literature from a minimal increase to a ten times higher gain over static R ON [92], even for commercial devices. It was recently pointed out that this inconsistency largely originates from the characterization methods [92]. Table IV summarizes the key aspects of three most commonly used D-R DS,ON characterization methods, including pulsed I-V test, double-pulse test (DPT), and steady-state continuousswitching test. By employing source measure units to modulate the voltage bias at multiple device terminals, the pulse I-V test is usually performed at wafer level with resistive load and used in many trapping physics' studies [82], [93], [94]. The overlap of current and voltage could be changed to simulate HSW/soft switching, but it cannot mimic the switching locus and slew rate (e.g., dv/dt) in real applications.
The classic DPT method, as recommended by the JEDEC standard [95], has been used in various circuit topologies with inductive load [79], [85], [86], [87], [95]. However, DPT could miscalculate the device D-R DS,ON in continuous-switching power converters [96] because it ignores the accumulation effects in repetitive switching cycles. In addition, DPT usually does not specify the OFF-state stress time before the first pulse, which could lead to uncertainties in D-R DS,ON .
More recently, state-of-the-art D-R DS,ON test design has been focusing on the continuous-switching method where the GaN devices are switched to the steady state in power converters, including half-bridge topology [78], [90], [96], buck converter [83], [97], resonant converter [85], [98], etc. With the realistic application profile, steady-state continuous-switching test is the best practice to perform a D-R DS,ON characterization. It is noteworthy that D-R DS,ON in continuous-switching converter (boost converter circuit [99]) has been performed at the wafer level, which could significantly shorten the R&D process of GaN HEMTs. The key to achieve this ON-wafer dynamic characterization is the accurate control of parasitics in the whole system, e.g., probe tip, connectors, and cables, which allows for reaching high switching speed and switching voltage/current.   Table V show the normalized D-R DS,ON measurement results of commercial GaN HEMTs under the steady-state switching conditions, characterized from hundreds of kilohertz up to several megahertz [80], [90], [97], [100]. Target devices include both SP-HEMTs and HD-GITs, whereas measurements of composite devices are still lacking. These devices were tested at nominal voltage levels (∼67% voltage rating, e.g., 400 V for 600/650-V devices) and nominal current level (∼50% current rating, e.g., 8 A for 15-A devices). With a steady-state switching measurement protocol, the worst-case D-R DS,ON of commercial GaN HEMTs was found to be less than three times higher than the static value. For the same device, D-R DS,ON generally increases as the switching frequency goes up. Below 1 MHz, the D-R DS,ON among all tested devices was within twice the static value, regardless of switching mode (hard or soft). In multi-MHz switching, D-R DS,ON of certain devices presented a saturation with frequency (e.g., 2 MHz in Fig. 6). This could be a result that the time constant of the combination of trapping and detrapping effects is exceeded [97].
From the application viewpoint, the D-R DS,ON characterized in application-use conditions provide valuable references for converter design and performance evaluation. The efficiency of GaN-based converters is directly affected by D-R DS,ON due to the increased conduction loss. Thermal management needs

B. Output Capacitance Loss
In addition to R DS,ON , GaN HEMTs produce the losses generated from the output capacitance (C OSS ). The C OSS loss is generated when the equivalent output capacitance of the OFF-state power device is subsequently charged and discharged; this loss is equal to zero in an ideal capacitor. In GaN HEMTs, output charge versus V DS characteristics show hysteresis in large signal, dynamic double sweep, producing power loss in a cycle of charging and discharging. This C OSS loss issue first gained attention in Si superjunction devices [101], [102] and recently in GaN HEMTs. Fig. 7 shows a comprehensive comparison of C OSS losses reported in various types of GaN HEMTs as compared with some Si and SiC devices [103], [104], [105], [106], [107]. GaN HEMTs are experiencing considerable C OSS losses, e.g., larger than 20% of the total C OSS stored energy (E OSS ) at the frequencies above 20 MHz, which is rarely observed in other types of power devices. From the system viewpoints, this loss starts to become a significant portion of the device total loss in high-frequency (>MHz) soft-switching applications [103]. In HSW or low-frequency applications, this loss is typically much lower than the other device losses (e.g., I-V overlap loss). It can induce an unexpected junction temperature climb-up [104], [108] and significantly impair the system efficiency [98], [109].
Several approaches have been utilized to characterize the C OSS loss, which are summarized in Table VI. In general, researchers attempted to quantify this loss by using either the calorimetric (thermal) method [108] or the electrical methods, including the Sawyer-Tower method, nonlinear resonance method, and unclamped inductive switching (UIS) method [104], [110], [111].
All these methodologies have advantages and limitations. For example, in the calorimetric approach, the device under test (DUT) is placed in parallel with an active switch; the DUT is turned OFF all the time with the V DS set by the active switch, and the DUTs C OSS loss is derived from its T J change. This method allows for measuring the device C OSS loss in working soft-switched converters without frequency limitation. In this method, however, the system calibration could be laborious and the separation of device C OSS losses from other losses could be challenging and time-consuming. Also, the accuracy of the calorimetric measurement can be lesser at low power levels.
By contrast, the implementation of an electrical method and the relevant data processing is usually simpler. The Sawyer-Tower method relies on a network consisting of the DUT, a reference capacitor, and a power amplifier that generates the sinusoidal excitation. The DUT is always OFF; its large-signal charge-voltage waveforms can be obtained from the network's input voltage (v IN ) and the capacitor voltage (v REF ), followed by the C OSS loss extraction from the hysteresis of charge-voltage waveforms. In the nonlinear resonance and UIS methods, the DUT operates in both ON and OFF states. In its OFF-state, a resonance is produced between the load inductor and the DUTs C OSS ; the C OSS loss is extracted by analyzing the loss in this resonance process based on the DUTs V DS or I DS waveforms. Despite the simpler setup, the accuracy of these electrical approaches may be compromised due to the variability and noise of waveforms and equipment, e.g., limited probe bandwidth, probe delays, and waveform distortion at high frequencies [113], [114]. In addition to the tradeoff between thermal and electrical approaches, the Calorimetric and Sawyer-Tower methods only involve the device OFF-state, which disallows for the study of the impact of ON-state current on C OSS loss. All these tradeoffs need to be considered when interpreting the C OSS loss data from various methods.
Finally, the origin of C OSS loss in GaN HEMTs is still contentious [108], [112], [115], [116], while a consensus is reached that the carrier trapping/detrapping induced C OSS hysteresis is a key root cause. However, the location, time constant, energy level, and physical origins of the relevant traps remain unclear [112]. The leakage current in the epitaxial structure [108] and the resonance on the Si substrate [116] have been reported to contribute to the C OSS loss. With the origin of C OSS loss remaining not fully clear, there have been relatively few reports on its reduction strategies. An experimental work has shown that the C OSS losses can be reduced by re-engineering the GaN HEMT architecture and epitaxial stack [108].
From the application viewpoint, the C OSS loss significantly impacts the device selection for high-and very high frequency power converters [105]. In parallel to understanding its origin and mitigation from device perspectives, an immediate need for applications is to provide such information in the device datasheet and the relevant models in the device application note. To facilitate this to happen soon, a widely accepted characterization method is preferable, which should ideally involve the device ON-and OFF-states and best represents the device's steady-state switching in converters [111], [112].

C. Dynamic Threshold Voltage in SP-HEMT
Bias-temperature V TH instability has been a crucial research topic of Si and SiC MOSFETs for decades. It was also studied for GaN HEMTs with various gate architectures. Early studies focused on GaN metal-insulator-semiconductor (MIS) HEMTs. The V TH instability in MIS-HEMTs is due to the trapping at the insulator/GaN interface or in the bulk dielectric, which are similar to Si and SiC MOSFETs. A thorough review of the V TH instability in GaN MIS-HEMTs is provided in [117].
In recent years, as p-gate gradually becomes the prevailing E-mode GaN technology, the research focus shifts to commercial p-gate HEMTs [87], [118], [119], [120], [121], [122], [123]. Unlike the V TH instability in MOSFETs and MIS-HEMTs, the dynamic V TH is an intrinsic property related to the floating p-GaN layer in SP-HEMT. As shown in Fig. 4, the SP-HEMT gate stack consists of a p-GaN Schottky junction back-to-back series connected with a p-GaN/AlGaN/GaN p-n junction. As the bias condition (forward or reverse) of these two junctions is opposite, the charges in the p-GaN layer cannot be effectively supplied or extracted in fast switching, making a "floating" p-GaN layer.
Latest progress in the V TH instability studies for SP-HEMTs is reviewed in [124]. The charge storage process in p-GaN usually leads to a positive dynamic V TH shift [120]. This V TH shift increases with the OFF-state blocking voltage and the switching frequency [122]. It is worth mentioning that the GIT features an Ohmic contact on p-GaN, allowing for effective charge supply/extraction and thereby a stable V TH .
In addition to the floating p-GaN, trapping may also contribute to the dynamic V TH . Under a forward V GS , a V TH shift can be impacted by two trapping mechanisms [125], [126], [127]. The first mechanism is hole trapping and recoverable, which creates a negative V TH shift. The second mechanism is electron trapping and slow in recovery, causing a positive V TH shift [125], [127].
The dynamic V TH shift could considerably impact the device switching operations [124]. With a positive shift, the reverse conduction voltage of SP-HEMT increases, leading to higher power loss. The dynamic V TH will primarily impact the turn-ON loss of SP-HEMTs [43]. It also demands a sufficiently high gate-drive voltage to fully turn-ON the device, which reduces the safety margin for the gate reliability. Hence, circuit simulations should consider the dynamic V TH to depict the practical circuit characteristics. Recently, a SPICE model with dynamic V TH is developed [121] and used to analyze the switching transients in a phase-leg circuit [128].

D. Other Issues Associated With Composite Devices
Since composite devices are combinations of multiple chips, they may face instability issues not only on GaN HEMTs but also associated with the interconnection between Si devices and GaN HEMTs. For example, some instability issues have been reported in cascode GaN HEMTs. During high-current, turn-OFF conditions, a divergent oscillation can occur because of the capacitance mismatch between the GaN and Si switches [129]. Additionally, the added inductance to the bond wires between the switches and the Si avalanche can also cause an increase in the internal switching losses [130]. To minimize the interconnection induced loss, the latest generation of commercial cascode GaN HEMTs eliminates the internal bond wires between the two chips by directly stacking the Si chip onto the source pad of GaN HEMT [22]. However, in some extreme instances, false turn-ON events can occur [131], and SC oscillations can cause catastrophic failures [132]. On the other hand, the gate instability is usually not an issue in the cascode GaN HEMT or direct-drive device because an Si MOSFET is primarily driving the device or additional protection circuits are copackaged with the GaN HEMT.

VI. ROBUSTNESS
A critical robustness requirement of power devices in many applications, such as motor drives, automotive powertrains, and electric grids, is the capability of withstanding overvoltage, overcurrent, and surge-energy events before the protection circuitry intervenes. The robustness is usually characterized by UIS (i.e., avalanche) and SC tests for Si and SiC power transistors. GaN HEMTs are known to possess limited SC robustness and no avalanche capabilities. Moreover, under some out-of-SOA conditions, GaN HEMTs withstand the stress or degrade/fail very differently as compared with Si and SiC devices. This section will present the SC, surge energy, and overvoltage robustness of GaN HEMTs. Note that the gate robustness is also very relevant to p-gate GaN HEMTs. Due to its close correlation with the gate lifetime, we will discuss it in Section VII.

A. SC Robustness
SC fault events occur when a conduction path with minimum impedance is present between the switching transistor and the power supply. The SC events usually drive devices into the saturation mode of operation, with both a high voltage and a high conduction current stressing the device [133]. A typical SC robustness requirement is the 10 μs SC withstanding time (t SC ) under the bus voltage (V BUS ) and driving conditions identical to the application-use operation [134]. If the 10 μs t SC is unattainable, according to the U.S. Department of Energy 2025 Vehicle Drive Roadmap [135], a 2 μs t SC of the power device together with the ultrafast protection circuit is needed. There are generally four types of SC conditions that can happen in a power electronics system: the arm SC, which is also called the hard-switching fault (HSF) or SC type I, the series arm SC, the output SC, and the ground SC [136], [137]. Among these conditions, HSF is usually employed for the evaluation of the power device SC robustness [134]. This section summarizes the single-event t SC , failure mechanisms, and repetitive SC test results recently reported for GaN HEMTs.
From the application viewpoint, it is critical to measure the SC capability under the application-use driving conditions (e.g., the same driving circuitry and voltage). Table VII summarizes the reported t SC of various GaN HEMTs under the driving condition similar to their normal operation [138], [139], [140], [141], [142], [143], [144], [145], [146], [147], [148]. Note that the t SC variation seen in some articles is believed to be due to distinct driver conditions. For example, a large gate resistor (R G ) is used in [149] and [150], leading to long t SC . The large R G slows down the device turn-ON, resulting in a smaller peak SC current. Additionally, the device gate-leakage current increases in the SC withstanding process due to the temperature elevation.
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The leakage current across the large R G could make the device V GS significantly lower than the usual operation [151], leading to even lower SC current and a thermal stress much lower than practical SC scenarios.
The reported t SC for 650 V SP-HEMTs is generally below 1 μs at V BUS higher than 350 V [133], [139], [140], [150], [151], [152]. For HD-GITs, an RC driving circuit is employed with a large R G (100+ Ω) to minimize the quiescent gate current [141]. This suppresses the device V GS under the SC stress, leading to a fast I D drop and a t SC >10 μs at V BUS below 350 V [141], [153], [154]. However, similar to SP-HEMTs, the t SC drops drastically to < 1 μs at V BUS > 350 V [141], [151], [153]. Cascode devices also show limited SC robustness. As the cascode gate is the Si MOS, the t SC is not sensitive to R G [143], [151]. Very few SC reports are available on direct-drive device. Song et al. [24] report the SC tests of a 650 V, 100 A direct-drive GaN HEMT, which is intentionally stopped in 100 ns. The device can withstand an SC current up to 358 A within this SC duration.
Extensive efforts have been made to understand the limiting mechanism of the SC capability in GaN HEMTs, particularly at high V BUS . In long SC duration tests with a low V BUS [141], [150], devices fail thermally. At high V BUS , many reports converge on the electrical failure. In [147], it is proposed that the SC failure could be caused by the high electric field induced by the hole accumulation underneath the gate in which the holes are generated from impact ionization. Castellazzi et al. [141] also report the correlation between the SC-induced high carrier density and electric field crowding at the drain-side gate edge. A gate-drain region failure in the SC condition is also reported in [143]. In [148], a wafer-level transient voltage measurement is used to monitor the potential profile in the gate-drain region under the SC stress. The failure is revealed to depend on the electric field propagation speed; when high electric field reaches the drain edge, impact ionization induces the failure.
Within the single-event SC SOA, the insufficient robustness of GaN HEMTs in repetitive SC stresses has been reported. In [133], the SP-HEMT fails after seven 1.2 μs SC pulses at 300 V. At lower V BUS , the repetitive SC stresses lead to an increase in R DS,ON and decrease in I DSS [133], [140], [149]. These parametric shifts are all evidences toward electron trapping in the buffer and gate regions during the repetitive SC operation. The repetitive SC tests on HD-GITs are reported in [141] and [155]. Under this stress, the evolution of crack formation and aluminum extrusion has been observed [155].
For the cascode HEMT, two additional mechanisms have been revealed to limit its SC robustness. First, the parasitics of the Si-GaN chip interconnection can excite the self-sustained gate oscillation in the SC condition, leading to the GaN HEMT false turn-ON and failure [132], [144]; second, the cascode HEMT has a lower thermal self-regulation capability on the gate control as compared with HD-GITs and SP-HEMTs [151].
From the application viewpoint, the short t SC of current GaN HEMTs requires the incorporation of protection circuits for applications where the SC fault could occur. The protection circuit should detect the fault and clear it within  ns. This is difficult to achieve by conventional desaturation circuits due to their long response time [156] and the false protection drawn by the high dv/dt [157]. Recently, ultrafast SC protection circuits for GaN HEMTs have been demonstrated by multiple groups [157], [158], [159], [160], [161]. The fault detection and clearance time demonstrated by these circuits are generally below 100 ns. Additional desirable features have also been presented, such as strong dv/dt noise immunity [157], applicability to the parallelconnected GaN HEMTs [159], and monolithic integration with the GaN device [161]. In addition to fast protection, other circuit approaches are also proposed, such as connecting the GaN HEMT with an Si MOSFET [162], to enhance the SC capability.
Finally, besides circuit approaches, device-level innovations have been reported to improve the t SC of GaN devices. A straightforward approach is to reduce the saturation current (and the associated electric field crowding under the SC condition) by removing segments of the 2DEG channel along the width of GaN HEMT [145], [163]. This approach enables a t SC over 3 μs in industrial cascode GaN HEMTs. A more significant improvement is demonstrated in 600-700 V vertical GaN FETs, with a t SC over 30 μs at 400 V [146], [164], [165]. This vertical GaN FET will be elaborated in Section VIII.

B. Surge Energy and Overvoltage Robustness
In addition to SC robustness, the ruggedness against surge energy is highly desirable for power devices [166], [167], [168]. Historically, the surge-energy robustness of Si/SiC MOSFETs and IGBTs relies on their avalanche capability, an impact ionization and multiplication phenomenon that allows the device to accommodate high current at high V DS (i.e., avalanche breakdown voltage, BV AVA ). As shown in Fig. 8, when devices are subject to surge energy, V DS rapidly ramps to and clamps at BV AVA . The drain current (I D ) drops to zero, accompanied by resistive dissipation of the surge energy via avalanching in device. This energy dissipation prevents the further energy circulation in converters. Hence, the surge-energy ruggedness is often referred Fig. 9. Schematic of three overvoltage ruggedness evaluation circuits: the UIS circuit (left), the CIS circuit (middle), and the soft-switch buck converter with an ACC (right), as well as the typical waveforms in these tests.
to as avalanche ruggedness. The avalanche energy (E AVA ), the maximum energy that a power device can dissipate without triggering thermal runway, has become an important metrics for device robustness [169].
GaN HEMTs, however, do not have the intrinsic avalanche capability [30]. The JEDEC JC 70 committee has recently identified their surge-energy robustness to be a critical issue for evaluation [6]. When GaN HEMTs are subject to surge energy, they show a swift increase in V DS (see Fig. 8) as the result of the resonance between their C OSS and the parasitic inductance of the circuit [169], [170]. This withstanding process cannot dissipate energy until the resonance voltage becomes negative, leading to the reverse turn-ON of GaN HEMTs. In the withstand process, the primary electrical failure is related to the overvoltage margin of the device, i.e., the dynamic breakdown voltage [41]. This BV in the transient switching could be different from the static BV measured through the quasi-static I-V sweep on the curve tracer [22], [41], [171], [172].
The above discussion manifests the convergence of surgeenergy robustness and overvoltage robustness for GaN HEMTs. In general, GaN HEMTs designed with a higher dynamic BV and larger C OSS can withstand a larger surge energy at the price of the compromised switching speed [169]. This tradeoff can be considered when designing and selecting any nonavalanche power device for various applications. In the remaining part of this session, we will discuss the characterization methods of dynamic BV and overvoltage ruggedness, the characterization results, and implications for GaN applications.
1) Characterization Methods: To date, three methods have been developed to characterize the overvoltage ruggedness and dynamic BV for GaN HEMTs, i.e., the UIS circuit, the clamped inductive switching (CIS) circuit [169], and the active clamping circuit (ACC) [172], [173]. The schematic and typical waveforms of these three circuits are illustrated in Fig. 9.
The UIS test is also an effective method to characterize the dynamic BV of a nonavalanche power device, such as GaN HEMT [41]. By tuning the load inductance, the dynamic BV of a 650 V rated GaN HEMT under various pulsewidth (and dv/dt) and temperatures is shown in Fig. 10(a). The dynamic BV (up to 1400 V) is significantly higher than the static BV (950 V) [41]. This suggests a higher overvoltage margin of GaN HEMTs in switching. These dependences of the dynamic BV can be explained by the trapping dynamics and the resulted change of the peak electric field magnitude in GaN HEMTs [41].
Differently, the cascode device shows a dynamic BV lower than the static BV in the UIS test [22], suggesting an inferior overvoltage ruggedness in switching. The 650 V rated cascode devices exhibit a dynamic BV (1.4-1.7 kV) lower than the static BV (1.8-2.2 kV); the dynamic BV also shows a strong frequency dependence, dropping from >1.4 kV at 1 kHz to 1.25 kV at 100 kHz [22]. These phenomena are explained by the GaN trapping affected by the Si MOSFET avalanche [22].
Despite the simplicity, the UIS test differs from many converter operations due to a relatively low V BUS and the absence of the overlap between high current and high voltage. To address these limitations, the CIS circuit is proposed with a high V BUS and a controlled "parasitic" inductance to create voltage overshoot in the HSW turn-OFF process [169], as illustrated in Fig. 9(b). This CIS test has been applied to SP-HEMTs [169], [171], [188] and HD-GITs [169], [188], [189]. The CIS tests with varying stressors (dv/dt, ambient temperature) show a failure overvoltage boundary consistent with the UIS tests under the same conditions. A limitation of UIS and CIS circuits is the difficulty of evaluating the device's overvoltage ruggedness in very high frequency switching. To address this limitation, a soft-switching buck converter with an ACC is developed in [172] and [173], as shown in Fig. 9(c), which allows for the continuous kilovolt overvoltage switching at a frequency up to 1 MHz. This test is applied to SP-HEMTs and HD-GITs from different vendors to study the failure boundary and ruggedness. Most devices show a consistent overvoltage failure boundary (i.e., dynamic BV) with the UIS/CIS measurements up to MHz [173].

2) Overvoltage/Surge Robustness and Application Insights:
The studies on the overvoltage ruggedness of GaN HEMTs in continuous switching started from the repetitive UIS tests, as reported by multiple groups. For HD-GITs, the earlier generation devices showed some level of parametric shifts in I DSS and output characteristics [178], [183], while these shifts were not reported in newer generation devices [41]. SP-HEMTs have been reported to show a negative, recoverable shift in I DSS due to buffer trapping [41], [178], [181], [182], [186]. Cascode devices show recoverable shifts in R DS,ON , I DSS , and junction capacitances after repetitive UIS tests [22], [23].
More recently, CIS circuits have been used as an advanced tool to study the GaN HEMTs ruggedness in overvoltage HSW. SP-HEMTs, HD-GITs, and MIS-HEMTs (used in direct-drive devices) have been reported to survive the repetitive overvoltage HSW with an overvoltage up to 90% of the dynamic BV [171], [189], [190]. However, different devices exhibit significant distinction in the magnitude of parametric shifts and their recovery speed.
Despite the distinction, a common cause of these shifts is the trapping of the holes generated in the impact ionization during the overvoltage switching, as shown in Fig. 10(b). This process is related to the breakdown mechanism of GaN HEMTs [30], [191]. When V DS approaches the dynamic BV, peak electric field is usually present near the drain or below the edge of source field plate, initiating the impact ionization. While the generated electrons are removed through the drain, the generated holes flow toward the gate and substrate [171]. The hole trapping or hole accumulation can produce parametric shifts, electric field crowding, and destructive breakdown.
A comprehensive study of overvoltage HSW up to the 90% dynamic BV for various GaN HEMTs is presented in [26]. Fig. 10(c) shows the evolution of parametric shifts with the increased CIS switching cycle, revealing a saturation and stabilization in all devices. These parametric shifts are all recoverable but require different techniques for various devices, as the device's poststress recovery is dominated by the hole detrapping and removal. The HD-GIT shows a fast natural recovery. The through-gate hole removal in SP-HEMT can be accelerated by negative gate bias and high temperatures. The MIS-HEMT can be recovered by applying positive gate and substrate biases, which make holes recombine in the 2DEG channel. These results suggest, despite the lack of avalanche in GaN HEMTs, the impact ionization places an important role in determining their ruggedness in overvoltage switching [26].
When the frequency of overvoltage switching is higher (e.g., >100 kHz), two premature failures have been reported for some SP-HEMTs, leading to failures at the voltage level much lower than the dynamic BV [173]. One failure features a drastic, nearly unrecoverable R DS,ON increase, leading to conduction loss ramp-up and thermal failure. The other failure exhibits an increase in I DSS and a catastrophic breakdown at lower voltage. These two premature failure mechanisms are both due to the severe trapping occurred in the GaN HEMT at very high frequency. To screen the devices suffering from these extrinsic failures, high-frequency continuous UIS tests can be used as an effective method [173].
The above results provide several implications for GaN applications. First, for applications that require the device to withstand single-event or repetitive surge energy, selection of GaN devices with high overvoltage margin (dynamic BV) and large C OSS is essential. With sufficient overvoltage margin and C OSS , the surge energy that GaN HEMTs can withstand could be similar to the avalanche energy rating of Si and SiC devices. Second, for normal operations, GaN HEMTs are quite robust against the transient overvoltage and oscillation beyond their voltage rating. However, for some devices, continuous voltage overshoot at high frequency could be detrimental. In this case, overvoltage suppression circuits that do not sacrifice the device fast switching capability could be needed, similar to those developed for SiC devices [192], [193]. For example, an ultrafast self-powered voltage overshoot suppression circuit is recently demonstrated for GaN HEMTs in solid-state circuit breaker applications [194]. One factor to consider when designing such circuit is the dependence of GaN overvoltage ruggedness on frequency, as the trap accumulation is affected more by frequency than the switching speed or slew rate.
Another need relevant to applications is on providing the transient voltage rating for GaN HEMTs. As shown in Table II, the transient voltage rating and the relevant acceleration model are only available from one GaN device vendor. On the other hand, a large variation in overvoltage margin is seen from GaN devices (e.g., a dynamic BV ranging from ∼1 to ∼2 kV for 650 V GaN devices from various vendors). Since such transient voltage rating could be frequency and temperature dependent, a unified test method and standard as well as the associated lifetime model are highly desirable.

VII. SWITCHING LIFETIME
For Si devices, some well-known standards, such as JEDEC JESD47, have been utilized for decades to provide guidelines for lifetime extraction. This approach is based on understanding of the failure modes of Si devices, as well as statistical calculations to assure the accuracy with limited samples. These traditional qualification tests, however, do not consider the switching conditions of power devices. Most of the test specified in JEDEC only utilizes static, high-voltage biases, and high temperatures. For GaN devices, due to the diverse failure modes, it is an open question on the viability of using static stress tests to evaluate the device lifetime. Many recent works are exploring the evaluation of GaN device lifetime under the application-use switching condition. This section presents such efforts in probing the gate lifetime, drain switching lifetime, and the device switching lifetime under mission profiles.

A. Gate Lifetime
Conventional Si and SiC power transistors (e.g., IGBTs and MOSFETs) usually comprise a MOS gate, and the gate lifetime is limited by the oxide reliability. The MOS reliability and lifetime are usually characterized by the HTGB test or the time-dependent dielectric breakdown (TDDB) test, which can follow the JEDEC JESD92 standard [195]. The gate oxides in Si and SiC devices have been conformed to show sufficient intrinsic lifetime at high temperatures [196]. Recent efforts on SiC gate lifetime study center on the lifetime testing and modeling for extrinsic failures [196], [197], [198], [199].
For commercial D-mode GaN MIS-HEMTs used in directdrive and cascode devices, very few gate lifetime studies have been reported except for the good HTGB qualification data from vendors. Most publications of MIS-HEMTs are based on research devices with nitride dielectrics [200], [201], [202], [203] or Al 2 O 3 [204] as the gate insulator [205]. The gate failure in most of these MIS-HEMTs shows the TDDB behavior [206], [207], [208]. A 20 years lifetime (100 pm, 130°C) extrapolation is reported for a 0.2 mm 2 gate area at positive gate voltage of 9.4 V [200].
Recently, gate lifetime studies gradually centered around the SP-HEMT, as it has become a common device platform in many foundries. A critical issue in the SP-HEMT driver design is to suppress the V GS overshoot induced by the parasitic gate-loop inductance or commutation crosstalk, as the margin between the typical drive voltage and the maximum allowable voltage of SP-HEMT can be as low as 1 V [209]. Moreover, as explained in Section IV-C, the Schottky-type p-gate is not fully insulating but comprises a floating p-GaN layer.
Several methods similar to those presented in Table III have been used to study the gate lifetime of SP-HEMTs. The dc tests with a constant-voltage stress or step-voltage stress have been widely employed [210], [211], [212], [213], [214], [215], [216], [217]. Fig. 11(a) and (b) shows the evolution of I GSS of a commercial SP-HEMT in a step-stress test until failure, revealing a TDDB behavior [45]. As shown in Fig. 11(c), the time to fail (t BD ) data at a certain V GS could be fitted by Weibull distribution (F is the cumulative probability function), and the shape parameter (β) higher than 1 indicates the wear-out failure. As shown in Fig. 11(d), the Weibull distributions can extract t BD at each V GS for a given failure rate, and the t BD -V GS relation is further fitted by a power law from which the maximum allowable V GS for a ten-year lifetime can be extrapolated for the failure rate of 63% and 0.1%. Another recent work found that the time-to-fail data from dc tests show an exponential dependency on 1/I G and follow a LogNormal rather than a Weibull distribution [218].
Recently, the square-wave pulse I-V test was used to study the gate breakdown and reliability [45], [219], [220], [221]. The I G evolution data similar to those in dc tests can be obtained from pulse I-V tests for lifetime extraction. Diverse dependencies of the gate lifetime in pulse I-V tests have been reported in the literature. The effective gate lifetime (i.e., the product of duty cycle and total lifetime) is reported to increase at higher temperatures and be weakly dependent on frequency from dc to 100 kHz [45]. In comparison, Millesimo et al. [220], [222] report that the effective gate lifetime decreases at increased frequency and duty cycle, when the frequency reaches 1 MHz. This is explained by the difficulties for the electrostatics in p-GaN to keep up with the V GS switching at high frequency.
These diverse dependencies suggest the strong impact of switching schemes on the SP-HEMT gate lifetime. This may lead to the inapplicability of the gate lifetime obtained from dc tests to device operations in power converters. Recently, a circuit method is proposed to evaluate the gate lifetime under the inductive load switching [223], the condition of which is not accessible by dc or pulse I-V methods. As the parasitic-induced gate overshoot has a resonance nature, this method features a resonance-like gate ringing with the pulsewidth down to 20 ns and an inductive switching concurrently in the drain-source loop. Fig. 12(a) shows the circuit schematic, and Fig. 12(b) shows the produced V GS overshoot in the HSW. As shown in Fig. 12(c), the single-pulse failure boundary, i.e., the dynamic gate breakdown voltage, is found to be strongly affected by the drain-source switching locus, e.g., HSW and drain-source grounded (DSG), pulsewidth, and temperature. These dependences are not observed in the MOS-type gates in the Si IGBT and SiC MOSFET. In addition to failure boundary, the application of this method to characterize the gate's switching lifetime is desirable. Finally, from the various reports on the time-dependent breakdown of SP-HEMT [39], [125], [211], [212], [213], [215], [216], [224], [225], [226], [227], [228], the failure mechanism remains contentious [228]. While all reports show the failure of devices with an increase in gate-leakage current, some reports claim that the failure is caused by the high electric field in the metal/p-GaN Schottky junction or AlGaN barrier layer [126], [210], [224], [227], while others have credited the failure to the generation of a percolation pathway [211], [212], [213], [215], [226], [229]. The positive temperature coefficient of the failure boundary in a commercial SP-HEMT [45] disagrees with the classic percolation-induced TDDB theory; instead, it is explained by the impact ionization in p-GaN and the resulted degradation of the Schottky contact on p-GaN [45].
Overall, the SP-HEMT gate stack architecture appears to have lifetime concerns, particularly in fast switching. Further investigations are ongoing to provide new gate architectures at the device level [216], [224], and driver techniques at the circuit level [46], [230], [231].

B. Switching-Oriented Lifetime Extraction
The importance of employing switching circuits to extract the GaN HEMT lifetime holds not only for the gate but also for the drain-source loop. For the conventional Si transistors, HTRB tests at multiple drain biases between the rated voltage and BV AVA are widely used for lifetime extraction, as voltage is a major lifetime accelerator. However, due to the distinct and complex breakdown mechanisms in GaN HEMTs, the viability of the HTRB-based lifetime extraction is questionable.
Recent efforts have explored the lifetime evaluation of GaN HEMTs based on the application-use switching conditions that involve both HSW and soft-switching stresses throughout the converter operation [168], [232]. Some of these efforts reported by device vendors are summarized in Table II. In addition, a generalized approach to determine the switching lifetime of a GaN HEMT is presented in [232]. Similar to the overvoltage stress tests, some of these experiments utilize the CIS circuit with the HSW turn-ON stresses instead of turn-OFF stresses. The I-V switching locus, as shown in Fig. 13(a) [232], utilizes the HSW turn-ON event in a CIS circuit to match that seen in a boost converter application. Through repetitive cycling under these switching events until failure, a lifetime plot is created. These results are then compared with application lifetime tests as well as the simulated lifetime metrics, which are extracted through calculations utilizing the switching energy as the primary parameter. Fig. 13(b) shows how this generalized testbed and switching energy focused method have been used to baseline the lifetime of GaN devices in varying applications [232]. The acceleration models for four representative stressors, i.e., V DS , channel current (I Ch ), temperature, and frequency, are illustrated in Fig. 13(c).

C. Mission-Profile Lifetime Considerations
The mission-profile-based model for electronic system lifetime extraction has seen evolutions recently. For example, the hybrid electric vehicle (HEV)/electric vehicle (EV) onboard chargers require more than 30 000 h lifetime, which is 3-4 times higher than the traditional internal combustion engines. Some other pulsed power application, such as medical equipment, will charge and discharge the load with power cycle in the range of millisecond [233]. Once the failure mechanism is identified, system-level solution to extract the lifetime can be deployed [234].
The mission-profile-based lifetime extraction usually suggests the need for considering more system-level variables, which could be more complex than the device-level reliability and robustness. From industry standpoint, such system-level variables typically include the packaging, system integration, harmonics, and electromagnetic interference (EMI).
The reliability issues associated with the package of GaN devices are strengthened by the diverse packages required to accommodate various chip footprints [235]. Si devices manufactured by different vendors now have standard footprint for the user to pick up from. However, for GaN devices, the footprint still varies between different vendors, which creates inconvenience for the end user and also not secure supply from procurement standpoint. Because of this packaging variety, reliability for each new packaging needs extra evaluation from vendors.
To accelerate the adoption of advanced GaN devices, the integrated function of gate driver built-in protection can be essential. The desirable system-level protection includes the overcurrent, overtemperature, and undervoltage lockout. Low-inductance design is also essential through system-level integration, which will minimize the nonideal symptoms, such as ringing and voltage overshoot [236]. Finally, the gate charge of GaN devices is much lower than Si devices. The enhanced dv/dt and di/dt in GaN device operations will inevitably create more system-level harmonics and EMI issues and, thus, desire novel and practical EMI solutions. The impact of EMI and harmonics on GaN device reliability and lifetime is still unclear.

VIII. EMERGING VERTICAL GAN DEVICE
Vertical GaN devices are regarded as candidates to expand GaNs application space into the medium-voltage range [5], [13], [20], [21], [237]. In this section, we introduce the latest reliability and robustness results of industrial vertical GaN devices, as they demonstrated breakthrough avalanche and SC capabilities. Additionally, vertical devices are less prone to surface traps, as the peak electric field is usually located inside the GaN layers. Until now, several multikilovolt vertical GaN diodes and 1.2-2 kV vertical GaN transistors have been reported, with architectures including p-n diode [238], Schottky barrier diode (SBD) [239], junction barrier Schottky diode [240], currentaperture vertical electron transistor [241], trench MOSFET [242], fin-channel MOSFET [243], and fin-channel JFET [244]. The fin-shaped vertical channel can enable a high channel density and, thus, a low channel resistance, at the same time enabling the E-mode operation [12], [13].
Despite still under active development, vertical GaN devices have shown to pass multiple traditional reliability qualification experiments, such as HTRB, HTOL, temperature humidity bias, and temperature cycling [245]. In these experiments, the fundamental failure mechanisms can usually trace back to the quality of the substrate and epitaxy material. Substrate orientation, surface preparation, and epi growth initiation are found to be critical in the device performance and reliability [21], [245]. As the bulk GaN substrates to date remains a higher dislocation density than Si or SiC, it can be expected that the device reliability will be further improved as the substrate and epitaxial growth technologies mature. Gate stability studies of vertical GaN transistors have also been reported, e.g., the evaluation of GaN fin MOSFET under positive gate step stress [246] and GaN trench MOSFETs under drain step stress [247].
Recent studies have also demonstrated superior switching stability of vertical GaN devices. With less surface-trapping effect as well as good crystalline quality, vertical GaN devices are less susceptible (or even free) to D-R DS,ON issues; this has been experimentally verified in a 600-V rated SBD by the DPT method [239]. Minimal R DS,ON change has been observed under various switching conditions, including OFF-state stress bias up to 500 V, OFF-state stress time within 10 −6 to10 2 s, high temperature up to 150°C, and different load current levels.
The GaN p-n junction is a critical building block for many vertical GaN power diodes and transistors. The overcurrent and overvoltage ruggedness of industrial vertical GaN p-n diodes are comprehensively reported in [248] and [249]. GaN p-n diodes show a critical surge current of 54 A (over tenfold higher than the rated current) and a critical surge-energy density of 180 J/cm 2 in 10-ms surge current tests, with the surge-energy density being comparable with SiC devices [248]. Note that the associated device physics is different in GaN and Si pn junctions. With little conductivity modulation in GaN p-n junctions, the good surge current capability is attributed to the increased acceptor ionization in p-GaN at high temperatures [248]. This suggests a high overcurrent robustness of GaN p-n junctions with small bipolar current and fast switching capabilities.
In addition to surge robustness, the industrial GaN p-n diodes also demonstrate strong avalanche capabilities with BV AVA up to 2 kV, maximum avalanche current (I AVA ) up to 61 A, and a critical avalanche energy density of 7.6 J/cm 2 (comparable with SiC p-n junctions) [248], [249]. Note that the main-junction avalanche may be shielded in the static I-V sweep by a trap filling process at the edge termination; therefore, it is necessary to characterize the avalanche capability in GaN devices in the UIS circuit tests [249].
For transistors, the industrial vertical GaN Fin-JFETs [see Fig. 14(a)] recently demonstrated a specific R ON of 0.82 mΩ · cm 2 , a V TH of 2 V, a BV AVA with positive temperature coefficient [see Fig. 14(b)], a ∼10 ns switching time in 600-V/4-A DPT, and good thermal stability up to 200°C [244], [250]. Moreover, vertical GaN FinFET shows textbook-like avalanche waveforms in the UIS tests, being the first avalanche-capable GaN power transistor [244], [250]. The critical energy density is up to 10 J/cm 2 , which is comparable with SiC devices and much higher than Si devices [251].
The natural I AVA path in vertical GaN Fin-JFETs is through the gate p-n junction, which may require extra protection circuitry in the gate driver. It is recently shown that I AVA in GaN Fin-JFETs can be tuned to flow through the source, by using an RC-interface driver, which turns ON the fin channel during the avalanche [see Fig. 14(c)] [252]. Under this condition, the major avalanche current path migrates from the gate p-n junction to the n-GaN fin channel, producing an interesting "avalanche through fin" process [252].
Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.  In addition to avalanche capabilities, GaN fin JFETs also exhibited the significantly enhanced SC robustness. Zhang et al. [146] present the SC characterization of a 650 V GaN fin JFET, revealing a t SC of 30.5 μs at 400 V V BUS [see Fig. 15(a)], 17.0 μs at 600 V, and 11.6 μs at 800 V (i.e., the BV AVA ). To date, these t SC are the longest reported in 600-700 V E-mode unipolar power transistors [see Fig. 15(b)]. Additionally, GaN fin JFETs fail with an open-circuit signature in SC tests, exhibiting a retained BV AVA . This failure signature is highly desirable for system applications. In contrast, most of the other transistors are reported to fail short under the SC stress. GaN fin JFETs are also reported to be robust in repetitive 10 μs, 400 V SC tests [146] and even up to V BUS of 600 V [164], the V BUS close to its rated voltage.
The underlying device physics that enables an SC capability at BV AVA is also found to be the "avalanche through fin," as illustrated in Fig. 15(c) [165]. In this condition, the thermal (I AVA ) stress is mainly located at the fin channel, which is separated from the main blocking junction below the p-GaN gate that supports BV AVA . Hence, when device fails thermally, the BV AVA usually retains, enabling the open-circuit failure signature. This reflects the overall robustness of GaN fin JFETs under the concurrence of overvoltage and overcurrent.

IX. RADIATION ROBUSTNESS
The use of GaN devices is attractive in space, aeronautical, and defense applications, where system weight is at a premium. Devices for these applications must demonstrate tolerance to high doses of radiation exposure. While GaN as a material is inherently radiation hardened due to a high displacement threshold energy (the energy required to create a displacement in the lattice of the material) and ionization threshold energy (the mean energy required by a high energy particle to create an electron-hole pair), radiation hardness of GaN devices depends upon the device design and material quality [253]. The physics and outcomes of radiation damage in lateral GaN HEMTs differ from those in traditional vertical Si and SiC FETs.
Device-level radiation effects can be grouped into three categories: total ionizing dose (TID), displacement damage, and single-event effects (SEEs). These effects, and their relation to local physical processes in GaN HEMTs, are outlined in Fig. 16(a). TID effects are induced by the deposition of energy by ionizing radiation due to either photons (X-rays) or ions, while displacement damage effects are due to the displacement of atoms in the irradiated device due to energy transfer. SEEs are due to the transient response of the device to the ionization induced during an instantaneous strike by a radiation particle. Both TID and displacement damage induce changes in the device, which are a function of the total dose of radiation absorbed, while SEE are transient events that may induce instantaneous device degradation or failure. SEEs, in particular, are of primary concern in power devices due to the potential for failed devices to induce unrecoverable HSFs in converter circuits [254]. The state of research into these effects in E-mode GaN HEMTs is discussed in the following text.

A. Total Ionizing Dose
Due to the lack of gate oxide, p-gate GaN HEMTs are expected to be generally tolerant to TID effects. Recent work reveals that the TID effects in GaN HEMTs are bias dependent [255], which is also reported in SP-HEMTs and HD-GITs. SP-HEMTs show negligible V TH shift when all terminals are grounded up to a dose of 1 MRad(Si); a negative V TH shift is observed over a 1 MRad(Si) test under V DS of 80% of the rated voltage [256]. Comparison between 80 and 200 V rated devices demonstrates a larger V TH shift in the higher voltage device [257]. Little work has been found on radiation studies of composite GaN devices, but such devices are expected to be more susceptible to TID effects due to the use of an Si MOSFET with the gate oxide. As annealing is shown to reverse some of the effects of TID exposure in GaN HEMTs [255], further investigation is needed of TID effects on GaN devices under the switching conditions where self-heating may be significant.
Fewer studies have been performed on the effect of TID on the dynamic characteristics of GaN HEMTs. HD-GITs show minimal D-R DS,ON shift after exposure to 300 kRad of Co-60 exposure (1 MeV X-rays) [258]. SP-HEMTs also show minimal change after 300 kRad of 10 keV X-ray TID exposure [259].

B. Displacement Damage
Displacement damage effects in GaN HEMTs are primarily a function of the energy, mass, and charge of the irradiating particle. These effects can be quantified by the nonionizing energy loss deposited by the interaction of the radiation particle with the material of the device, which can be related to the displacement damage dose [253].
Various HD-GITs and SP-HEMTs are tested both under bias in [260] under proton and neutron irradiation to a maximum total fluence of 6 × 10 15 cm −2 . The devices, if unbiased, can survive up to maximum fluence, while failures are observed in devices biased at high OFF-state biases. Similar results are found in [257], where SP-HEMTs are exposed to total fast neutron fluence of 1 × 10 12 to 1 × 10 15 cm −2 . A reduction in I GSS is observed a function of fluence, while V TH and R DS,ON do not change as a function of exposure. In contrast, a study of a research grade SP-HEMT at high proton fluence in [261] shows a negative V TH shift and a fivefold increase in R DS,ON after irradiation with a 5 MeV proton dose of 2 × 10 15 cm −2 . These results are attributed to the creation of defects in the p-GaN gate. Interestingly, irradiation of HD-GITs with high energy protons up to a fluence of 6 × 10 14 cm −2 in [262] demonstrates a small positive V TH shift. More work is needed to understand the susceptibility mechanisms between the SP-HEMT and HD-GIT designs to radiation displacement damage effects.

C. Single-Event Effects
SEEs are transient events due to the strike of a high energy radiation particle into a device structure under bias. The creation of a large track of electron-hole pairs in devices under bias can lead to device degradation or instantaneous failure. While SEE can be important in strikes by high energy neutrons and protons, the primary cause of SEE in operational devices is due to heavy ion strikes originating from high energy cosmic rays. Primary metrics for quantifying the potential for damage from a heavy ion strike is the linear energy transfer (LET) of the ion, and the range of the ion in the structure. LET is related to the magnitude of charge generation and transfer, while the range of the ion (as a function of the device structure) will determine the susceptible areas of the device to SEE events [254]. Both device structure and bias condition influence the susceptibility of a device to SEE.
Three SEE types are important in power devices: single-event burnout (SEB), single-event gate rupture (SEGR), and singleevent transients (SETs). Due to the lack of a gate oxide in most GaN HEMT structures, SEGR is not expected to be important. Most work reviewed here follows the MIL-STD-750 Method 1080 for testing the device robustness against SEE effects: devices are biased in the OFF-state to a fraction of the rated V DS , and drain current is observed during irradiation until a failure transient is observed [263]. The V DS at which SEB is observed is denoted as V SEB and can be used to give a baseline for the SOA of the HEMT under heavy ion irradiation of a given LET. Additional device damage can occur from the effects of SETs during heavy ion exposure of HEMTs for V DS bias less than V SEB , such as increased OFF-state drain and gate leakage [264].
When a heavy ion strikes the high-field gate-drain region of an HEMT, a short can be induced between the gate and drain, which can be due to the initiation of impact ionization in the access region or dielectric passivation failure. Other SEEs include drain-to-substrate shorting and potential charge amplification effects in the GaN buffer layer. Several SP-HEMTs rated at 40 V, 100 V, and 200 V are tested in [264] under 127 I irradiation at 276 MeV at rated voltage. SEB is observed in the higher voltage rated devices with cumulative damage due to strikes leading SEB. In SEB, drain current is shown to spike to a short condition, while the gate current shows a transient than a recovery, potentially indicating failure between the drain and source rather than the gate and the drain.
In [265], HD-GIT and SP-HEMT devices are tested under variable LET, dc bias, and incident angle. As in [264], devices show increased SEE susceptibility at higher blocking bias. Interestingly, V SEB is shown to decrease for both HD-GITs and SP-HEMTs as incident ion angle is increased to 60°. Postfailure analysis shows failure points at the drain edge of the gate; and a failure mechanism is proposed [266]. Further testing of HD-GITs in [267] confirmed the angular dependence of SEE.
Postfailure analysis of these tests shows failures in devices tested at perpendicular ion incidence that induced direct damage from the drain contact to the substrate. Parallel incidence ions are shown to result in failures in which thermal failure destroyed and bridged the gate to the drain contact. A dielectric failure mode in the intermetallic region between source and drain is found in [268] for SP-HEMTs.
In comparison with SP-HEMTs and HD-GITs, testing of 650 V cascode devices showed significantly reduced V SEB , at 100 V under 48.5 MeVcm 2 /mg in [268] and 40 V under 28.5 MeVcm 2 /mg in [269]. A range of experimentally determined V SEB values found in the literature as a function of device voltage and LET of the irradiation is shown in Fig. 16(b).
Due to the dependence of V SEB on V DS (and V GS ) bias, SOAs can be established for derating of GaN HEMTs to consider SEE dependence. Several companies now offer SEE-rated components, including EPC-Space and Renesas. EPC-Space SP-HEMTs are offered with SEE SOAs up to 300 V at LET values up to 83.7 MeVcm 2 /mg [270]. However, significant questions remain unanswered about the dependence of SEE in GaN devices on device architecture, bias, and temperature, especially under switched conditions. As the susceptibility of GaN devices is a strong function of operation condition, interplay between the failure modes must be examined to determine the overall reliability of a GaN HEMT for a radiation critical application.

X. EXTREME TEMPERATURE ROBUSTNESS
Here, we define the extreme temperature range as device operation at temperatures below 0°C or above 200°C (as demarcated in Fig. 17). From an application perspective, the ability of power electronics to operate at cryogenic temperatures is desirable for weight-sensitive transport applications, such as shipping [271] and aircraft [272]. The emergence of reliable power devices that can operate at cryogenic temperature is especially important for aeronautics and space power systems where temperature extremes to below −200°C [273] can be expected over the operating life of deep space missions. For these applications, the reliability and performance studies of the integrated device-package system, rather than the device alone, are necessary. Packaging-based effects can be important at cryogenic temperatures due to thermal cycling issues and changing material properties of solder joints and die bonds [274]. This section will focus on the extrapolated intrinsic performance and reliability issues of E-mode GaN HEMTs at extreme temperatures but will examine temperature-related packaging reliability issues that have been shown to occur in the experimental literature when pertinent.

A. Cryogenic Temperature Performance and Reliability
Due to the nature of the 2DEG channel, the performance of GaN HEMTs at cryogenic and high-temperature extremes differs from that found in the traditional vertical devices in Si or SiC. Studies on the dc characteristics of E-mode GaN HEMTs demonstrate a general decrease in R DS,ON as temperature decreases [275], [276], [277]. This effect is attributed to the increase in channel mobility with decreasing temperature under both the gate and the access region. Due to the 2DEG channel making up the majority of the ON-state resistance of GaN HEMT, no carrier freeze-out effects on R DS,ON occur as temperature decreases. HD-GITs were found in [275] to have a smaller decrease in R DS,ON with temperature, which is attributed to increased trap state density and, hence, decreased channel mobility due to the recessed etch gate.
The V TH behavior as a function of temperature has been shown to differ among HD-GIT, SP-HEMT, and cascode GaN HEMT. Tests in [275] demonstrated a negative temperature coefficient for V TH down to 4.2 K for both HD-GIT and cascode devices, with a larger temperature variation found in the Cascode device due to the driving Si MOSFET. In contrast, V TH in SP-HEMTs tested in that work and, in [276] and [277], was found to have a positive temperature coefficient due to the dominance of Schottky barrier height variation with temperature on V TH level in the SP-HEMT. GaN SP-HEMT static BV was found to be relatively stable as a function of temperature down to 100 K [277]. Several studies in D-mode GaN HEMTs have shown that dynamic R DS,ON sees a strong temperature dependence upon a variety of device processing, buffer design, and surface state-related issues. Similar issues are, thus, expected in E-mode GaN HEMT designs [278], [279], [280]. A study in [281] examined the effect of cryogenic temperatures in a commercial SP-HEMT device, finding that dynamic R DS,ON measured at 400 V decreased with temperature with a similar temperature dependence as the static R DS,ON .
Dynamic switching performance of commercial SP-HEMT and HD-GIT at cryogenic temperatures was investigated in [275], [277], and [281]. Tests of the HSW performance of SP-HEMTs were examined in [277] and [281] using a DPT. The turn-ON and turn-OFF energy loss was found to decrease by 30% as temperature decreased from 298 to 133 K, with the majority of switching loss due to the turn-ON transient. Work to measure the effective soft-switching loss for SP-HEMT, HD-GIT, and cascode devices as a function of temperature was performed in [275] down to 4.2 K using the Sawyer-Tower method to measure the C OSS loss. Small temperature variations were found for one SP-HEMT and the HD-GIT device, while the tested cascode device showed a large loss increase as the temperature fell below 200 K. The distinct temperature dependence is found to be manufacturer dependent and not a function of device structure.
To the best of our knowledge, long-term reliability of GaN HEMTs at cryogenic temperatures has not yet been studied in depth. The work performed in [277] found several failure modes related to the increase in di/dt as temperature decreased, resulting in premature gating of the upper transistor in the phase leg due to the intrinsic parasitic inductance in the device packaging.

B. Elevated Temperature Performance and Reliability
High-temperature performance and reliability of GaN HEMTs, particularly industrial devices, have only recently been investigated due to the challenges in developing hightemperature packages [235]. An initial study of experimental nonrecessed GaN GITs was performed in [282] up to 420°C for four different buffer designs. V TH in all four device designs was found to have a similar negative temperature coefficient, which resulted in a normally ON behavior for a specific buffer at 420°C. R DS,ON was found to increase with temperature due to the high-temperature degradation of 2DEG mobility and contact resistance. Similar work in [283] examined the dc characteristics of bare-die R&D and packaged commercial SP-HEMTs up to 500°C and 250°C, respectively, and found a similar increase in R DS,ON and small negative temperature coefficient for V TH with increasing temperature. High-temperature static characterization of industrial 1.2 kV vertical GaN Fin-JFETs was reported in [250], revealing a V TH shift below 0.15 V and R DS,ON increase by two times at 200°C as compared with those at 25°C; the BV at 200°C is considerably higher than that at 25°C due to the avalanche capability.
In general, the switching time and loss of GaN HEMTs are expected to increase with temperature. The switching loss of commercial SP-HEMTs was reported in [284] to show a larger temperature coefficient than SiC MOSFETs, particularly at high currents. In comparison, dynamic switching characteristics at high temperature of an early commercial cascode device were investigated in [285] up to 200°C, with no significant variation in switching speed or loss observed as temperature increased.
As for device reliability, V DS step-stress testing of the R&D GaN HEMTs in [282] up to breakdown showed a decrease in the observed V DS failure voltage from 380 V at room temperature to 160 V at 420°C, which was attributed to vertical leakage through the epitaxial stack. A high-temperature robustness test in nitrogen gas of SP-HEMTs in [283] found that V TH remained stable over 20 days of exposure, while R DS,ON and saturation current were found to degrade depending upon the presence of bonding pads, indicating the determining role of packaging in device reliability at high-temperature extremes. A recent review article has discussed in detail the power device packaging for high-temperature applications [235].

XI. IMMEDIATE RESEARCH NEEDS
While there has been much advance in the understanding of GaN device stability, reliability, and robustness, there are still a number of immediate research needs. These gaps are important for the increased adoption of GaN devices in power electronics' applications. Some of these research needs include the following.
1) Full understanding of trapping locations (e.g., surface, channel, and buffer) and energetics (e.g., shallow, deep, and acceptor-or donor-type) that correlate to each stability, reliability, and robustness issue, which allows for addressing these issues through the improvements in material, processing, and device designs. 2) New circuit methods for the in situ measurement and monitoring of device parametric stability in highfrequency switching with minimal disturbance on converter operations. 3) Accurate models that describe the device failure rate as a function of operating stimuli (i.e., voltage, current, and their concurrence under various switching schemes) for both the device's drain-source loop and gate loop. 4) Reliability, robustness, and qualification of GaN devices for application-specific mission profiles, e.g., electric vehicle powertrains, solar and wind power conversion, power supplies, etc. 5) Improved compact and TCAD models accounting for the device dynamic characteristics (e.g., D-R DS,ON , V TH shift, and C OSS loss) that are ideally applicable to multiple types of GaN devices. 6) Protection methodologies for the necessary fast turn-OFF of GaN HEMTs under SC, overvoltage, and surge-energy events. 7) Full understanding of gate reliability and robustness under application-use conditions, as well as lifetime models accounting for intrinsic and extrinsic failures.

8) Further radiation qualifications and investigations on
the TID and SSE breakdowns of the different GaN device structures for integration into the aeronautical and aerospace industries. 9) Further qualification and evaluation of GaN power devices under extreme temperature conditions for aerospace applications and the emerging quantum computing applications. 10) Stability, reliability, and robustness of high-current GaN devices and modules, accounting for the packagingdevice interplays. 11) Device innovations, e.g., D-R DS,ON free GaN HEMTs, avalanche and SC capable GaN HEMTs, vertical GaN devices, higher voltage and higher current GaN devices. 12) Stability, reliability, and robustness of GaN power technologies that do not possess good counterparts in Si and SiC, e.g., the full-GaN-integrated power device and IC, the single-chip bidirectional GaN switch.

XII. SUMMARY
GaN devices, both discrete and composite, offer a plurality of benefits to power electronics' applications. Since these devices have only recently entered the commercial markets and they possess significantly different device structures and physics as compared with Si and SiC power devices, many stability, reliability, and robustness questions remain to be addressed before their full integration into various applications.
This article presents a comprehensive discussion on the stability, reliability, and robustness issues of GaN devices, with the particular emphasis on their presence under dynamic switching conditions and their impact on power electronics' systems. Some key takeaways include the following. 1) Traditional Si-based qualification standards are not sufficient for GaN HEMTs; GaN device vendors have published many extended reliability/stability/robustness data, but many evaluation methods have not been standardized. 2) GaN HEMTs suffer from parametric instability in highfrequency switching; the D-R DS , ON and C OSS loss issues can induce additional conduction and switching losses, respectively; the characterization of these parametric shifts is preferable to be performed under or best similar to the application-use conditions. 3) GaN HEMTs possess limited SC capabilities and minimal avalanche capabilities; the SC capabilities can be significantly impacted by bus voltage; the dynamic BV differs from the static BV and is the key determining factor for the surge energy and overvoltage robustness; GaN HEMTs can be designed to withstand higher surge energy with a larger overvoltage margin and higher C OSS ; the GaN HEMT overvoltage robustness could become inferior at high frequencies. 4) GaN HEMTs' lifetime is preferable to be characterized based on the application-use switching conditions; the gate lifetime in p-gate HEMT can become a limiting factor of the overall device lifetime.

5) Vertical
GaN devices show good promise for realizing a reduced parametric instability as well as good avalanche and SC robustness, which is comparable or even superior to SiC and Si devices. 6) The radiation ruggedness is strongly dependent on the OFFstate blocking bias; significant voltage derating must be considered for radiation critical applications. 7) GaN HEMTs show particular promise for cryogenic temperature applications due to the unique properties of the 2DEG channel; preliminary promising results have also been reported for high-temperature applications.