Integrated Fractional-Turn Planar Transformer for MHz and High-Current Applications

In megahertz and high-current applications, planar transformers face problems such as significant winding loss and limited winding current-carrying capacity, which seriously restrict the converter's efficiency and power density improvement. This article proposes a fractional-turn planar transformer structure and embeds key power devices into the transformer. The proposed method can significantly shorten the winding length, thus reducing winding losses. At the same time, the high integration of the transformer and key power devices can effectively reduce the overall volume of the converter and eliminate terminal losses. The analysis and optimization of the proposed integrated fractional-turn transformer are presented in detail. Finally, a 380 V–12 V 1-kW unregulated LLC is built with the proposed integrated transformer. The full-load efficiency is 97.7%, and the power density is 99 W/cm3, both of which are the highest among the state-of-the-art prototypes with similar specifications.


Integrated Fractional-Turn Planar Transformer for
MHz and High-Current Applications Kangping Wang , Senior Member, IEEE, Qingyuan Gao, Gaohao Wei, and Xu Yang , Senior Member, IEEE Abstract-In megahertz and high-current applications, planar transformers face problems such as significant winding loss and limited winding current-carrying capacity, which seriously restrict the converter's efficiency and power density improvement. This article proposes a fractional-turn planar transformer structure and embeds key power devices into the transformer. The proposed method can significantly shorten the winding length, thus reducing winding losses. At the same time, the high integration of the transformer and key power devices can effectively reduce the overall volume of the converter and eliminate terminal losses. The analysis and optimization of the proposed integrated fractional-turn transformer are presented in detail. Finally, a 380 V-12 V 1-kW unregulated LLC is built with the proposed integrated transformer. The full-load efficiency is 97.7%, and the power density is 99 W/cm 3

I. INTRODUCTION
W ITH the continuous development of aerospace, information technology, electric vehicles, etc., higher requirements are placed on power converters in terms of efficiency, power density, and current capability. Taking the data center as an example, as a basic platform to support the development of new infrastructures such as artificial intelligence, cloud computing, 5G, etc., the electricity consumption of the data center will account for about 4.5% of the electricity consumption of the whole society in 2025 [1]. However, the power supply's efficiency from the power grid to the processor in the data center is only 85% at present [2]. Therefore, improving the power converter's efficiency is significant for saving energy and reducing carbon emissions. At the same time, with the development of data centers, the power consumption of a single rack is as high as 25 kW, about 2100 A@12 V, which poses Manuscript  a greater challenge to improve the power density and current capability of power converters.
In recent years, with the application of wide-bandgap devices and soft-switching technology, the switching frequency has been continuously pushed up to the megahertz (MHz) frequency [3], [4]. At the MHz frequency, planar transformers based on printed circuit board (PCB) windings have been widely studied and applied due to their advantages of high power density, good consistency, and easy interleaving of windings, etc. However, it is very challenging to handle large currents efficiently at MHz frequencies. This is because eddy current effects (including proximity effect and skin effect) become more pronounced as frequency increases, resulting in higher winding resistance and losses. To reduce the eddy current effects, thinner conductors are required. At the same time, more windings need to be paralleled to handle high currents. Taking the LLC circuit shown in Fig. 1 as an example, there are the following problems under high frequency and high current [5]: 1) current sharing issues in parallel windings; 2) current sharing issues in parallel synchronous rectifiers (SRs); 3) large terminal loss; 4) large leakage inductance, etc. Therefore, it is not a high-efficiency way to directly parallelize multiple windings in high-frequency and high-current applications.
Matrix transformer has been extensively studied to solve the above problems. The windings and SRs can be dispersed around the core legs by adopting a multileg magnetic core structure to  reduce PCB layers and terminal losses. Power converters based on MHz matrix planar transformers have been proven to have higher power density and efficiency than the traditional ways with direct parallel windings [6], [7], [8], [9]. However, the research works show that the winding loss of the planar matrix transformer is still dominant [8] and is not easy to reduce further.
Fractional-turn transformers have been proposed for a long time, and they have recently regained attention in high-frequency, high-current, and low-voltage applications. Fractional-turn transformers can be divided into two categories: 1) fractional-flux structure and 2) fractional-winding structure, as shown in Fig. 2. The magnetic core of the fractional-flux structure has multiple side legs, and the fractional turn is achieved by placing the secondary winding around the side post [10], as shown in Fig. 2(a). To further reduce the winding end loss and leakage inductance, the current of each secondary winding is first rectified and then connected in parallel on the dc side [11], [12]. However, the winding length of the fractional flux structure is not significantly shortened, so the reduction of winding loss is limited. The fractional-winding structure achieves the fractional turns by constructing fractional winding lengths. Taking Fig. 2(b) as an example, a whole turn of winding is divided into several segments, and the current in each segment can be equal through a symmetrical structure design. This structure is used for the first time in the application with a wide voltage range, and the equivalent transformer ratio can be changed by configuring the rectifier bridge [13]. Furthermore, 1-MHz LLC DCX is built based on the fractional-winding structure and achieves a full-load efficiency of 96.8% [14]. In [15], a 750-kHz, 600-W half-turn structure LLC DCX was developed where a Litz wire is used for the primary winding and PCB trace is used for the secondary winding. The full-load efficiency reaches 97.2% (the driving loss is not included). The fractional-turn transformers have great potential for winding loss reduction. However, there is still a gap between converters built with fractional-turn transformers and state-of-the-art converters in terms of efficiency and power density.
This article proposes a highly integrated fractional-turn planar transformer for MHz and high-current applications. The SRs and output capacitors are embedded in the transformer. The proposed transformer has a more compact structure and shorter winding length than the conventional fractional-turn schemes, so the power density and efficiency can be further improved. A 380 V-12 V/1 kW LLC DCX is built with the proposed integrated fractional-turn transformer. The experimental results show that the LLC DCX achieves a full-load efficiency of 97.7% and a power density of 99 W/cm 3 , both of which are the highest among the state-of-the-art prototypes with similar specifications.

A. Proposed Schemes and Basic Relationships
The proposed fractional-turn transformer structure is shown in Fig. 3, which integrates the SRs and output capacitors. A full turn of the winding around the central column is equally divided into N segments. Then N groups of SRs and output capacitors are symmetrically placed on the windings. For simplicity, the SRs are replaced by diodes in the figures. The output nodes V o and GND are connected together outside the transformer. Here, a full-wave rectifier circuit is taken as an example, and the proposed methods are also applicable to full-bridge rectifier circuits and the like. Fig. 4 shows the working processes of the proposed integrated transformer. In the positive half cycle, SR a1 -SR a4 are ON, and SR b1 -SR b4 are OFF. The output capacitors provide a low-impedance path for high-frequency winding currents. Through a symmetrical structure design, the high-frequency current in the secondary winding will flow around the center column. The path of the high-frequency current is the shortest, which can significantly reduce the winding loss and eliminate the terminal loss. For the negative half cycle, SR b1 -SR b4 are ON, and SR a1 -SR a4 are OFF. The working process is similar and will not be repeated here.
The voltage on each group of output capacitors is V o . The voltage on each winding segment is clamped to V o , which is equal in magnitude and opposite to the output capacitor voltage. So the output capacitors of the N groups are all grounded in  common. The voltage on one turn of the winding around the center column is NV o , which is N times the output voltage V o , so the equivalent turn of each segment winding is 1/N.
When the SRs are turned ON, the voltage on one turn of the windings is clamped to NV o . The magnetic flux density B(t) in the core is shown in Fig. 5. According to Faraday's law, it can be deduced If B m and T s are kept unchanged, the effective core area A e is proportional to N. Here, we consider the case where the center column of the magnetic core is circular. The effective core area A e = πr 2 , so where r is the radius of the central column. The length of each segment in secondary winding l s is where c is the winding width. Here, we ignore the distance between windings and cores for simplicity. It can be seen from the above formula that the length of each secondary winding l s decreases with the increase of N, which means that the resistance of each secondary winding can be reduced by increasing N.
The length of the primary winding is where N p1 is the turns of the primary winding when N = 1. Likewise, the resistance of the primary winding can be reduced in the same proportion by increasing N. The volume of the core is where A and T 1 are the area and thickness of the top and bottom plates, respectively, and T 2 is the height of the central column, which is a fixed value. A and T 1 are calculated by N full-turn transformers are used as a reference for comparison. Fig. 6 shows an example with N = 4. The output power of each full-turn transformer is P o , so the total output power of N full-turn transformers is NP o , the winding loss is NP Cu (1), and the core loss is NP Fe (1). The full-turn transformer is a special case of a fractional-turn transformer, where N = 1. As for the fractional transformers with an output power of NP o , the winding loss is P Cu (N), and the core loss is P Fe (N). The magnetic loss is proportional to the core volume because the maximum magnetic flux density B m and the core loss per unit volume P V are kept the same. The winding losses are proportional to the winding length because the current in the windings is the same and the winding resistance is proportional to the winding length   7 shows the relative variation of fractional-turn transformer losses. It can be seen that the reduction of the winding loss is much greater than the increase of the core loss with the increase of N. The volt-second product is small in the case of low voltage and high frequency, so the loss of the magnetic core is relatively small. At high currents, the winding losses of planar transformers tend to be dominant and much higher than the core loss. Therefore, choosing an appropriate N by weighing the core loss and copper loss can reduce the total loss for applications with high frequency, high current, and low voltage output. In addition, the proposed scheme is highly integrated and is expected to increase the converter's power density further. Fig. 8 shows the derivation of an equivalent circuit of the fractional-turn transformer. Here is an example of a one-fourth turn. We assume that the core and winding structures are perfectly symmetrical and ignore external reluctance. Fig. 8(a) shows the simplified core structure with primary and secondary current loops. Fig. 8(b) shows the magnetic circuit derived from Fig. 8(a). R s is the reluctance of each side leg. R c is the reluctance of the central leg. R lk is the reluctance corresponding to the leakage inductance of the primary side. R s and R c can be expressed as

B. Equivalent Circuit Modeling
where l g is the air gap length, l s and l c are the magnetic path length of the side column and the center column, respectively, A s and A c are the cross-sectional area of the side column and the central column, respectively (where A s = A c /4), and µ r is the relative permeability of the core.
The number of turns on the primary side is N p , so the magnetomotive force of the primary current is N p i p . The magnetomotive force of the secondary side is i s . The total reluctance R m can be obtained by combining the side leg reluctance R s and the side leg reluctance R c , namely Then, the magnetic circuit model is transformed into an electric circuit model, as shown in Fig. 8(c). Furthermore, the equivalent circuit of the fractional-turn transformer can be derived as shown in Fig. 8(d). The secondary current i s is replaced with four ideal transformers considering that the secondary winding has four openings. The turns ratio of each transformer is N p /4:1/4. The leakage inductance and magnetizing inductance are transformed to the primary side, so Finally, we can draw a complete LLC circuit with other circuit components, as shown in Fig. 9. The proposed fractional-turn transformer is highly integrated, including the transformer, SRs, and output capacitors.

A. Design and Optimization
A 380 V-12 V/1 kW, 1 MHz LLC DCX is designed and optimized with the proposed integrated transformer. The magnetic core material is DMR53 from DMEGC company, suitable for 1-3 MHz operating frequency. The primary and secondary windings of the proposed integrated transformer can be simplified into a ring shape, as shown in Fig. 10. Winding losses and core losses are simulated in 2-D Maxwell software. In Fig. 10, r   is the radius of the central core column, c is the width of the secondary winding, and d is the distance between the winding and the core. The edge distance between the center column and the side column of the magnetic core is a = c + 2d. Fig. 11 plots the contours of the transformer losses as a function of core radius r and winding width c. The numbers  shown on the curves are the transformer losses. The transformer footprint is also related to r and c A = π(r + c + 2d) 2 + πr 2 .
Furthermore, the footprint curve of the transformer can be plotted as a function of r and c, as shown by the dotted line in the figure. For given transformer losses, r and c should be chosen to minimize the transformer footprint. The tangent point between the loss curve and the footprint curve is the optimal point where the footprint is the smallest for a given transformer loss. Furthermore, we can find the tangent point under different transformer losses and the corresponding footprint. Finally, the curve of transformer loss with footprint can be drawn, as shown in Fig. 12. The final choice of the transformer footprint is 650 mm 2 as a tradeoff between transformer loss and footprint. The effective core area A e is selected as 163 mm 2 , and the resulting maximum magnetic flux density B m is 74 mT.

B. Core Shape Optimization
Generally, the shape of the power modules is rectangular. With a circular magnetic core, it is difficult to fully use the corner area, which wastes some PCB area and reduces the converter's power density, as shown in Fig. 13(a). The magnetic core shape is optimized into a rectangular shape to improve the area utilization, as shown in Fig. 13(b). The center leg of the core is optimized as a rectangle with rounded corners. The radius of the rounded corners is r, and the side length of the rectangle is b.
The two cores have the same effective area A e and winding width c. The core areas of the outer leg and center leg are kept equal. Taking into account the four unused corners, the total footprint of the circular core is For square cores, the total footprint is Then, the area ratio of the two cores is The footprint ratio is 78.5%, which means that square cores can save 22.5% of the board area.

A. Winding Layout
Fig. 14 shows the layout of the proposed fractional-turn transformer windings. The PCB with four copper layers can be used. The top and bottom layers are the secondary windings, which are convenient to connect with the SRs and the output capacitors. The SRs and output capacitors are symmetrically distributed on the secondary winding. The inner two layers are the primary windings with four turns. The turns ratio of the fractional transformer is 4:1/4, which is equivalent to 16:1. It can be seen that the winding area is fully utilized. The overlapping area of the primary and secondary windings is also relatively small, which is only one-third of that of the matrix transformer    [8] due to the reduced winding length and no corners. The parasitic capacitance is proportional to the winding area. That is, the parasitic capacitance between the primary and secondary windings is reduced in the same proportion, which is beneficial to reduce electromagnetic interference (EMI) noise. Fig. 15 shows the connection of the dc outputs. The GND and V o of all outputs are connected to the PCB outside the transformer. Since the outputs are direct currents, the inner and outer copper layers of the PCB can be directly connected in parallel.

B. Gate Layout of SRs
One driver is used to drive all SRs to simplify design and reduce cost. Because the SRs are distributed over the windings, minimizing gate inductance and using a symmetrical layout is critical. A sandwich layout structure is adopted, where the gate trace is buried between two ground layers. This sandwich structure can significantly reduce gate parasitic inductance. Fig. 16 shows the gate traces layout from the driver to the SRs. The gate parasitic inductance is extracted using the Q3D simulation, and the results are shown in Table I. Low-voltage Si MOSFETs are used as SRs, and their large input capacitance reduces the sensitivity of gate-source voltage to the gate parasitic inductances [16]. Circuit simulations were performed in LTspice, where the gate parasitic inductances and the coupling between them were considered. The maximum rise/fall time difference of V gs among SRs is only 12 ns, accounting for 1.2% of one cycle with a 1-MHz  switching frequency. This has little effect on the control of the SRs.

C. Finite-Element Simulations
When the circuit works, the SRs on the same PCB side are turned ON at the same time. The secondary ac current forms a complete loop around the center column. Its working process is the same as that of the traditional full-turn transformer. The proposed transformer is simulated in 3-D Maxwell software. Fig. 17 shows the simulated current distribution in the windings. Fig. 18 shows the simulated flux density in the magnetic cores. The distribution of the winding current and the core flux density are well symmetrical. The air gap should be kept away from the PCB copper layer to reduce the effect of fringing flux on winding losses. The distance from the top plate core to the top PCB copper layer is set as 1.1 mm, which is about 16 times the air gap length.
Furthermore, a simulation is performed to prove that the secondary winding current will not flow through V o and GND buses. Fig. 19(a) shows the simulation model. The secondary winding is divided into four segments. These segments are connected by a section of insulating material with high permittivity, which is used to simulate the output capacitors C o . The V o bus and GND traces are connected to the secondary windings near the output capacitors C o . A current excitation of 1 A is applied to the primary winding (for simplicity, only one turn). Fig. 19(b) shows the induced current distribution on the secondary winding, V o , and GND traces. The current density on the secondary winding is much higher than the current density on the V o and GND traces. The currents on V o and GND traces account for 0.024% and 0.089% of the current on the secondary winding, respectively, which is very small and can be ignored. Fig. 20 shows the simulation results for the effect of the air gap on the magnetizing inductance and leakage inductance. The magnetizing inductance decreases as the air gap increases. The change of air gap has little effect on primary leakage inductance.

V. EXPERIMENTAL RESULTS
A 380 V-12 V/1 kW LLC DCX is built to verify the proposed integrated transformer. The switching frequency is 1 MHz. The switches on the primary side are GaN devices, and the SRs are Si MOSFETs. The PCB has six copper layers, and the copper thickness of each layer is 2 oz. Only four layers are used for windings, and the other two are reserved for EMI shielding. The circuit parameters are shown in Table II. The resonant inductance L r is the primary leakage inductance with a value of 0.2 μH. The magnetizing inductance L m is 25 μH. The deadtime T d is 88 ns. The magnetic core material is DMR53 from DMEGC company, suitable for 1-3 MHz operating frequency. The primary winding turns are 4, and the equivalent turns of the secondary winding are 1/4. Fig. 21 shows the LLC DCX prototype pictures. The size of the LLC DCX converter prototype is 29 mm × 41 mm, and the total thickness is 8.5 mm. The power density of the prototype  is 99 W/cm 3 , including the control and driver circuits. The SRs have a bottom thermal pad, and the heat is mainly dissipated out through the PCB. A thermally conductive material can be filled between the magnetic core and the SRs, and between the magnetic core and the PCB, so that part of the heat can be conducted out through the magnetic core. Fig. 22 shows V gs and V ds waveforms of the four SRs on the top side. V gs and V ds are measured close to each SR. Both the waveforms V gs and V ds among SRs overlap very well, which shows that the symmetry of the SRs is good. The driving capability of a single driver chip is sufficient as the rising and falling edges of V gs are fast. In addition, there is no overshoot in the gate voltage waveform, which shows that the gate parasitic inductance is acceptable with the optimized layout.
Furthermore, thermal distribution is measured to prove the transformer works well. Fig. 23 gives the thermal distribution under natural convection conditions without fans. All SRs are turned OFF, and the load current is set to 5 A. The main loss of the transformer is the core loss and the diode conduction loss of the SRs. The thermal image was measured at 2 min after loading, and the heat distribution tends to be stable. The thermal distribution of the transformer is very symmetrical, which shows that the symmetry of the transformer is good and the whole circuit works well.   Fig. 24 shows the measured key waveforms at the light and full load. The circuit works well under different loads. The V ds waveforms of both the primary and secondary switches are very clean, and soft switching is fully realized. Fig. 25 gives the measured efficiency. The output current is up to 85 A, and the output power is up to 1000 W. The peak efficiency is as high as 98.2% at 60% load, and the full-load efficiency reaches 97.8% for the power stage. With the control and driving loss, the peak efficiency is 97.93%, and the full-load efficiency is 97.7%. Fig. 26 shows the thermal result under full load with forced air cooling. No heat sink was used in the experiment. The wind blows from the upper right corner to the lower left corner, and the wind speed is 3.3 m/s. The thermal image was taken in 2 min,    and the temperature rise of all components tended to be stable. The primary GaN devices' temperature is the highest, reaching 77.9°C, and the temperature rise is 51.1°C. If the module is potted and a heat sink is added, the heat dissipation of the devices in the module will be better. The maximum temperature can be further reduced. Table III compares various LLC DCX with similar specifications where the input voltage of about 380 V and the output voltage of 12 V. The losses and volumes of planar transformers are also compared. The transformer loss percentage is the ratio of the transformer loss to the output power, which can be used to compare the transformers with different power levels. The volumes of some transformers are not directly given and are estimated by referring to the size of the prototype. The SRs and output capacitors are included when estimating the transformer volumes. The transformer power density is the ratio of output power to transformer volume. The loss percentage of the traditional fractional-turn transformers is 1.07%-1.63% [11], [12], [14] while that of the proposed transformer is only 0.62%, which is reduced by 42%-62%. The power density of the traditional fractional-turn transformers is 39.5-72.7 W/cm 3 [11], [12], [14], [15], [17] while that of the proposed transformer is as high as 140.9 W/cm 3 , which is increased by 94%-260%. Fig. 27 plots the loss percentage and power density for different transformers. It can be seen that the transformer designed in this article has the smallest loss percentage and the highest power density when compared with other transformer designs. Fig. 28 compares the power density and efficiency among various 380 V-12 V LLC DCX with similar specifications. The LLC DCX built with the proposed transformer achieves a power density of 99 W/cm 3 and a full-load efficiency of 97.7%, both of which are currently the highest among the state-of-the-art prototypes. As for the peak efficiency, this work is only 0.1% lower than the best matrix transformer solution [19]. In [18] and [20], the higher peak efficiency is achieved mainly due to the use of lower figure of merit (FOM) switches and stackedcells topology. Higher peak efficiency could be predicted if the method with low FOM switches and stacked-cells topology is combined with the proposed transformer scheme.

VI. CONCLUSION
This article proposes a fractional-turn planar transformer structure with integrated key power devices for MHz and highcurrent applications. The proposed method can significantly shorten the length of the windings, thus reducing winding losses. Meanwhile, integrating the transformer and key power devices can effectively reduce the overall volume and eliminate terminal losses. The analysis and optimization are carried out in detail. Finally, a 380 V-12 V/1 kW LLC DCX was built with the proposed integrated transformer. The circuit works well under different loads. The measured full-load efficiency is 97.7%, and the power density is 99 W/cm 3 , which is higher than the state-of-the-art prototypes with similar specifications. The peak efficiency reaches 97.93% with control and driving losses. The proposed method is suitable for high-frequency, high-current, and low-voltage output applications.