Small-Signal Modeling of Phase-Shifted Digital PWM in Interleaved and Multilevel Converters

In this article, small-signal modeling of digital pulsewidth modulators (DPWMs) used in multicell voltage source converters (VSCs) is addressed. In addition to sampling and computation, DPWM introduces delay, which impairs VSC's dynamic performance and robustness. In order to take into account the influence of modulation delay, an accurate small-signal representation of DPWM is necessary. Here, modeling of multisampled bipolar and unipolar phase-shifted DPWMs for single-, double-, and multi-update strategies is presented. The simplest multilevel modulation of single-cell full-bridge VSCs, unipolar DPWM, is also covered by the analysis. The derived operating-point-dependent small-signal DPWM models are verified using simulated and experimental frequency response measurements up to four times the Nyquist frequency. Comparisons are also made with the models conventionally considered in the literature. Additionally, an approximate method is presented to model the influence of dead time on DPWM's small-signal dynamics. For the purposes of showcasing the importance of the proposed DPWM models, high-frequency admittance of a VSC employing multisampled multiupdate unipolar DPWM is modeled and verified in simulations and experiments.

For current-controlled PS-DPWM MC-VSCs, the choice of sampling and controller update rates is not always straightforward [15], [16]. Most often, the multisampled approach is taken, where, due to frequency multiplication [17], the average current is acquired more than twice per switching period of each cell [3], [16]. Ideally, sampling instants are chosen to coincide with the peaks, valleys, and intersections of individual carriers. Regarding the controller update, the first approach, denoted as multisampled single-update (MSSU), assumes that the modulating signal for each cell is updated either at the peaks or at the valleys of the corresponding carrier. If the update is performed both at the peaks and at the valleys, i.e., twice per carrier period, the approach is referred to as multisampled double-update (MSDU) [16], [18]. Another approach, denoted as multisampled multiupdate (MSMU), assumes that the modulating signal, which is the same for all cells, is updated at the peaks, valleys, and intersections of all carriers [3], [7], [19]. With MSMU, some nonlinear characteristics may appear in case of vertical crossings between modulating signals and carriers [7], [19], [20]; on the other hand, MSMU significantly reduces the modulation delay [21], [22].
Modulation delay, together with delays due to sampling and computation, limits the achievable bandwidths and deteriorates the robustness of VSCs employing DPWM [21], [23], [24], [25]. In order to account for the impact of the modulation delay on a system's performance, an adequate small-signal representation of the modulator is essential [21], [26], [27]. Although PS-DPWM is widely used, accurate small-signal models are derived only for two-level modulation strategies [26], [28]. A lack of small-signal modeling is present even for the simplest multilevel modulation of single-cell full-bridge VSCs, unipolar DPWM (U-DPWM). Without formal derivations, the authors in [7] assume that the model from [29], derived for two-level DPWM, is directly applicable for MSMU-UPS-DPWM. In this article, we show that the model from [29] accurately represents MSMU-BPS-DPWM, whereas a different model is obtained for MSMU-UPS-DPWM.
To fill in the gaps of previous research, this article addresses modeling of various strategies for multilevel modulation. Smallsignal models of U-, BPS-, and UPS-DPWM are derived for the MSMU, MSDU, and MSSU strategies. The presented models are verified using simulated and experimental frequency response measurements (FRMs), up to four times the Nyquist frequency (NF). Benchmarking against models typically considered in the literature is provided to highlight the accuracy achieved. To showcase the importance of an accurate DPWM representation, high-frequency admittance of a full-bridge VSC employing MSMU-U-DPWM is modeled and validated in simulations and experiments.
This article is organized as follows. In Section II, the basic principles of the PS-DPWM are outlined, along with an explanation of the MSMU, MSDU, and MSSU strategies. The mathematical derivation of the U-, BPS-, and UPS-DPWM small-signal models is presented in Section III. The verification and benchmarking of these models is provided in Section IV. As an application example, high-frequency admittance modeling with MSMU-U-DPWM is addressed in Section V. Finally, Section VI concludes this article.

A. System Description
In order to derive small-signal models of U-, BPS-, and UPS-DPWM, a single-phase, digitally controlled, N cell CHB converter is considered in this article. CHB is chosen as an illustrative example because it allows the implementation of the three DPWMs types. Nonetheless, the presented methodology can be directly applied to other MC-VSC topologies, employing PS-DPWM. The dc-link voltage of each cell is assumed to be constant and equal to E. The extension of derived models for unbalanced operation is left for future work.
A block diagram of the considered current-controlled system is shown in Fig. 1(a). An analog-to-digital converter (ADC) performs the transition from the continuous domain to the digital domain. Current sampling is performed at the middle of the applied voltage pulses, so that center-pulse (synchronous) sampling is obtained [21]. The highest possible sampling frequency f s that ensures removal of the switching ripple from the current i is considered within the article, as explained in Section II-B and II-C.
By subtracting the sampled current i s from the reference i r , error signal e is obtained and used as input to the current controller G c . The controller output update is usually delayed by one sampling period due to the finite execution time [21]. The voltage reference generated by the current controller is scaled to the range [0, 1], resulting in the modulating signal m s . In order to obtain the digital modulating signal for the ith cell, m ui , a rate transition from f s to f u may be required, depending on whether the multi-, double-, or single-update strategy is used. The implementation and differences between these strategies are addressed in Section II-D. It is important to note that this article considers symmetric PS-DPWM, where the same signal m s is forwarded to all rate transition blocks.
The modulating signal m ui is used by DPWM i to perform the transition from digital to continuous domain. Its inherent zeroorder hold (ZOH) function transforms m ui to m i . As outlined in the following subsection, switching waveforms for the ith cell, x ia,b , are obtained from m i based on the modulation type. They are used to control the power transistors within the ith cell of the CHB converter. Each cell is realized as an H-Bridge, which consists of two legs, a and b, as shown in Fig. 1(b). The output voltage of the ith cell v oi is determined as a difference between the output voltages of the two legs, v oi = v ai − v bi . Since the cells are connected in series, the output voltages of all the cells are summed up to form the output voltage of the CHB converter where x ai and x bi are the switching waveforms for legs a and b, respectively, and x eq is the equivalent switching waveform. 1 The difference between v o and the voltage at the point of common coupling (PCC), v pcc , is applied to an arbitrarily chosen inductive output filter L.

B. Bipolar and Unipolar Modulation of a Single Cell
Control signals for switches within the same leg of an individual H-bridge cell are always complementary to avoid shootthrough. Two widely used strategies to determine switching waveforms for different legs are bipolar (B-DPWM) and unipolar modulation (U-DPWM) [14], [30].
In B-DPWM, the same switching waveform is used to control both legs, i.e., x ai = x bi . It is determined by the comparison between m i (t) and w i (t), as shown in Fig. 2(a). This results in two possible levels for the cell output voltage, −E and E. In case only one cell is used, the inductor current features a triangular switching ripple with the lowest frequency component at f rip = f pwm . Thus, for a single cell modulated by B-DPWM, the maximum frequency at which current can be sampled, without introducing switching ripple in the feedback, is equal to 2f pwm .
On the other hand, in U-DPWM, x ai = x bi . The switching waveform for leg a, x ai , is determined in the same way as in B-DPWM. However, x bi is determined by a comparison between the complementary modulating signal 1 − m i (t) and the switching carrier w i (t), as shown in Fig. 2(b). Alternatively, U-DPWM can be realized so that the two legs use the same modulating signal, but different, 180 • phase-shifted carriers. Nevertheless, the former realization is more often used, since it requires fewer carriers. With U-DPWM, three output voltage levels appear: −E, 0, and E. In case only one cell is used to supply the filter inductor, its current features a triangular switching ripple with the lowest frequency component at f rip = 2f pwm . Thus, U-DPWM allows the average current to be sampled four times per switching period. Compared to B-DPWM, U-DPWM offers twice the frequency multiplication [3], [12], [14]; however, it also increases the common-mode noise injection [30].

C. Phase-Shifted Modulation
In PS-DPWM a phase-shift between carriers of the cascaded cells is introduced in order to achieve frequency multiplication effect, i.e., increase of f rip . The value of the phase-shift depends on the number of cells and the modulation type used, i.e., bipolar or unipolar.
In case of BPS-DPWM, in order to achieve the highest possible harmonic cancellation [31], phase-shift between carriers

D. Multisampled Control With Multi-, Double-, and Single Update
In this subsection, three different strategies to choose the update rate f u = 1 T u of the controller are briefly explained. For all strategies, the sampling rate is determined by the ripple frequency, i.e., f s = 2f rip .
In the MSMU strategy f u = f s , i.e., the modulating signal, which is the same for all cells, is updated as often as the current sampling is performed, . This is illustrated in Fig. 3(a), where BPS-DPWM with N = 3 is used as an example. As it will be analytically shown in the next section, the MSMU strategy offers a significant reduction in modulation delay. However, since the modulating signal update is performed more than twice per switching period, around certain steady-state operating points (SSOPs), vertical crossings between the modulating signal and the carriers may appear, which results in a nonlinear behavior of the DPWM [7], [19], [20]. The analysis of this phenomenon is beyond the scope of this article, whose focus is on assessing the system properties around SSOPs where the linear behavior is guaranteed.
In the MSDU strategy, the update frequency is determined as f u = 2f pwm . The digital modulating signal for the ith cell, m ui , is obtained by resampling m s at instants that coincide with the peaks and valleys of the ith carrier, 2 as illustrated in Fig. 3(b). For certain applications, MSDU may be more suitable than MSMU, as it avoids the modulator nonlinearities caused by the vertical intersections between m i and w i [7], [16], [19].

E. Small-Signal Representation
Another possible update strategy is MSSU, where f u = f pwm and the modulating signal for each cell is updated at either peaks or valleys of the corresponding carrier, resulting in the symmetric-on-or -off-time modulation [28]. As shown in Appendix A, MSSU introduces a larger modulation delay than MSDU. Thus, when it is of interest to avoid modulator nonlinearities caused by vertical intersections, MSDU is usually preferred, although MSSU may be necessary in computationally demanding applications.
In Fig. 4, the small-signal s-domain representation of the system from Fig. 1(a) is shown. The output filter is represented by the transfer function G l where s is the complex variable of the Laplace transform, The transfer function of the current controller in s-domain is denoted by G c (s). The computational delay, which is assumed to be equal to one sampling period T s and is denoted by z −1 in Fig. 1(a), is represented in Fig. 4 as e −sT s . The main contribution of this article is the derivation of the DPWM small-signal model, represented by G DPWM (s) in Fig. 4, for the modulation strategies described earlier. The following variables will be useful for the derivation of G DPWM (s): x eq (t), defined in (1), and m eq (t) where v d is the delayed controller output and m is the continuous-time equivalent of m s , which when sampled at f s yields m s . Laplace transforms of small-signal perturbations of x eq (t) and m eq (t) are given bŷ , and m(t), respectively. By defining G DPWM (s) as the current controller can be seen to result in a reference voltage which, after being processed by G DPWM (s), appears at the output of the CHB. This equation will be used in the following derivations to determine the small-signal representation of DPWMs.

III. DPWM SMALL-SIGNAL MODELING
The goal of this section is to derive accurate small-signal models of U-, BPS-, and UPS-DPWM, for the MSMU and MSDU strategies. The procedure from [26] and [28] is used as a basis. The operating-point-dependent DPWM models are derived using pulse-to-continuous transfer function in s-domain, which is adequate for both sand z-domain modeling of the overall system [27], [28], [32]. 3

A. Multisampled Multiupdate Strategy
First, MSMU-BPS-DPWM is considered. Since in bipolar modulation x ai = x bi , (6) reduces to To simplify notation,x ai is replaced byx i and further used to denote the DPWM i 's output. In the following analysis, the waveforms of MSMU-BPS-DPWM with N = 3, shown in Fig. 6, are used. Nevertheless, the analytical expressions are provided for a general case of N cells.
The continuous input of the modulator m(t) is separated into a steady-state part M and a small perturbation: m(t) = M + m(t). By sampling m(t) at T s , the sampled modulating signal m s (t) is obtained. The DPWM i performs ZOH of m s (t) and the comparison with the triangular carrier w i (t). This results in the switching signal x i (t), as seen in Fig. 5(a).
Assuming an ideal sampler, its small-signal output can be represented as a series of Dirac impulses [26], [28], denoted bŷ m s (t). In order to distinguish between impulses that impact the rising from those that impact the falling edges of the modulator's output, this series is divided into two subseriesm sf (t) and m sr (t). Each of these two subseries is further divided into N subseries, corresponding to each individual cell δ is the Dirac delta function and p fi , p ri ∈ [0,N − 1] are indices that determine which sample within one T pwm affects which cells' falling and rising edges of the output. These indices are defined by p fi = div(NM, 1) + (N − 1)(i − 1) and , where div is the integer division operator. As for m(t), x i (t) can be separated into two parts: represent DPWM i 's response to M andm(t), respectively. As illustrated in Fig. 6, x i (t) is a series of pulses. Provided thatm(t) is sufficiently small,x i (t) can be approximated by a series of Dirac impulses positioned at the edges of X i (t), such that each impulse has the same integral over time as the pulse that it approximates [26], [28]. This series of impulses can be separated into two subserieŝ wherex fi (t) andx ri (t) represent DPWM i 's response tô m sf i (t) andm sri (t), respectively. The impulsesx fi (t) are positioned at the falling edges of X i (t) and delayed with respect tom sf i (t) by τ F i . Similarly, the impulsesx ri (t) are positioned at the rising edges of X i (t) and are delayed with respect tom sri (t) by τ Ri . For example, The delays τ F i and τ Ri , found from Fig. 6, are shown to be the same for each cell and equal to τ F i = τ F = mod(NM, 1)T s and τ Ri = τ R = (1 − mod(NM, 1))T s , where mod is the modulo operator. Thus, and taking into account that L{δ(t − t 0 )} = e −st 0 , the Laplace transforms ofx fi (t) andx ri (t) can be expressed aŝ x ri (s) = T pwm 2 e −s(1−mod(NM,1))T sm sri (s) wherem sf i (s) andm sri (s) are the Laplace transforms of m sf i (t) andm sri (t), respectively. Summation of (12) and (13) yields DPWM i 's output in s-domain This is illustrated in Fig. 5(b) where the block diagram of DPWM i is shown. Since, according to (9) and (10),m sf i (t) andm sri (t) are obtained from the same continuous signalm(t), by sampling it at T pwm ,m sf i (s) andm sri (s) can be expressed as [33] where j is the imaginary unit. Substitution of (15) and (16) into (14), while focusing on the input-output relation at the same frequency, i.e., assuming h = 0, yieldŝ The same expression can be obtained from (18) for N = 2, by substituting mod(2 M, 1) = |2M − 1|. This is clear considering that U-DPWM with N = 1 can be realized in the same way as BPS-DPWM with N = 2.

B. Multisampled Double-Update Strategy
Using the Dirac impulse-based approach from [26] and [28] and following the same methodology as for MSMU, small-signal models of DPWMs employing MSDU startegy can be derived. It can be shown that, contrary to MSMU, where each type of modulation, i.e., U-, BPS-, and UPS-DPWM, features a different small-signal model, with MSDU, the model is the same regardless of the modulation type used. Moreover, the model does not depend on the number of cells nor on the sampling period, but only on the switching period and the SSOP. Due to space limitations, detailed derivation is not included-only the final expression of the MSDU-DPWM small-signal model is provided

C. Overview of the Presented DPWM Models
By providing the frequency response of G DPWM , an overview of all DPWM small-signal models derived in the previous two subsections is presented in Table I, in order to emphasize different gains and delays. As a benchmark, the conventional doublesample double-update bipolar DPWM (DSDU-B-DPWM) is also included [26]. First, it can be seen that for the DSDU and MSMU strategies, the delay is determined in the same way, using the sampling period T s . On the other hand, for MSDU, the delay is determined by the switching period T pwm . Next, since for MSMU strategies T s = T pwm 2 N with bipolar and T s = T pwm 4 N with unipolar modulation, it can be observed that MSMU-DPWMs feature either N or 2 N times lower delay compared to MSDU-DPWMs. This is an important remark, since it points to higher control-loop bandwidth capabilities of systems with MSMU-DPWMs.
For comparison, the ZOH and pure delay models are also included in Table I, as they are often used in the literature to represent DPWM [3], [16], [19], [23], [24]. As it will be demonstrated by means of simulated and experimental FRMs, in order to obtain an accurate small-signal representation of MSMU-and MSDU-PS-DPWMs, the proposed models are necessary.

IV. VERIFICATION AND BENCHMARKING
A goal of this section is to verify the derived small-signal DPWM models. For the purposes of the following validations, all modulation strategies from Table I are realized in simulations as well as in a standardly available control platform. BPS-and UPS-DPWM are implemented with N = 3. The switching frequency for each DPWM type is chosen to correspond to a sampling frequency of 40 kHz. Thus, f pwm is set to {20, 10, 6.67, 3.33} kHz for B-, U-, BPS-, and UPS-DPWM, respectively.
For each modulation strategy, FRMs are performed for two different implementations: with and without one step computational delay, denoted by T d = T s and T d = 0, respectively. For MSMU strategies, validations are given for SSOPs around which nonlinear effects due to vertical crossings are not present [20].
MATLAB Simulink is used to perform the simulated FRMs. Perturbation generation, as well as postprocessing of v d (t) and v o (t) to obtain the FRMs of DPWMs is performed using the frequency response estimator block. The sinestream experiment mode is used with the perturbation frequencies in the range [6,80] kHz. Settling and acquisition time are set to 20 and 40 ms, respectively. The perturbation magnitudes are set so that they produce a 3% peak-peak variation of m. To force the operation around the desired SSOPs, an appropriate dc bias is imposed.
For experimental FRMs, the DPWMs from Table I are implemented on a DSP TI f28379 d. The measurements are performed in the following manner. A signal generator is configured to provide a small sinusoidal perturbation superimposed on the dc bias. The perturbation magnitudes and frequencies are chosen in the same way as in the simulations. The output of the signal generator, representing m(t), is sampled by the DSP. The DPWM outputs, i.e., the switching waveforms x ia,b (t), and the ADC input m(t) are measured using the Rigol MSO5354 oscilloscope, with a data length of 40 ms. The acquired data are imported into MATLAB, where x ia,b (t) and m(t) are algebraically transformed so that x eq (t) and m eq (t) are obtained, as in (1) and (3). Fast Fourier transform (FFT) of m eq (t) and x eq (t) is performed to obtain the spectral components at the perturbation frequency f p . The ratio between these components determines the frequency response of the DPWM at f p .
The experimental and simulated FRMs of the DPWMs are compared with the analytical models, both those derived in this article and those typically used in the literature.
First, results for MSMU strategies are presented. DSDU-B-DPWM is also included. In Fig. 7, the magnitudes of the simulated and experimental FRMs are compared with the different small-signal models. It is clearly visible that only the proposed models accurately predict the DPWMs' small-signal dynamics. Phases of the DPWMs' frequency responses, with and without one step computational delay, are compared with the proposed models in Fig. 8. Note that comparison between different models is shown only for magnitude, and not for phase, since all compared models predict the same phase delay. According to the presented results, the proposed models match the simulated and experimental FRMs, up to four times the NF.
The results for MSDU strategies are presented next. In Fig. 9, the magnitudes of the simulated and experimental FRMs are compared with the different small-signal models. As seen, only the proposed MSDU model accurately predicts the modulators' dynamics. Note that even though all MSDU-DPWMs feature the same small-signal model, the results shown in Fig. 9(a)-(c) differ from each other for the following two reasons. First, U-, BPS-, and UPS-DPWMs are all implemented with different f pwm , since the design criterion was to keep the sampling frequency the same. Next, different SSOPs are used to obtain the results in Fig. 9(a)-(c). Phases of the frequency responses for MSDU-DPWMs, with and without one step computational delay, are compared with the proposed model in Fig. 10. An excellent match is achieved between the proposed model, and simulated and experimental FRMs, up to four times the NF.
The presented results showcase that the proposed small-signal models accurately predict the modulators' dynamics in a very wide frequency range. Moreover, the proposed DPWM models are able to predict the dependence of the system properties on the SSOP, which the ZOH and pure delay models are not. For analyses at lower frequencies, up to approximately one sixth of the update frequency, the ZOH, pure delay, and proposed DPWM models can be used indistinguishably, since they result in identical phase response and magnitude response within 1 dB from the unity gain. However, for analysis at higher frequencies, around and above f u 6 , the use of the proposed DPWM models is essential to accurately predict the modulator's dynamic response. The importance of accurate high-frequency modeling is evident, for example, in the stability analysis of grid-tied converters [23], [27], which is illustrated in the following section.

V. APPLICATION EXAMPLE
Passivity-based controller design has been shown to be an effective tool that ensures stable operation of the system containing numerous power electronic converters [23], [24]. Using the impedance-based stability approach as a basis, it implies that, in order to prevent the harmonic instability issues, the converter's input admittance should be designed dissipative, i.e., such that its phase is within the range [-π 2 , π 2 ], in as wide frequency range as possible [24]. Recent studies have shown that destabilization of poorly damped grid resonances might also occur at frequencies near and above the NF [23], [34]. It is shown in [27], that the accurate DPWM model is of vital importance to predict the dependence of the admittance measurements (AMs) on the SSOP. Following the methodology from [27], this section addresses high-frequency admittance modeling of center-pulse sampled grid-following MC-VSCs, to showcase the importance of the DPWM models presented in the previous section.

A. Multiple-Frequency Admittance Model
Using similar mathematical procedures as in [27], it can be shown that cancelation of additional loops induced by the PWM sidebands also holds for the center-pulse sampled MC-VSCs. Thus, an accurate small-signal admittance model of the MC-VSC from Fig. 1 can be obtained by incorporating an appropriate DPWM model from Table I in the following multiple-frequency admittance model [27] Y m (s) = G l (s) where and The resulting admittance models are verified using a great number of consistent simulated AMs performed at different SSOPs. Due to space limitations, the results are presented only for a single-cell full-bridge VSC employing MSMU-U-DPWM. Experimental AMs are performed for the same case.

B. Simulated Admittance Measurements and Benchmarking
Simulated AMs are performed using MATLAB Simulink environment, in the same way as in [27]. The VSC used for the following validations is modulated using the MSMU-U-DPWM and its hardware parameters are given in Table II. As an example, a proportional-resonant current controller is used. Its s-domain   Table I (25) where w 1 is the angular fundamental frequency, k p and k r are proportional and resonant gain, respectively, set as in [27] to achieve the crossover frequency f c = 0.05f s . In Fig. 11, the simulated AMs are compared with the analytical predictions, for different SSOPs. Operation around the different SSOPs is achieved by imposing an adequate bias voltage at the output of the converter, V o = (2M − 1)E. For analytical predictions, the admittance model from (22) is used with the G DPWM from (20). The infinite sum in (22) is replaced by a finite sum of 1000 elements. According to the presented results, the proposed model accurately predicts the AMs up to four times the NF.
In order to illustrate the importance of using the appropriate DPWM model, in Fig. 12, the simulated AMs at M = 0.55 are compared against the multiple-frequency admittance model (22) obtained with different DPWM models. The presented results clearly show that neither the ZOH nor the pure delay model can be used to accurately predict AMs for MSMU-U-DPWM. For a precise prediction of the system's behavior, the proposed MSMU-U-DPWM model is essential.

C. Experimental Admittance Measurements
As a final verification, an industrial full-bridge VSC modulated using MSMU-U-DPWM and the VSC described in Table II is used for the experimental AMs. The input voltage is provided by the Keysight RP7962 A dc power supply.
The control system is implemented on an NI sbRIO-9606, which is based on a Xilinix Zynq 7020 all programmable system on chip. The inductor current is sensed by a custom interfacing board based on a shunt resistor. The board uses conditioning circuits, a 12-bit AD9226 ADC module by Analog devices, and digital isolators. The DPWM clock runs at 160 MHz.
Admittance is found by injecting a voltage perturbation at the PCC and measuring the current response, as in [27]. The sinusoidal perturbation voltage is generated using the MP118 power operational amplifier from APEX. The perturbation is injected at 21 different frequencies, one at a time, starting from 6 kHz and up to 41 kHz. The perturbation voltage is calculated to obtain at least 100 mA of the perturbation component of i, to achieve a good measurement resolution. The inductor current i and the PCC voltage v pcc are measured using a Tektronix 5 series oscilloscope with a data length of 40 ms. The FFT of i and v pcc is performed in MATLAB to obtain the spectral components of i and v pcc at the perturbation frequency. These components are then used to calculate the admittance at the perturbation frequency. More details on the measurement procedure can be found in [27].
In Fig. 13, the experimental AMs obtained at M = 0.7 are compared to the proposed admittance model. As seen, the analytical model predicts the experimental AMs well up to twice the NF. This attests to the accuracy and robustness of the proposed model.

VI. CONCLUSION
This article addresses accurate small-signal modeling of phase-shifted DPWMs used in MC-VSCs. The operating-pointdependent pulse-to-continuous s-domain transfer functions of U-, BPS-, and UPS-DPWM for MSMU, MSDU, and MSSU strategies are derived analytically and verified in simulations and experimentally, up to four times the NF. Comparison with models typically considered in the literature is provided to highlight the accuracy obtained. It is shown that for lowfrequency analyses, the ZOH, pure delay, and proposed DPWM models can be used indistinguishably, since they all predict the same phase response and nearly the same magnitude response, close to unity. However, as the frequencies of interest approach one-sixth of the update frequency, the use of the presented DPWM models becomes essential for system modeling. As an application example, which illustrates the importance of accurate DPWM models, the admittance of a single-cell, fullbridge, VSC modulated using MSMU-U-DPWM is modeled, simulated, and experimentally measured.
Similarly to the MSDU, the MSSU models do not depend on the number of cells. Thus, (26) and (27) are also valid for the case of a single cell, which is in agreement with the results from [26]. As seen from (26) and (27), compared to MSDU, the MSSU strategy introduces two times larger modulation delay. The derived MSSU-DPWM models are verified by comparing them with the simulated FRMs, up to four times the NF. The results are not shown because of space limitations.

APPENDIX B
In order to avoid shoot-through faults within one leg of the converter, the dead-time is introduced. With the goal of providing an insight into the impact of the dead-time on DPWM's small-signal dynamics, an approximate representation of deadtime effect is considered [21]. During dead-time, the switchednode voltage is assumed to be constant and defined by the sign of the output current I. Although this representation is often used in the literature, it is important to note that it neglects nonlinear phenomena that may appear [35]. Since, due to dead-time, the cell's output voltage v oi is no longer defined only by x ai , x bi , and E, the output voltage v o must be used instead of x eq in (6) Using the same methodology as in Section III, general expression for the extended DPWM model, which includes dead-time, is obtained G DT DPWM (s) = 1 2 e −s(τ R +t DT sgn(I)+1 2 ) + e −s(τ F −t DT sgn(I)−1 2 ) (29) where sgn is the sign function, t DT is the imposed dead-time value, and τ R and τ F are determined based on the chosen modulation and control strategy, just like in Section III. By substituting the appropriate values of τ R and τ F in (29), the extended DPWM models can be obtained for all considered MSMU-and MSDU-DPWMs. Substitution of t DT = 0 in (29) yields the same expressions as those reported in Table I. The proposed extended DPWM models are verified for several different dead-time values and both signs of the output current by comparing them to the simulated FRMs, up to four times the NF. The results are not shown because of space limitations. It was shown that for dead-time values below t DT ≈ 0.01T pwm , the impact on the modulator's small-signal dynamics is negligible. Nevertheless, it should be noted that the model from (29) does not take into account the nonlinear impact of the dead-time, which affects the damping of the system [35].