Single-Input Quadruple-Boosting Switched-Capacitor Nine-Level Inverter with Self-Balanced Capacitors

This paper suggests a single-input switched-capacitor Nine-level inverter configuration advantaging from quadruple voltage-boosting ability, natural voltage balancing of capacitors, and reduced components per level. Also, the single-source character of the proposed topology makes it cheaper and more compact. The cascaded version of the suggested topology has also been introduced, by which high boosting factors, as well as large number of steps, can be obtained. The proposed topology can effectively supply the resistive-inductive or pure inductive load types. The capacitors’ impulsive-charging-current issue has been solved by simple small-inductance-based inductor-diode (L-D) networks. The comparative analysis affirms the fewer device-usage in suggested configuration per equal gain or level count than existed structures, resulting in less size and cost. The usage of Nearest-Level modulation guarantees the low-frequency operation of semiconductors and reduces the switching losses. The comparative analysis and experimental outcomes affirm the competitiveness and accurate functionality of suggested configuration.


I. INTRODUCTION
The Multi-Level Inverters (MLI)s are well-known for highquality output voltage and low voltage stress on switching devices [1]. The conventional MLIs are mainly categorized as: A) Cascaded H-Bridge (CHB), B) Diode-Clamped (DC), and C) Floating-Capacitor (FC) inverters. The CHB inverters produce many voltage steps but have no voltage boosting ability and usually require numerous DC supplies and power semiconductors [2][3][4]. Also, the DC and FC inverters demand more clamping-diodes, DC-link, or floatingcapacitors to acquire increased-levels. The requirement of voltage sensors and complex strategies for balancing the charge of capacitors is another shortcoming of NPC and FC inverters [5,6].
To increase the number of voltage steps in MLIs, more DC supplies, semiconductors, and driver circuits are required, which leads to a bulky, heavy, and costly converter. So, many studies have focused on presenting reducedcomponent structures like [7,8]. In [9], the authors aimed to decrease the semiconductors (and gate-driver circuits). As aimed in [10,11], reducing the number of DC supplies (as large and expensive parts) is more beneficial than other components. The utilization of Switched-Capacitor Cells (SCCs) in MLIs can provide a higher number of levels without the need to increase DC sources. This critical feature improves output voltage quality and simultaneously keeps the converter as compact/cheap as possible [12,13]. From viewpoint of voltage boosting ability, the Switched-Capacitor Multi-Level Inverters (SCMLIs) are classified into boost (step-up), step-down or unity-gain categories. The [14,15] present two step-down converters, where the peak voltage (Vo,max) is lower than total inputs. The topologies presented in [16][17][18][19] are examples of unity-gain converters with equal peak output voltage and summation of input sources. Usually, the MLIs utilizing capacitors only in DClink(s) produce unity gain. But, the step-up or boost SCMLIs like [11,[20][21][22][23][24] have voltage boosting ability and can produce larger voltage than total inputs. The voltage boosting ability becomes very vital for grid-tied SCMLIs fed by Photovoltaics (PVs) or Fuel Cells (FCs), where the input

II. PROPOSED 9-LEVEL INVERTER
The proposed switched-capacitor-based inverter (shown in Fig. 1) is composed of level generation and polarity generation units. The level generation unit is formed of a single DC source, single-diode, two capacitors, and seven switches (MOSFETs), as (1). The S1 -S2 are bidirectional commonsource switches. The others are unidirectional switches. The end-side H-bridge plays the role of the polarity generation unit.  Table I shows different switching states of switches, forward/reverse bias of D1 diode, and charge/discharge mode of C1-C2 capacitors. The green up and red down symbols represent the charging and discharging modes, respectively. Fig. 2 displays various operational modes of the suggested circuit. As seen, the positive and negative voltage steps are generated respectively by turning on the (H1, H4) and (H2, H3) switch pairs. Also, there is only one redundant state, which leads to zero voltage level.
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. (e) (f)  States 5-6 (Figs. 2(e) and 2(f)): The Vo = ±2Vdc voltage steps are generated by a series connection of input source and C1 capacitor. At the same time, The C2 capacitor is paralleled with the cascaded input source and C1 capacitor. So, the C2 capacitor is charged to vC2 = Vdc + vC1 = 2Vdc.

States 7-8 (Figs. 2(g) and 2(h)):
In order to synthesize the Vo = ±3Vdc on the load, the input source is cascaded with C2 capacitor. Meanwhile, the parallel connection of the input source and C1 capacitor keeps its voltage on vC1 = Vdc.
States 9-10 (Figs. 2(i) and 2(j)): Finally, the Vo = ±4Vdc voltage steps are provided by cascading the input DC source, C1 and C2 capacitors. Table I and Fig. 2 show that the suggested converter can produce 9 voltage steps (including 0, ±Vdc, ±2Vdc, ±3Vdc and ±4Vdc) with a maximum output voltage of Vo,max = 4Vdc. So, the voltage gain (G) of the suggested topology is equal to 4. Also, as shown in (2)  The Voltage Stress (VS) on the semiconductors has been shown in Table II. The H-bridge switches tolerate the Vo,max, but operate at low-frequencies, leading to limited switching losses.

III. PROPOSED CASCADED STRUCTURES
According to Fig. 3, the suggested basic 9-level inverter can be extended in two forms to achieve an increased number of levels: First extended topology (T1), which employs multiple H-bridges ( Fig. 3(a)), and Second extended topology (T2) that applies single H-bridge ( Fig. 3(b)). These structures are explained in the following.

A. 1 ST EXTENDED TOPOLOGY (T1)
As evident from Fig. 3(a), the number of required devices in proposed first extended topology are as (3): This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.
For level-count maximization, the DC-sources' voltage is decided as (4). The DC-sources' variety is n.
Where, the Vo,max j denotes the maximum output voltage of j th cascaded unit. Also, the Vi represents the input source of The maximum output voltage of each unit, as well as the whole cascaded structure, are computed as (5). 1 ,max ,max ,max 1 4 4(9) , The voltage-levels and gain are as (6)-(7), respectively.
,max 1 The TVS for first extended topology is calculated from (8). ,, The Average Voltage Stress (AVS) on switches/diodes of first extended topology is as (9).

B. 2 ND EXTENDED TOPOLOGY (T2)
The 2 nd extended structure is shown in Fig. 3(b). The number of different components has been presented in (10 For level-count maximization in 2 nd extended structure, the size of DC-sources is decided as (11).
The peak output voltage of each unit and the total output voltage are shown in (12). 1 ,max ,max ,max 1 4 4(5) , According to (12), the level-count and gain of 2 nd extended structure is computed respectively from (13) and (14).

IV. DESIGN OF CAPACITORS
The proper determination of capacitances leads to low voltage ripple and power loss in capacitors. The capacitors are designed such that their voltage ripple during Longest Discharge Interval (LDI) be limited to the desired value (ΔVC). According to Fig. 4, the LDI of C1 capacitor occurs during the generation of ±4Vdc. Also, the LDI of C2 capacitor happens at ±3Vdc and ±4Vdc. The beginning and ending of LDI of C1 capacitor are θ4 and π -θ4, respectively. Also, the LDI of C2 capacitor starts at θ3 and finishes at π-θ3. So, the duration of LDI of C1 -C2 capacitors are θC1 = π-2θ4 and θC2 = π -2θ3, respectively. From (17), the capacitances are determined to limit their voltage-ripple to ΔVC. Note that Io,max: maximum load current, θC: duration of LDI of C capacitor, cosφ: load power-factor, f: fundamental-frequency, ΔVC: capacitor's voltage-ripple.

V. SUPPRESSION OF CAPACITORS' CHARGING CURRENT
The capacitors' impulse charging current is one of the main challenges associated with switched-capacitor-based multilevel inverters, which subject the semiconductors to large current stress and increase the losses. In this study, the Ci's charging-current is restricted by inductor-diode (Li -Di') cells, as Fig. 5. The presented equivalent circuits show that the This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. limiting inductors (Li)s are place on the charging path of capacitors, leading to lower charging currents. But, at discharging modes, these charge-limiting inductors are bypassed by the reverse diodes (Di)s.

VI. NEAREST LEVEL MODULATION (NLM)
In recent years many different modulation techniques have been presented for MLIs. This paper employs the "Fundamental Frequency" or "Nearest Level" modulation technique, which profits from generality, simplicity, ease of implementation, fast operation speed and low-frequency operation of semiconductors, and reduced switching losses [9]. A sinusoidal reference (Vref = Arsin(ωt)) waveform with an amplitude of Ar and frequency of f = ω/2π = 50[Hz] is compared with producible levels (0, ±Vdc, ±2Vdc,•••, ±NPVdc), where 0 < Ar ≤ NP and the NP denotes the maximum positive level. The control block diagram of "Nearest Leve" modulation techniques as well as resulted switching pulses have been shown in Fig. 6. It is seen that the H-bridge switches (H1 -H4) operate at fundamental frequency. The other remaining semiconductors also operate at low frequencies. (a)

VII. COMPARISONS
This part compares the suggested topologies with existed SCMLIs from viewpoints of level and device count, voltagestress on semiconductors, voltage-boosting capability and efficiency. In Table III, the suggested basic 9-level inverter is compared with similar 9-level inverters.
As seen, the proposed basic topology requires fewer total switches and diodes than other counterparts for producing 9 levels. Among selected topologies, the [32] utilizes two DCsources, while the others and suggested basic configuration use on a single DC source. Table III confirms that the proposed basic topology employs only two capacitors (the same as [32,35]), while the others use 3 capacitors. According to Table III, the proposed basic topology and [31,32,34] use minimum total devices, where the [22] utilize maximum devices. As seen from Table III, the TVS on semiconductors of suggested basic inverter is higher than other counterparts, which is considered as its main drawback. Among selected topologies, the [22] has the least maximum voltage stress (=0.25Vo,max) on its semiconductors than other structures. The maximum voltage gain (quadruple gain) belongs to proposed basic inverter and [22,30,31,34,35], where the [32] has the least gain (double gain).
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. Based on Table III, none of semiconductors in [22,35] tolerate Vo,max. In [32,34] two semiconductors tolerate Vo,max, while this amount in proposed basic inverter and [30,31] is four. Based on Table III, none of semiconductors in [22,35] tolerate Vo,max. In [32,34] two semiconductors tolerate Vo,max, while this amount in proposed basic inverter and [30,31] is four.
Table III presents and compares the efficiency of proposed converter with that of [22,[30][31][32][33][34][35]. As seen, the efficiency of topologies presented in [22], [30] and [31] are 88.9%, 91.5%, and 91.6%, respectively at 74[W], 138[W], and 60[W]. The efficiency of proposed converter in this range of output power is about 90.9% to 93.5%, which is higher than the reported efficiency of [22,30,31]. The reported efficiency range of [32] across output power range of 50[W] to 500[W] is [90%-94.5%]. During almost the same output power range, the efficiency of proposed topology is about 90.6% to 95.5%, which is slightly higher than that of [32]. Meanwhile, the reported efficiencies of topologies presented in [34,35] are higher than the efficiency of proposed converter.
The proposed basic inverter and [30,31] use an H-bridge, while the [32] use a developed H-bridge and [34,35] employ two half-bridges for negative voltage generation. This feature is realized inherently in [22].
The proposed cascaded inverter and generalized counterparts presented in [10,28,30,33,36,[38][39][40][41] are compared in Table IV. Fig. 7 present the comparison results as plots. The topologies presented in [38,39] utilize 2 DC sources, but the proposed topology (T1, T2 and P1) and [10,28,30,33,36,40,41] demand only a single DC source at basic version. This further decreases the overall weight, expense and volume of the converter (Fig. 7(a)). Fig. 7(b)-7(c) show that the proposed T1 and T2 topologies and [30,36] require equal or less switching devices (switches and diodes) than other counterparts, which accordingly leads to less gate-driver circuits, less complexity, low size and low losses. Based on Fig. 7(d), the proposed T1 and T2 topologies utilize the second least number of capacitors to produce equal levels with similar counterparts. Also, it is seen from Fig. 7(e) that the proposed T1 and T2 topologies provide the third-highest (after [30,36]) ratio of levels to total devices (NTC = NDC + NSW + NGD + ND + NC). This can result in a compact and less-complicated structure. As seen from Fig. 7(f), the gain of converters presented in [36,38] increases at extended versions, but the gain of converters presented in [10,28,30,33,[39][40][41] remains constant. Among these constant-gain converters, the proposed T1, T2 and P1 topologies have the maximum step-up capability. According to Fig. 7(g), the Average Normalized Standing Voltage (ANSV) of the proposed symmetric converter (P1) is quite low, while this amount in proposed asymmetric (T1 and T2) converters is rather high. Fig. 7(h) shows that the ANSV of converters reduces by an increment of cascaded units. Also, at equal units, the ANSV of proposed T1, T2 and P1 topologies is lower than that of [33,36,38,39], which is desirable. The proposed topology and [30,31] require an H-bridge to create a bipolar voltage-waveform. Thus, the H-Bridge's switches are exposed to Vo,max. The negative voltage-level generation in [32] is achieved through a developed-H-bridge, where two switches tolerate Vo,max. The [34,35] employ two half-bridges and the [33] inherently produce the negative voltage levels. The number of semiconductors tolerating the maximum output voltage (NMVS) in [33], [34] and [35] are 4, 2 and 0, respectively. The [35] has the least TVS, because none of its semiconductors tolerate the Maximum Voltage Stress (MVS) of Vo,max.

VIII. LOSS AND EFFICIENCY ANALYSIS
The losses occurred in switches, diodes, and capacitors form the total power loss of the converter. The power dissipation in each component is demonstrated in the following.

A. SWITCHES
The switches of the proposed topology have been realized by MOSFETs, which can be modelled with an on-state resistance (Ron,T or Ron,H). The conduction loss of switches happens at on-state resistances. Also, the switching losses occur during switch on-off transitions. The switching losses depend on voltage stress (Vstress), average current (Iave), turn on and off times (ton, toff) and switching frequency (fs) of a switch. The total switch losses (conduction and switching) can be computed from (18 The total power losses, as well as the efficiency (η) of suggested, can be achieved from (21) and (22) Fig. 8 displays the laboratory-scale prototype implemented to verify theoretical analysis and correct performance of suggested basic inverter. Table V shows the experimental parameters. The load power factor is cos(φ) = cos(arctan -1 (Lω/R)) = 0.9336. According to section 4, the LDI of C1 and C2 capacitors are respectively θC1 = π -2θ4 and θC2 = π -2θ3, where θ4 = 67.5º and θ3 = 45º. So, the duration of LDI of C1 and C2 capacitors are, respectively θC1 = 45º and θC2 = 90º. The C1-C2 capacitors have been designed such that to limit the voltage ripples to 5% (ΔVCi = 0.05VCi, i = 1, 2). Based on This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.     The peak value (Vo,max) is around 118 [V]. Note that the 3 volts difference between theoretical and measured maximum output voltage originates from voltage drops on current flow-path devices. Due to the pure resistive nature of load in Fig.  9(a), the load voltage and current waveforms are stepped and in-phase. The phase-difference of φ=arctan -1 (Lω/R) = 21º between Vo and Io in Fig. 9(b) approves the ability of suggested inverter on feeding resistive-inductive loads. Fig.  10 presents harmonic-spectrum of output-voltage.

FIGURE 10.
Harmonic spectrum of the output voltage.
As seen from Fig. 10, the even-order harmonics have been eliminated from the output voltage. Among available harmonic orders, the 21 th , 17 th , 25 th and 23 th harmonic orders have the highest magnitudes, which are respectively about 3.1%, 2.97%, 2.88% and 2.7% of fundamental harmonic. These high order harmonics can be eliminated through a small filter. The Total Harmonic Distortion (THD) of the suggested 9-level inverter is about 8.53%. Fig. 11 displays the current and voltage waveform of C1 -C2 capacitors.  Voltage/current waveforms of (a) C1, (b) C2, capacitor.
As expected, the voltage across C1-C2 capacitors has been naturally balanced on 28  acceptable. Fig. 12 indicates the dynamic operation of the suggested topology during sudden load change conditions. It is seen that during decrement of load to half (from 120 [] to 60 []), the peak load-current is doubled without considerable change in output-voltage. While changing load from 60 [] to 120 [], the peak load-current reduces to half, but its voltage remains unaltered. This confirms the appropriate dynamic performance of the suggested topology during sudden load change conditions.

X. CONCLUSION
This paper has proposed a basic switched-capacitor 9-level inverter that is extendable to higher levels. The single-source nature, quadruple voltage-boosting ability, capacitors' natural charge-balancing, increased levels per device, and capability of feeding low power factor (resistive-inductive or inductive) load types are the main advantages of the suggested topology. The H-bridge switches tolerate Vo,max, but due to their fundamental-frequency operation, their switching-loss is  suppressed. The capacitors' impulse-charging current has been reduced by a small-inductance-based L-D network. The output voltage THD of the suggested topology is about 8.5%. The comparative analysis confirms that the suggested topology has higher ratios of a number of levels and gain to devices, which is an important advantage. The efficiency of an implemented laboratory-scale prototype of the suggested topology for Vdc = 30 [V] is about 90.9%, which is acceptable. Two extended versions of the suggested basic topology have been introduced to achieve more levels and voltage-gains. The experimental outcomes validate the proper performance of the suggested switched-capacitor 9-level inverter topology.