Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution. High-speed feedback pathways relying on Miller capacitors and current buffers are implemented within the amplifier scheme to push the non-dominant poles to high frequencies for small to medium load capacitors. A small resistor is also shared between the two pathways to improve the stability regardless of the load capacitor. A serial R-C branch is then added to extend the lower limit of load drive capability to small load capacitors. Gain margin is, for the first time in literature, analytically evaluated and included in the design phase. A prototype of the proposed amplifier is fabricated in 65-nm CMOS process with active area of 0.0017 mm2 and 1.15 pF total compensation capacitance. It can drive the load capacitor range from 200 pF to 100 nF, while drawing a quiescent current of 7.4 μA from a 1.2-V input voltage supply. A unity-gain frequency of 1.67 MHz was measured with an average slew-rate of 1.31 V/μs, when the proposed amplifier is wired in unity-gain configuration to drive a 500-pF load capacitor.


I. INTRODUCTION
A large DC gain is a prerequisite for realizing operational transconductance amplifiers (OTAs) with high accuracy. A high DC gain is, however, difficult to achieve in nano-scale CMOS technologies, since scaling MOS devices decreases their intrinsic gain as well [1,2]. In conventional CMOS technology, the DC gain of an amplifier could be readily increased by stacking more transistors in a cascode configuration. The reduced power supply of the integrated circuits (IC) in modern technology nodes, however, leaves little voltage headroom for stable operation of cascoded devices, rendering more convenient the use of cascaded gain-stages to construct multistage amplifier topologies for high-precision applications. Nonetheless, additional lowfrequency poles in the voltage-gain transfer function of cascaded amplifiers complicate their stability in feedback configuration. Many frequency compensation techniques have thus been introduced [3][4][5], allowing the researchers to propose new design procedures depending on the application requirements [6][7][8][9][10][11][12]. Multistage OTAs are the fundamental block of many critical modules in an amplifier, removing the Miller capacitors comes with degraded power efficiency, since extra feedback loops and more biasing current would be required to compensate the inner gain-stages.
Alternatively, single-Miller compensation (SMC) resorts to the solutions which construct a stable multistage amplifier using one Miller capacitor, CC, only [33,36]. In this category, cascode-Miller compensation topologies (Miller compensation employing current buffer) exhibit better power/area efficiency for those OTAs driving large capacitive loads, since the required CC would be a function of CL rather than CL in the classical Miller compensation [37][38][39][40]. Cascode-Miller compensation can be combined with local impedance attenuation (LIA), in the form of a serial RC branch, to extend the drivable load range of a three-stage OTA to small load capacitors [37]. Similar approaches demonstrated maximum efficiency for ultralarge capacitive loads but still show limited efficiency for small CL [39,41,42].
In view of this shortcomings and in order to enable very wide capacitive load range with low quiescent power and small active area, this work introduces a compensation topology based on Hybrid Cascode frequency compensation, local Impedance attenuation and Resistor (HCIAR) for three-stage amplifiers and provides the analysis and design insights to drive light to heavy capacitive loads. The proposed OTA, in particular, is CC compensated for small to medium load capacitors, becoming smoothly CL compensated for large capacitive loads. As a result, the load capacitor range is extended to about 500× from 200 pF up to 100 nF using an overall compensation capacitor of 1.15 pF in 65-nm CMOS technology. In addition to analytical discussions, simulation and measurement results will be reported and compared with the prior art in the rest of this paper. The main contributions of this work are summarized below: 1. By combining the advantages of the compensation topologies introduced in [37] and [39], a novel compensation strategy is introduced exploiting also an additional compensation resistor in the main compensation path; 2. Gain margin is, for the first time in literature, analytically evaluated and included in the design phase; 3. A general design procedure to guarantee stability of the amplifier for both small and large load capacitors is introduced; 4. Experimental results show an outstanding 500×capacitive load driving range without reconfiguring the amplifier which, to the best of authors' knowledge, is the highest reported in literature.
The paper is organized as follows. At first, Section II describes the conceptual block diagram, principles of operation and stability conditions of the proposed compensation strategy. Next, in Section III we discuss about the circuit implementation, large-signal operation and design guidelines of the amplifier. Simulation and measurement results are then presented in Section IV, where a comparison with the state-of-the art is carried out. At last, conclusions are drawn in Section V. Some ancillary calculations and a comparison between the proposed solution and similar works in the literature are included in the Appendices. Fig. 1 shows the proposed HCIAR amplifier diagram. It is composed of a differential first stage, a non-inverting second stage, and an inverting third stage with the equivalent transconductances gmi, gm2 and gmL, respectively. Each stage output resistor and capacitor are also modeled by Ri and Ci, where I =1,2,3. As it will be shown in the next subsection, the feedforward stage gmf, has a negligible effect in the amplifier transfer function but is added to implement a class-AB output stage capable of driving CL with increased charging/discharging rate [40].

A. AMPLIFIER DIAGRAM
1st stage 2nd stage 3rd stage 0.5 g mi 1 g mC

FIGURE 1. Conceptual block diagram of the proposed HCIAR amplifier.
Frequency compensation is accomplished mainly by a single Miller capacitor which is equally split into two parts, CC/2, to create a dual feedback network from the output to the first stage. Going forward, we will show that such arrangement yields larger non-dominant poles with smaller quality factor, Q, in contrast to a single feedback configuration made by a monolithic CC. Superior stability margins are thus achieved compared to the prior SMC solutions [24,37,38,40,42].
What's more, two current buffers with transconductance gmC and input resistance 1/gmC are cascaded with Miller capacitors to assist in feeding the output compensating current back to the first stage. The reduced input resistance 1/gmC of the two current buffers lightens the loading effect of the Miller capacitors on the output terminal which leads to extended bandwidth. The described feedback pathways share a small compensation resistor denoted by RC, through which an extra left-half plane (LHP) zero is created and used for improving stability by introducing some phase lead to the external loop. Besides the above-mentioned This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ components for frequency compensation, HCIAR includes a serial RC branch at the second stage output (RD and CD). Aimed at reducing the Q-factor of the non-dominant poles, the corresponding branch is meant for decreasing the lower limit of CL by increasing the gain margin (GM) in the small load capacitors.

B. TRANSFER FUNCTION
An estimation of OTA open-loop transfer function allows exploring its stability and bandwidth variations as a function of the load capacitor. Using the results reported in Appendix A and under the assumptions that: 1. the equivalent transconductance of all stages is much greater than their output conductance (gmi,gm2,gmL>>1/Ri); 2. the nulling resistor RC is much lower than RD and both are much smaller than the output resistors (RC << RD << Ri); 3. the compensation capacitors are much lower than the load capacitor and all are much larger than the parasitic capacitors (CL >> CC, CD >> Ci), the simplified amplifier transfer function, using the methodology described in [43], can be expressed by is the DC gain and is the magnitude of dominant pole frequency. The Q-factor and center frequency of standard second-order polynomial in the denominator of (1) are respectively expressed by Finally, the magnitude of the remnant poles and zeros is given by 4 Pole-zero map of HCIAR amplifier as CL is varied.
From (6) and (10) it is apparent that there is an inherent pole-zero cancellation due, as usual, to the serial RC branch at the second stage output.
Referring to (4) and (5), the following points can be stated. 1. Enlarging the load capacitor decreases the Q-factor of the pole pair, generating ultimately real poles. 2. The coefficient "2" in (4) and (5) is in favor of amplifier performance; originating from the parallel feedback loops in the proposed configuration, this factor moves the nondominant poles to higher frequencies and reduces their Qfactor as compared to a single feedback loop. 3. The effect of RD on both (4) and (5) is worth investigating. The Q-factor is now proportional to RD rather than R2 in the absence of the RC circuit at the second stage output [37,38], enabling to reduce Q via RD, without sacrificing the DC gain of the second stage. Too small RD is, however, unsuitable since it moves 0 to low frequencies. Hence, its value should be tuned for an optimal location of the pole pair depending on the application requirements.
The first LHP zero, z1, depends on either RC and RD, and can be used to counteract part of the negative phase shift caused by non-dominant poles. The second right-half plane (RHP) zero, z2, is inversely proportional to the parasitic C1. It is thus positioned well beyond the gain-bandwidth product (GBW) and can be pushed further to the higher frequencies by increasing RC. Besides, from the expressions of A0 and p-3dB in (2) and (3), the GBW is given by The above relation simplifies to the usual expression gmi/CC for small to medium load capacitors (i.e., CL <<gm2gmLR1R2CL), changing smoothly to gmigm2gmLR1R2/CL This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. for heavy capacitive loads. The GBW is thus scaled down with CL for CL>>gm2gmLR1R2CL, which shows that the proposed amplifier is compensated by the load capacitor rather than by CC for large load capacitors. Fig. 2 shows the pole-zero map of HCIAR amplifier, and the changes of its pole magnitudes with respect to CL. The complex and conjugate p2and p3 become real for higher CL, while the dominant pole moves closer to the origin consistent with (3).

C. ANALYSIS OF STABILITY
The phase margin (PM) related to (1) is carried out in the eq. (33) in Appendix B, which allows finding the PM limits when CL tends to zero and infinity as The limits in (12), (13) can be made positive and sufficiently large by properly sizing the contributing components from the compensation network. In particular, the stability of the OTA will be guaranteed for ultra-large load capacitors by adequately enlarging the PM limit in (13). With reference to (36) in Appendix B, the GM becomes negative by letting CL approach to zero. The closed-loop stability can thus be ensured only for the load capacitors larger than a threshold. Indeed, to get a positive GM we must fulfill the condition ( ) which yields a minimum CL given by A more conservative choice of the minimum CL is according to the maximum tolerable Q-factor, Qmax, of complex and conjugate non-dominant poles, since decreasing CL increases accordingly the Q-factor as is evidenced by (5), thus yielding Both (15) and (16) indicate that the minimum capacitor of the proposed structure is dependent on RD rather than R2 in the absence of the RC circuit at the output of the second stage. The serial RC branch thus lowered the minimum CL owing to the additional GM recovered by this block at small capacitive loads. Moreover, the GM is monotonically increasing by letting CL approach infinity according to (36) The above relation shows that the stability for the ultralarge load capacitors is affected only by the PM and not the GM. Fig. 1, where the original gm-stages are implemented by their counterparts in dashed lines. It consists of an input folded-cascode stage, a current-mirror second stage with a positive gain factor for the negative feedback sign of the external loop, and a common-source third stage. The first stage is an inverting differential amplifier made up of M1a−M1b as the input pMOS pair, M3a−M3b and M4a−M4b as cascode devices, M5a−M5b as current mirror for fully-differential signal to single-ended conversion, and M0, M2a−M2b as biasing current sources. The second stage is made by M0 as input device, M7a−M7b as current mirror, and M8 for bias generation. Transistor M7c is also exploited to increase the equivalent transconductance of the second stage [31,37].

FIGURE 3. Circuit implementation of the HCIAR amplifier.
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication. The output stage is formed by M9 and M10 with rail-to-rail voltage levels for maximizing the OTA dynamic range in low-voltage environment. Push-pull operation is implemented through M10connected to the first stage output, whose transconductance is equivalent to gmf. The components used for frequency compensation are the serial RD and CD, dual CC Miller capacitors, and RC. Hybrid cascode Miller compensation has been implemented by the Miller capacitors coupling the left-hand side of RC and the source of common-gate M3a and M4a devices, through which the gmC stages in Fig. 1 are realized without any power overhead.
In the analysis carried out in Section II, it was assumed that the transconductance of transistors M3a and M4a is equal. Although perfect matching can be hardly met, being the two devices a nMOS and a pMOS transistor, respectively, it is worth noting that feasible mismatch percentages between the transconductance of these devices changes slightly the location of the poles and zeros derived in Section II. Detailed analysis of mismatch between the two feedback transistors is carried out in Appendix C, where it is shown that the location of the poles and zeros would be changed slightly by the mismatch between the transconductances of M3a and M4a.
Contrary to the asymmetrical compensation network that can be made by the whole CC [37,38], a balanced operation is resulted by the proposed arrangement during the rising and falling of the output voltage. Further comparison between the proposed work and similar solutions in the literature is left to Appendix D.

B. LARGE-SIGNAL OPERATION
The setting response is impacted by the OTA large-signal operation and, in particular, its slew rate (SR) besides the small-signal performance metrics like the stability margins and the GBW. Defined as the highest changing rate of an output voltage, the SR depends on the maximum biasing currents available to charge and discharge the capacitors lumped at the different nodes of the circuit.
In Fig. 3, by denoting IA1IC,IA2I2a, and IA3IL as the maximum currents that can be delivered to charge/discharge the load capacitors, CL1CC/2+CC/2=CC, CL2CD, CL3CD+CL, of the first, second and third stage, respectively, and assuming that the load and compensation capacitors are much higher than the parasitics, the SR can be approximated as the minimum between the slew rate for the first, second and third stage, thus: The overall SR is likely limited by SR1 for lighter CL, becoming identical to SR3 for the heavy load capacitor range. A push-pull output stage is formed by M10 in Fig. 3, which helps to improve the large-signal operation by modestly increasing the output current for faster changing rate of the output. A slew-rate enhancer may be also added to temporarily boost the load current while driving ultra-large capacitive loads [24].

C. NOISE ANALYSIS
The input-referred noise spectral density, Sn,in, of the proposed HCIAR amplifier is dominated by the first stage in Fig. 3, since the noise contribution of the last stages is divided by the gain factor of the former stages when referred to the input. The main noise components of the input stage are due to the flicker and the thermal noise ofM1a−M1b,M2a−M2b and M5a−M5b. Consequently, the following input-referred noise spectral density is derived: where gm,Mi and Sn,Mi are the transconductance and the noise spectral density of the i-th transistor, respectively. Splitting the Miller capacitor into equal parts and the serial current buffers effectively doubles gmC relative to single-Miller compensation solution. Less biasing current would be then required for prescribed stability margins by assuming unchanged gm/ID factors, enabling to lower the current of M2a−M2b and M5a−M5b and, eventually, their contribution on the input referred noise of the amplifier.

D. DESIGN GUIDELINES
The proposed OTA can be designed in different ways depending on the load capacitor range, and nominal GBW or noise requirements imposed by the application. In this section, we shall describe the main design considerations of HCIAR topology being useful for primitive hand calculations. For simplicity, we assume that CL is not affecting the GBW, thus this parameter can be expressed as gmi/CC 1 . We also assume that the output resistors and capacitors are extracted initially by circuit simulation. Of course, these critical components can be revised/updated recursively when developing an iterative computer-aided design flow.
We start our design procedures by sizing the RC circuit of the second stage output. The main purpose of this block is to overcome the parasitic pole generated by R2 and C2 and to move it to the high frequencies, as is evident from the analysis in Section II. At this purpose, RD and CD should be set such that the second stage output impedance approaches RD within the frequency range of concern, say between 0.1´GBW and 10´GBW. After routine manipulations, these elements can be obtained as [42] 1 Note that this assumption is true if the nominal load capacitor is sufficiently small (usually up to hundreds of pF). This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and The sizing of CC, on the other hand, should be according to the desired location of the non-dominant pole pair.
Choosing 0 equal to ´GBW (where  may be nominally selected between 2 and 3 to allow enough GM and PM for the unity-gain OTA), GBW=gmi/CC can be combined with (4) to get In addition to the center frequency of the pole pair, their Q factor also influences the time and frequency response of an OTA. Choosing Q=2/2 is convenient for many applications since it shapes the frequency response according to the Butterworth approximation with maximally flat band, hence Substituting gm2gmL from (23) into (22) gives which simplifies (22) into The sizing of gmi and, subsequently, gmC in (24) and (25) is according to the nominal GBW, thus The transconductances gm2 and gmL should then be evaluated such that (23) is fulfilled. Despite the usefulness of (23) as the starting point, simulations should be carried out to track the variations of GBW, PM and GM across the capacitive load range for the transconductance values to be optimized accordingly.
In the end, gmL should be also set to mf mL gg = in order to maintain the balance of the last stage. The resistor RC is finally sized such that the first zero is positioned at the desired ´GBW location higher or lower than the GBW frequency [7], thus from (8) and (26) we get It is also important to check the frequency of the second RHP zero, z2, after RC being determined from (28), since its location also depends on RC in the transfer function. Choosing |z2|>10´GBW as a safe margin to avoid the negative phase shift of z2 deteriorating the frequency response, we get 2 2 5 10 After the analytical phase, simulation of the parasitic poles and zeros against the process, voltage and temperature (PVT) variations is required to fine tune the compensation elements for the increased robustness in presence of these inevitable changes. A prototype of HCIAR amplifier was implemented based on the above design procedures, and with the aid of an algorithm which optimizes the transistor aspect ratios for minimum silicon footprint and power consumption given the nominal GBW, settling time, DC gain, dynamic range, and capacitor load range [44].

A. SIMULATION RESULTS
Simulations were conducted in a standard 65-nm CMOS technology using MOS devices operating at 1.2-V power supply, in order to validate the HCIAR amplifier design. The design was optimized for minimum power consumption and maximum bandwidth over the load range of 200 pF and 100 nF. The amplifier occupies a total area of 0.0017 mm 2 with the current consumption of 7.4µA. Table I summarizes the device aspect ratios while Table  II reports the performance specifications for the nominal CL of 500 pF, together with DC bias currents, gm values, and output resistors.
The loop-gain frequency response is depicted in Fig. 4(a) for different load capacitors. In line from the limited SR, originating from the limited quiescent current of the output stage, the OTA is found to be unconditionally stable with a minimum CL of 200 pF, which is coherent with the analysis. The dominant pole is initially observed as a function of the Miller capacitance for small capacitive loads, becoming slowly a function of CL for large load capacitors. Fig. 4(b) shows the settling response of the unity-gain amplifier to the rising and falling edges of an input step voltage. It can be observed that the OTA remains stable across the PVT corners, while the nominal and worst-case 0.1% positive/ negative settling time are 1.26/1.40 µs and 1.46/1.71 µs, respectively, according to Fig. 6(c).
The simulated PSRR+/ PSRR-are found as181.7/188.6dB at DC, dropping to 135.1/136.6 dB and 17.75/20.00 dB at 1 KHz and 1 MHz, respectively, for CL = 500 pF. The DC CMRR is also obtained as 71.96 dB. Finally, the equivalent input noise is equal to 172 nV/Hz at 100 kHz.

B. MEASUREMENT RESULTS
The proposed HCIAR amplifier was fabricated in a standard 65-nm process. Fig. 7(a) shows the chip micrograph incorporating the 0.0017-mm 2 layout of the amplifier.
The experimental setup is displayed in Fig. 7(b). It consists of a waveform generator (right-side) and two power suppliers (left side). An oscilloscope, Tektronix TDS5054B, was also used to measure the input and output signals for transient response. Finally, setup configuration involves also a E5061B LF-RF network analyzer (ENA) provided by Keysight technologies, which was used to measure the amplifier response in the frequency domain. Fig. 8 illustrates the loop-gain frequency responses for the CL range from 200 pF to 100 nF. The DC gain is extrapolated as around 107 dB, and the GBW is 2.01 MHz and 0.03 MHz with a phase margin of 60.1 o and 72.7 o for 200 pF and 100 nF load capacitors, respectively. Fig. 9 shows the settling response to a 400-mV input step voltage for the unity-gain OTA. The average SR is measured as 1.86 V/µs and 0.01 V/µs for 200 pF and 100 nF load capacitors, respectively.     Overall, the settling response correlates well with simulation results, but a longer settling time was appreciated due to the loading effect of the experimental setup. Performance parameters have been measured over 6 samples and a good stability is observed being the relative standard deviation lower than 5% in all cases unless for the offset voltage whose average value is 0.28 mV with a standard deviation of 7.24 mV. This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and  Table III presents the performance metrics of the proposed HCIAR amplifier and compares them with the results from some of the state-of-the-art OTAs.

B. COMPARISON
The standard figures of merit, IFOMS=GBW´CL,max/IDD and IFOML=SR´CL,max/IDD, were used to characterize the small-signal and large-signal operations for the maximum load capacitance, while IFOMSA=IFOMS/Area and IFOMLA=IFOML/Area were added to also take into account the silicon area.
With the aim of including in the comparison also the stable and drivable load capacitor range, the figures of merit LR-IFOMSA=IFOMSA/CL,min and LR-IFOMLA=IFOMLA/CL,min are then introduced. A lower total CC was achieved in [24] for comparable current consumptions (0.50 pF vs. 1.15 pF) but the minimum CL for stable operation is limited to 5 nF rather than 200 pF in the proposed implementation.
In the absence of Miller capacitor, the capacitor-less frequency compensation solution in [20], on the other hand, increases significantly the current consumption to maintain stability as compared to this work (185 µA vs. 7.4 µA). The measured DC gain was also limited to about 71 dB for heavy load mode. Similarly, the required current consumption of the design in [18] with a DC gain of 107 dB is comparatively high owing to the conventional Miller compensation solution applied (146 µA). A total compensation capacitance of 3.1 pF was also incorporated to stabilize the amplifier. Overall, the proposed OTA achieved the highest LR-IFOMSA=IFOMSA and LR-IFOMLA among the OTAs listed in Table III, when taking into consideration the range of stable operation, active area, current consumption and small-signal and large-signal operations altogether. ,max ,max 2 ,max 2 ,max 2 ,min ,max 2 ,min This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.

V. CONCLUSION
The stability of multistage OTAs is compromised by the load-dependent position of zeros and poles when driving a wide range of capacitive loads is of concern. An efficient design methodology and, subsequently, a high-performance frequency compensation solution were proposed in this work to improve the operation of three-stage amplifiers with ultra-wide load capacitor range. The proposed compensation network is comprised from identical compensation capacitors for cascode-Miller compensation, a small resistor for positive phase shift and enhanced stability, and a serial RC network for extending the drivable load range to small load capacitors. Verified by analysis, simulation and measurement results, the proposed OTA establishes an optimal stability/bandwidth trade-off over a very wide load capacitor range. The figures of merit related to power consumption, silicon area, and load capacitor range reveal superior performance metrics compared to the previous arts.

APPENDIX A. Simplification of the Amplifier Diagram
The transfer function of the circuit shown in Fig. 1 can be simplified by combining the parallel feedback pathways through identical CC/2 and gmC stages in Fig. 11(a) and merging them in the form of a single CC in series with gmC, as graphically depicted in Fig. 11(b). Indeed, in Fig. 11 whereas in Fig. 11(b), iF can be written as ' ' 12 11 2 // 1 2 1 2 Both models induce the same iF in the output of the first stage, which proves that they are equivalent owing to the symmetry in the original configuration. Consequently, the HCIAR block diagram in Fig. 1 can be simplified as shown in Fig. 11(c) with CC in series with a 2gmC stage.

APPENDIX B. Gain and Phase Margin Evaluation
Neglecting the pole-zero pair z3-p4, the phase margin of the transfer function (1) is expressed by the well-known expression where the approximation holds assuming that z1, z2 and p4 are located at frequencies higher than GBW and recalling that tan(90°-)=1/tan() and that tan(++) tan()+tan()+tan()+… for small , ,… values.
Substituting (3) where PX 0 is the phase crossover frequency.
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.
Considering that in general and for small x and y, eq. (34) can be approximated as Substituting (3)- (11) in (35) yields (36) at the top of the page.

APPENDIX C. Mismatch between feedback transconductances
Being different type of devices with unequal aspect ratios, the inevitable mismatch between the transconductances of M3a and M4a which forms the parallel feedback pathways in Fig. 3 is a concern which requires further investigation. Denoting with gmC1 and gmC2 the equivalent transconductances of these devices, respectively, the general form of the feedback current iF in Fig. 11(a) is obtained as ( ) Let gmC1=gmC and gmC2=gmC+gmC, where gmC models the effect of mismatch, we get ( ) With reference to the above result, Fig. 12 modifies the previously described amplifier model shown in Fig. 11(c). The two diagrams are analogous for the small mismatch errors between gmC1and gmC2 when gmC << gmC+CCs, except that the original gmC prior to the first stage output will be replaced by gmC+gmC in presence of mismatch. By means of the modified amplifier model in Fig. 13, analysis of the transfer function reveals that the location of the poles and zeros is changed slightly by gmC. For instance, the Q-factor and the center frequency of the second and the third poles (Eqs. (4) and (5)) are modified to The block diagram of an improved SMC [33], CLIA [37] and HCFC [39] compensation topologies is shown in Fig. 13. Their transfer function can be approximated by (1) but with the expression of natural frequency, quality factor and zeros summarized in Table IV. For analogous parasitic capacitors and transconductance values and depending on the gain factor gmCRD (or gmCR2), SMC yields a natural frequency much lower than the rest, which is because of the advantage of cascode compensation over the classical Miller compensation. This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.  topologies have a value of 0 which is higher by a factor of 2 and, at the same time, a value of Q which is reduced by the same factor. This means that the amplifiers HCFC and HCIAR achieve the same stability margins with smaller compensation capacitance, and thus lead to GBW and SR improvements.
To get similar performance of HCFC and HCIAR, CLIA amplifier must entail a doubled value of gmC which comes at higher power/area consumption.
However, from Table IV it is apparent that  0 and Q of HCFC is a function of R2. This parameter cannot be set independently from gm2, and in turn, without changing the DC gain of the OTA. In the proposed HCIAR topology, like in CLIA, 0 and Q are a function of RD, rather than R2, which is a physical resistor that can be set according to the guidelines provided in Section III.D.
As a further advantage of the proposed scheme, the first LHP zero, z1, depends on either RC and RD similar to improved SMC, and can be used to counteract partly the negative phase shift caused by non-dominant poles, thus allowing to increase PM for equal CC or reduce CC for equal PM.
Therefore, we can conclude that HCIAR takes advantage of the benefits of SMC, CLIA and HCFC and introduces increased intrinsic performance by exploiting resistor RC.