Cascading CMOS-Based Chaotic Maps for Improved Performance and its Application in Efficient RNG Design

We present a general framework for improving the chaotic properties of CMOS-based chaotic maps by cascading multiple maps in series. Along with two novel chaotic map topologies, we present the 45 nm designs for four CMOS-based discrete-time chaotic map topologies. With the help of the bifurcation plot and three established entropy measures, namely, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient, we present an extensive chaotic performance analysis on eight unique map circuits (two under each topology) to show that under certain constraints, the cascading scheme can significantly elevate the chaotic performance. The improved chaotic entropy benefits many security applications and is demonstrated using a novel random number generator (RNG) design. Unlike conventional mathematical chaotic map-based digital pseudo-random number generators (PRNG), this proposed design is not completely deterministic due to the high susceptibility of the core analog circuit to inevitable noise that renders this design closer to a true random number generator (TRNG). By leveraging the improved chaotic performance of the transistor-level cascaded maps, significantly low area and power overhead are achieved in the RNG design. The cryptographic applicability of the RNG is verified as the generated random sequences pass four standard statistical tests namely, NIST, FIPS, Diehard, and TestU01.


T HE inception of chaos theory is marked by Henri
Poincaré's observation on non-periodic orbits in his study on the three-body problem in the 1880s (translated in [1]). However, to see significant development in chaos theory, the world had to wait for the invention of digital computers that had made the repeated iterative computation easier, and eventually, resulted in Edward Lorenz's seminal 1963 publication [2] on an accidental discovery of chaos in his study on weather prediction [3]. Chaos occurs as a special condition in a nonlinear deterministic dynamic system [4]. Dynamic systems describe the time evolution of one or multiple points in a geometrical space. There are mainly two kinds of dynamic systems: (i) stochastic, when the trajectory of the point is random, and (ii) deterministic, when a mathematical function can exactly predict the future state after a certain time interval. Dynamic systems are called non-linear where the change in output is not proportional to the change in input. Generally, in a non-linear deterministic dynamic system, the time-trajectory of a point eventually reaches a periodic steady-state, after starting from any initial state. In this general case, two very close initial states result in an almost similar steady-state. However, when the parameters of a nonlinear deterministic dynamic system are tuned to its chaotic region then we can observe two special conditions: firstly, the time trajectory never reaches a periodic steady-state, secondly, two initial states -even if they are very close to each other-will eventually follow two very different time-trajectories [5]. The aperiodicity of a chaotic system is distinct from randomness since the time-trajectory is deterministic in the chaotic case where we can always reproduce the same trajectory starting from the same initial state. The initial state sensitivity is popularly known as the 'butterfly effect', after being coined by Lorenz in a lecture [6], as if a butterfly flapped its wings in Brazil a few weeks earlier and as a result, eventually, that minor perturbation has changed the nice sunny weather in Texas into a tornado. This deterministic aperiodicity and the sensitive dependence on the initial state of chaotic systems have proven their utility in numerous security applications such as data encryption [7], random number generation [8], [9], reconfigurable logic [10], [11], Physically Unclonable Function (PUF) [12], sidechannel attack mitigation [13], secure communication [14], logic obfuscation [15] and so on.
Depending on the number of state variables involved, chaotic systems can be categorized into two groups: (i) onedimensional (1-D) maps, where only one function describes the evolution of a single state variable. (ii) Multi-dimensional (multi-D) chaotic maps, where the time evolution of more than one state variable is described with the same number of functions. The nature of time-evolution divides the chaotic systems into two classes: (i) continuous time, where the governing function contains the time derivative terms and time steps of the trajectory is continuous, (ii) discrete-time, where the trajectory evolves in discrete time steps and any next state of the system is a direct function of the previous state. Familiar examples of 1-D discrete-time maps are sine map, tent map, logistic map, and so on. On the other hand, Henon map (discrete-time) and Lorenz system (continuoustime) are examples of multi-D maps. In this work, we focus on 1-D discrete-time chaotic maps.
Regarding security applications, multi-D chaotic maps, with their complex chaotic properties, provide higher security [16], however, they are expensive to implement in hardware. On the other hand, 1-D chaotic maps are simple to implement. One downside is this convenience in the implementation comes with a compromise in security since the output trend can be predictable with low computational cost [17]. Zhou et al. proposed a scheme where multiple 1-D chaotic maps are cascaded together in series to form the final map that shows improved chaotic properties relative to its constituent 1-D seed maps [18]. They have demonstrated superior chaotic performance from their proposed scheme by cascading multiple 1-D maps like sine, logistic, and tent maps. These mathematical maps are suitable for softwarebased applications like encryption algorithms, however, they are not suitable for CMOS (Complementary Metal Oxide Semiconductor) implementations in hardware for applications where there is high constraint in chip area and power. One example of this type of application can be a hardware-based security protocol for edge devices like IoT (Internet of Things). The reported CMOS implementations of classical mathematical maps, including logistic map [19], sine map [20], and tent map [21], are so hardware-hungry that they are not suitable for any low-overhead hardware-security applications. Instead of trying to mimic the characteristic curve of classical mathematical maps, some researchers have been leveraging the built-in non-linearity in MOS transistors and proposing simpler CMOS circuits, with characteristic curves similar enough to classical mathematical functions, which are capable of generating discrete-time chaotic sequences. Dudek et al. proposed the design of two discretetime chaotic maps in a 600 nm CMOS process, in [22] and [23]. It was shown that, each of these two circuit topologies, with only three MOS transistors, demonstrated promising chaotic properties. In this paper, we present 45 nm designs of these two circuit topologies and propose two novel threetransistor discrete-time chaotic circuit topologies. With these four chaotic map topologies, we explore the application of the cascading scheme in CMOS-based chaotic circuits. The chaotic properties of the main four topologies and their cascaded combinations are analyzed with bifurcation plot, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient. To demonstrate the application of cascading, we propose a novel CMOS-based chaotic random number generator (RNG) design with two additional alternative designs. The cryptographic performance of the proposed RNG is evaluated with four statistical tests.
The rest of the paper is organized as follows: Section-II presents the four chaotic map topologies and the cascading scheme. The chaotic performance of the proposed chaotic maps and their cascades are analyzed in Section-III. The RNG design and performance evaluation of the RNG output are presented in section-IV. Section-V provides the concluding remarks.

II. CASCADED CHAOTIC MAP (CCM)
The building block of a discrete-time chaotic system is a function with non-linear transfer characteristics. Eq. (1) shows the general expression of a recursion relation where a non-liner function, S(.), transforms any point, x i from a closed interval [L 1 , L 2 ], into some other point, x i+1 in the same interval.
Here, C is a controlling parameter that governs the shape of the transfer characteristic and i denotes the discrete steps, 1, 2, 3, ..., n. This is called a discrete-time map in the interval [L 1 , L 2 ]. As we are dealing with CMOS implementations in this paper, this non-linear functionality will be provided by a CMOS circuit. We refer to this circuit as the seed map. FIGURE 1 shows the schematic of four topologies of seed maps where, V c denotes the control parameter. As we have mentioned in section-I, the 600 nm CMOS designs of Topology-I (FIGURE 1(a)) and Topology-II (FIGURE 1(b)) were proposed in [22] and [23], respectively. We introduce two more three-transistor-based chaotic map topologies, namely, Topology-III (FIGURE 1(c)) and Topology-IV (FIGURE 1(d)) in this work. We have simulated these four chaotic map topologies (I-IV) using the Spectre simulator in Cadence, with a 45 nm CMOS process. In the simulation, we have experimented with the sizes of three MOS transistors and come up with different geometries that can generate discrete-time chaotic sequences. TABLE 1 shows the transistor sizing of two geometries (a, b) under each topology that we will be using to present all the results in this paper. Generally, map circuits are designed to approximately imitate the unimodal transfer characteristics (for example, tent or 'V' shape for the tent map or inverse tent map, respectively) of one of the widely known chaos maps such as a logistic map, sine map or a tent map. Although, in general, any number of seed maps can be connected in series to form CCM, in this paper, with the objective of overhead optimization in mind, we are limiting ourselves to a cascade of two seed maps. The schematic of the cascading scheme is shown in FIGURE 2. FIGURE  3 shows the transfer characteristics of seed maps and the cascaded pairs of the same maps. Comparing FIGURE 3(g) and 3(i), we can see how the shapes of the transfer curves vary with the choice of geometry in the same topology. The seed maps of T opology − I and T opology − IV generate approximate 'V -shaped' curves while we get approximate 'tent-shape' from T opology − II and T opology − III. We know from Feigenbaum's work in [24] that differentiable unimodal transfer characteristics have the potential to generate chaos. Hence, the transistor sizes of the seed maps are carefully chosen to get the unimodal transfer curve shapes (close to a 'V' or tent-shape). We are getting multi-modal transfer characteristics from cascaded maps which result in a much better chaotic properties compared to the unimodal characteristics of the seed maps.

III. PERFORMANCE ANALYSIS
The chaotic property of a discrete-time map is evaluated based on the discrete-time sequence generated from the map. For a particular value the control parameter, C, if we run the recursion relation of Eq. (1) in a loop where the output of one step will be fed back as the input for the next step, we   get a sequence of discrete-time values. However, we do not have a simple closed-form analytical input-output relation for our CMOS-based seed maps. To generate discrete-time sequences from these map circuits, we use a feedback system called chaotic oscillator. FIGURE 4 shows the schematics of chaotic oscillators for a single seed map and cascade of two seed maps. In both oscillators, switch ϕ 0 is used to feed the initial state, X 0 , to the system. At each iteration, an analog voltage, X n , passes through the forward path (Seed map−A in the single case, Seed map − A, and Seed map − B in the cascaded case) and we get the first output, V out1 . In general, capacitors are used to sample and hold the voltage in the feedback path. In our design, we reduce the hardware cost by performing the sample and hold operation with two nonoverlapping clock-run switches, ϕ 1 and ϕ 2 , and the parasitic capacitance of the transistors of the seed map circuit. One iteration loop completes when the output of the feedback path, V out2 , is fed back to the forward path as an input for the next iteration. At each iteration, we sample out two analog voltages, V out1 , and V out2 . The discrete-time sequences are recorded for 15000 iteration loops. Then the first 1000 iterations are discarded to get steady-state values. The steadystate discrete-time values are used for chaotic performance analysis, with the help of bifurcation plot, and three chaotic entropy metrics: Lyapunov exponent, Kolmogorov entropy, and correlation coefficient measurement.
A. BIFURCATION PLOT FIGURE 5 shows the bifurcation plots for single and cascaded maps of both geometries under each of the four topologies. In these plots, 14000 steady-state analog values are plotted for each control/bifurcation parameter (V c ). The dark-colored regions of the plots indicate chaotic behaviour.  In the remaining portions of the plots, the analog sequence either remains fixed to a single value (fixed point) or periodically fluctuates among a countable number of levels (periodic orbit). One distinction between the single and cascaded case is that the even periodic orbits are reduced by half in the cascaded case. For instance, 0 V < V c < 0.25 V region in FIGURE 5(a) shows a period of two (two distinct output voltage levels for all the V c values in this region), where the same region in Figure 5(e) shows just one level. The reduction of even periods by half comes from the fact that we are connecting two similar seed maps in series. A cascade of three similar maps would result in a reduction of the period-3 orbit region to a single level region.

B. LYAPUNOV EXPONENT
The Lyapunov exponent (LE) is the most widely-used metric to quantify the sensitive dependence of a chaotic sequence on initial conditions. On average, two neighboring trajectories of a chaotic sequence, starting from slightly different initial conditions, diverge exponentially fast [5]. For a discrete-time chaotic system, as expressed in Eq. (1), LE (denoted by λ) can be expressed as shown in Eq. (2) [5], where, n denotes the number of iteration.
A negative LE value indicates either a fixed point or a periodic orbit. On the other hand, a positive value of LE represents a chaotic attractor [5]. Faster divergence of the output trajectory of a chaotic oscillator corresponds to a larger positive LE value. Now, we want to derive the LE for a cascaded chaotic map. Let's consider two very close initial states, X a 0 and X b 0 , which are separately passing through a cascaded map as shown in FIGURE 2(b). After the first iteration, they result in two output states, X a 1 and X b 1 , respectively. We can express the difference between the two output states as shown in Eq. (3).
The derivatives of two seed maps in the cascade combination can be considered separately as follows: In the same way, after the 2 nd iteration, the difference between two outputs can be expressed as shown in Eq. (5).
The difference between two outputs after the n th iteration can be expressed as shown in Eq. (6).
The average change per iteration that occurs to go from |X a 0 − X a 0 | to |X a n − X a n |, can be expressed as shown in Eq. (7).
According to the definition, LE for the cascaded map (λ c ) can be expressed as follows: If the cascaded map uses two similar seed maps, i.e. when S 1 and S 2 are same, each of the two terms in Eq. (8) can be approximated as the LE of the seed map. In general case of the cascade of k similar maps, the LE of the cascaded map can be expressed as shown in Eq. (9). It should be noted that expressing the LE of cascaded maps as a sum of constituent seed maps (as shown in [18]) is not true in general. Eq. (9) holds only when the seed maps have identical or very similar trajectories. FIGURE 7 demonstrates this point by comparing the sum of the positive LE values of seed maps with the cascaded maps in two cases: (a-h) cascade of same seed maps (same topology, same geometry) and (i-l) cascade of different seed maps (same topology but different geometry). As we can see from FIGURE 7(a-h), Eq. (9) holds for same seed maps but does not necessarily hold in the general case with different seed maps (FIGURE 7(i-l)). Moreover, the bifurcation plots of FIGURE 7(o) and FIGURE 7(p) show that, the chaotic region is absent as a result of cascading two dissimilar maps where there is no overlap between their corresponding chaotic regions (as shown in FIGURE 5(c,k), and FIGURE  5(d,l)). Consequently, we get no positive LE value over the whole V c range of FIGURE 7(k) and FIGURE 7(l). In all results up to this point, both maps of a cascade share the same V c . However, it is possible to use any arbitrary combination of V c values. FIGURE 8(a-c) shows the LE values using heat map for all possible combinations of V c between two cascading maps. Here, we can see that, a cascade of two dissimilar topologies (FIGURE 8(c)) does not result in positive LE values for any combination of V c . Hence, as a design guideline, we should keep in mind that the benefit of cascading can be leveraged most conveniently when we cascade two identical maps.

C. KOLMOGOROV ENTROPY
The Kolmogorov entropy (KE) measures the complexity in a sequence by capturing the generation rate of new information. To present an estimation method in [25], Grassberger et al. defined KE as follows: let's suppose, in a dynamic system, an F -dimensional phase space is partitioned to ϵ F -sized boxes. We are measuring the state of a trajectory, ⃗ X(t), in the time intervals τ . There is a probability measure, p(i 1 , i 2 , ..., i d ), that defines the joint probability of ⃗ X(t) being in the box i 1 at t = τ , in i 2 at t = 2τ , and so on. As a result, KE is defined as shown in Eq. (10) [25].
The value of KE is 0 for an ordered sequence, ∞ for a random sequence, and a nonzero constant for a chaotic sequence. FIGURE 9 shows a comparison of KE values between the seed map and it's cascaded pair where, the nonzero KE regions correspond to the respective chaotic regions. We can notice here as well that the cascading scheme substantially increases the entropy measure compared to the constituent seed map.

D. CORRELATION COEFFICIENT
The initial state sensitivity in chaotic and non-chaotic regions of a sequence can be measured using the correlation coefficient as well. The correlation coefficient between two sequences, X and Y, can be expressed as shown in Eq. (11) [26].
Here, in Eq. (11), the operator 'E[.]' denotes the expectation function, µ and σ are the mean value and standard deviation, respectively. The correlation value is close to +1/-1 if X and Y are highly correlated whereas, a 0 correlation coefficient value indicates an extremely low correlation between the two sequences. For each value of the bifurcation parameter, two sequences are generated, starting with two very close (1 nV apart) initial states. FIGURE 10 shows the calculated correlation coefficients for different values of bifurcation parameters, in both single and cascaded cases of different geometries. This same metric can also be used to see the sensitivity of the bifurcation parameter variation. For this purpose, another set of data is generated, with a 1 nV variation in the control parameter, while keeping the initial state fixed. FIGURE 11 shows the calculated correlation coefficients for the V c variation scheme. Both figures depict that, in chaotic regions for both single and cascaded cases, even that tiny difference in the initial state or V c leads to significant divergence between the two sequences which causes the correlation coefficient to become close to 0. However, in the non-chaotic regions, the tiny difference in initial condition eventually diminishes in steady-state output values and that results in a correlation coefficient of 1.
Moreover, mainly at the edges of the chaotic regions, the cascaded maps show correlation coefficient values closer to 0 than the seed maps, which indicates stronger chaotic property from the cascaded maps.
The comparison of LE between seed maps and corresponding cascaded pair of the same seed maps. In the cascade, both maps use the same Vc. Here, for example, 'IIa' denotes the Geometry − a of T opology − II which shows the comparison between the LE from the seed map, IIa, and the cascaded map, IIa-cascade-IIa.
: The comparison of KE between seed maps and corresponding cascaded pair of the same seed maps. In the cascade, both maps use the same Vc.
FIGURE 10: The comparison of initial condition variation-based CC between seed maps and corresponding cascaded pair of the same seed maps. In the cascade, both maps use the same Vc.

IV. APPLICATION
It is clear from the entropy measurements that we are getting improved chaotic performance from cascaded maps. Hence, this topology can be a natural choice for applications like chaos-based random number generator (RNG) where a chaotic map with better chaotic properties is always desired for ensuring more secured cryptographic performance. In this section, we are presenting the design of an efficient RNG, based on a combination of single and cascaded maps. The applicability of the generated random sequence in cryptography is assessed with four established statistical randomness test suits and the overhead cost of the RNG is compared with other reported works. to increase the entropy in the generated sequence. For each comparator, we use the cascade of two identical maps and single output from the same map. We have experimentally come up with multiple combinations of maps to be used in three comparators of the RNG, that pass the statistical tests. Then we measured the worst-case delay of the cascaded oscillators (since the cascaded delay is higher than the single one and the higher delay component is the determining factor of the circuit). FIGURE 13 shows the delay with respect to V c for different maps. We also have recorded the total power consumption of single and cascaded oscillators. The power is averaged over multiple oscillations in steady-state, starting from three different initial conditions. The average power with respect to V c is shown in FIGURE 14. Considering the sizing of the transistors (shown in TABLE 1), the worst-case delay of the oscillators, and the average power consumed by the oscillators, we have nominated one combination to present the results where, Comparator − I, Comparator − II, and Comparator − III use Ib, IIIb, and IV b maps, respectively. For each comparator, all the six maps from the single and cascaded oscillators run at one particular V c . We wanted to make sure that the nominated combination would capture a low on-chip area, and the chosen V c point for each oscillator is in a reasonable delay and power range while ensuring enough chaotic entropy to pass the statistical tests.

A. RNG DESIGN
In the presented RNG, Comparator −I, Comparator −II, and Comparator − III use V c = 0.408 V , 0.474 V , and 0.904 V , respectively. For statistical tests, we generated 100 million binary bits, starting with 100 unique initial conditions where each initial voltage generates 1 million bits.
As mentioned earlier, the simulation is done in the SPICE (Simulation Program with Integrated Circuit Emphasis)class circuit simulator of Cadence, called Spectre. We have not added any stochastic component in the simulations that are shown up to this point. Hence, the simulation results are purely deterministic. That means, with a specific V c and initial condition, a chaotic oscillator made with two IIa maps, for example, will generate an identical chaotic sequence each time we run the simulation. As a result, the simulated number sequence from the proposed RNG is not truly random, since the simulation result is reproducible. This type of aperiodic but reproducible number sequence is called pseudo-random sequence and the circuit is called pseudo-random number generator (PRNG) [27]. Our proposed circuit acts as a PRNG in the simulation with no stochastic component added. However, in an integrated circuit (IC) chip, there will be inevitable cycle-to-cycle perturbations such as noise-driven drift of node voltages, power supply noise, temperature variation over the course of operation, and so on. These perturbations, even if they are small in amplitude, will eventually be amplified by the chaotic properties and the circuit will be close to a true-random number generator (TRNG) in practice [28]. To demonstrate the essence of this mechanism, we added normally distributed random noise (mean= 0 V , standard deviation= 0.1 mV ) in the simulation. Two sets of 100 million data are generated from the TRNG, using the same set of 100 unique initial conditions in both cases. Then the correlation coefficient is calculated between these two sequences. A low correlation coefficient of 1.7 × 10 -6 shows that the small noise perturbations got amplified by the chaotic nature of the circuit, satisfying the condition that the output of a truly random number generator is not reproducible.

1) NIST SP 800-22 Test Suite
The test suite from the National Institute of Standards and Technology (NIST) offers 15 statistical sub-tests to measure  the randomness in a sequence [29]. We ran the test with a bit-stream length of 1 million. The significance level was set to 0.01. Hence, a sequence with 100 million bits (containing 100 bit-streams) will pass a particular test if at least 96 out of the 100 bit-streams generate a p-values greater than 0.01. The test suite allocates each of the 100 generated p-values in 10 sub-intervals from 0 to 1 and evaluates the uniformity in the distribution with χ 2 -test. The sequence under test can be considered uniform if the p-value generated from the χ 2 -test (refers to p−value T ) is greater than or equal to 0.0001. NIST results, presented in FIGURE 15, show that both PRNG and TRNG sequences pass all requirements of 15 sub-tests.

2) FIPS PUB 140-2
The Federal Information Processing Standards Publications (FIPS PUB) 140-2 test suite was developed by NIST [30].  order. The linear fits in both plots show close conformity with the generated p-value trends, indicating the desirable randomness in each sequence.

4) TestU01
TestU01 offers a collection of utilities for the empirical statistical testing. This test suite comes as a software library generated in ANSI C language [32]. We ran three test batteries namely, Rabbit, Alphabit, and BlockAlphabit.

C. OVERHEAD ANALYSIS OF THE RNG
We have simulated our circuit in Cadence with 45 nm CMOS process and 1 V power supply. We analyzed the area, delay, and power profile of each of the components separately to optimize the whole RNG design. Considering two maps in the single oscillator (FIGURE 4(a)) and four maps in the cascaded oscillators (FIGURE 4(b)), we have a total of 18 maps from all six oscillators in the proposed three-comparator RNG design. The total area of six chaotic oscillators is 0.809 µm 2 . The worst-case delay of the cascaded oscillators, at the chosen V c points are 1.6 ns, 3.4 ns, and 0.36 ns. As the slowest oscillator governs the overall speed, the analog voltage generation rate from the oscillator portion of the circuit is 3.4 ns. The total power of six chaotic oscillators is 140.65 µW . We have implemented the 45 nm design of a standard latch-type comparator, originally proposed by [33] in a larger technology node of 5 V power supply. We have verified that, in our supply voltage range of 1 V , the performance of this basic design is as good as a more advanced and complex (larger area) design proposed in [34]. The area of the comparator is 110.6 µm 2 , the worst-case delay of the comparator is 0.4 ns, and the average power consumption is 1.9 µW . As a result, the overall area, power consumption, and bit generation rate of our proposed RNG design are 332.6 µm 2 , 142.5 µW , and 294 M S/s.

D. PERFORMANCE IMPROVEMENT
We can accommodate additional design requirements by altering the proposed core RNG design. For example, the total area can be reduced by implementing an alternative design as presented in FIGURE 17(a). In this design, the added area and power overhead from the addition of a 3-bit shift register (SR) will be over-compensated by the deduction of two comparators. With an efficient setup of clocking for the selection mechanism at the comparator input and the 3bit SR, we can ensure that the three bits from three pairs of single-cascade comparison will be ready for XORing within the worst-case delay of the slowest chaotic oscillator. As a result, the bit generation rate of the alternative design-I will be the same as the originally proposed design. This design can be useful where there is a tighter area constraint but slightly additional design complexity from the extra clocking for the selection mechanism is acceptable. On the other hand, if a design requires higher bit generation rate with a compromising area constraint then we may propose a design as shown in FIGURE 17(b). This design uses n copies of alternative design-I providing n-times more bit generation rate with respect to the alternative design-I. In this alternative design-II the area and power overhead will be increased by around n-times of the alternative design-I. We have verified that both of these alternative designs pass the statistical tests. TABLE 4 presents an overhead comparison between the proposed designs of this paper and some already reported designs. We can see that a significant improvement in the area and power overhead is achieved by the proposed designs.

V. CONCLUSION
We have demonstrated a hardware-efficient way of improving the chaotic performance of CMOS-based chaotic maps. The 45 nm designs of four chaotic map topologies are presented. With the help of eight unique chaotic maps, it is demonstrated that the cascade of multiple seed maps offers improved chaotic behavior over its constituent seed maps under certain constraints. This improved chaotic property of the cascading topology was utilized to propose a novel comparator-based RNG design that passes four standard statistical tests. Two alternatives of the proposed core design are presented to show the applicability in accommodating special design requirements. The proposed RNG designs have accomplished a significant reduction in area and power overhead compared to previous designs of similar kinds. The simple transistor-level seed maps along with the framework of cascading can be used to improve the chaotic performance and reduce the overhead cost of discretetime chaotic systems. This work can be useful in different VOLUME 4, 2016  hardware security applications including side-channel attack mitigation by chaos-based reconfigurable logic and RNGbased data encryption.