Implementation of Hardware Architecture for SVPWM with Arbitrary Parameters

A novel hardware digital architecture for the Space Vector PulseWidth Modulation technique is proposed. Its characteristics are the reduced demand for resources and the possibility to change in real-time the values of the carrier and switching frequencies, of the phase and of the amplitude of the three-phase output voltages without external reference signals or processor. The basic idea is to pre-calculate a set of normalized dwell-time for only one sixth of the α-β-plane and, then, to reconstruct through our architecture the effective dwell-times and the right inverter configurations by an optimized management of the memory. The architecture is implemented in a Field Programmable Gate Array Cyclone V using the 6% and the 1.01%, respectively, of the Look-Up Tables and of the Flip Flops and the experimental measurements show the goodness of the generated waveforms and the high numbers of degrees of freedom without the demand of Digital Signal Processor or Personal Computer.


I. INTRODUCTION
T HE modern power converters are complex electronics systems where Analog/Digital Converters, decision logic circuits, auxiliary supply circuits, communication circuits are part of a single unit together with the power electronic circuits. Digital controllers can manage them and also perform the mere control of the power converter but requires a high degree of complexity in terms of calculations and of resources. For example, in some applications a multi stage of power converters, like insulated DC/DC converter followed by DC/AC inverter [1], is frequently used and a customized digital controller can drive both converters, differently from the past where a single controller is dedicated to each single power stage. Programmable Logic Devices, PLD, like micro controller [2], Digital Signal Processor, DSP, [3] or Field Programmable Gate Array, FPGA, [4], are good candidate for such kind of applications thanks to the good performances of elaborations and to the ease of use [5]. In the mentioned scenario, even if the elaboration speed of the new processors increases, it also needs the capability of parallel processing for the management of the auxiliary circuits as well as for the overall computing load. Therefore, the design of the new HardWare, HW, architectures focuses on reducing the use of advanced processors, like DSPs, in order to keep them for other features, as well as the resource utilization and the power dissipation. Moreover, in the scenario of the obsolescence of integrated circuits that is relevant for all those industrial applications where the product life is longer than ten years [6], Application Specific Integration Circuits, ASICs, are more expensive and difficult for firmware updating than PLD, like FPGAs. Moreover, the recent introduction of the wide-bandgap power devices, like Silicon Carbide DMOSFETs [7]- [9] and Gallium Nitride HEMTs [10]- [12], permits to increase the switching frequency over hundreds of kHz and new HW architecture of the PLDs are required in order to optimize their resources. Indeed, stand alone systems needs a single PLD able to manage both power electronics and the auxiliary circuits and, also, their large scale produc-tion imposes the utilization of low cost electronics that have low performances in terms of system clock frequency and HW resources.
In this context the design of three-phase DC/AC power converters and, in particular, of those systems implementing the Space Vector Pulse Width Modulation, SVPWM, control technique imposes several stringent conditions. Indeed, SVPWM technique can be implemented by using only digital controllers because the high computational calculation of the dwell-times for the gate signals is difficult to achieve with analog circuits [13]. The most used SVPWM digital controllers are microcontrollers and FPGA [14]- [17]. They permits to reconfigure the control technique, once the electronic board is fabricated, and to operate in real time with low execution times [4], [18]- [21]. If, on one hand, microcontrollers are interesting for low cost systems comparing with the FPGA, on the other hand they show more failures for the generation of the signals using the direct digital synthesis, like phase errors among the generated signals due to sync problems [22]. Since the choice among them depends on the specific applications, the state-of-art of SVPWM digital control shows still some drawbacks. For example, the trigonometric functions for the dwell-times are evaluated either through CORDIC algorithm [23] or through DSPs and EPROM reference table [24] with the need for an external reference signal, which is impracticable for stand alone and low cost systems. Indeed, further hardware or software tools need to generate the three-phase reference signal, to calculate the dwell-times and to send the gate signals to the gate drivers: such approach increases the cost, the space and the complexity of the power system.
In this paper, a novel hardware design of a digital architecture to implement SVPWM technique is proposed. The HW architecture calculates the dwell-times of the gate drive signals and the inverter configuration by selecting in real-time the desired values of the carrier and switching frequencies, of the amplitude and of the angle of the three-phase output voltages and the rotation direction of the rotor. Moreover, our architecture avoids external signals or processors and, although it uses tabled data stored in an internal Look-Up Table, the management of the memory is optimized in order to reduce the resources and to have a high degrees of freedom. We show our proposal by using FPGA digital controller integrated in a power AC/DC converter for asynchronous motor driving, but it can be also adapted for microcontrollers. The novelties introduced in this paper compared to others solutions [25], [26], that are based on the storage of pre-calculated dwell-times are as follows: • a detailed theory for the optimized management of the HW memory; • the possibility to vary switching frequency in real-time; • the possibility to choice the angle of the reference vector in real-time; • a detailed description of the HW architecture. The paper is organized in this way: in Section II the basic theory of the SVPWM control technique is reported, whereas the theory and the implementation of our HW architecture are, respectively, in Section III and IV; in Section V we implement our proposal and compare the results from the state-of-art; Section VI reports the conclusions.

II. BASIC THEORY OF SVPWM
Let us consider the three-phase inverter of Fig. 1.a where P A+ , P B+ and P C+ are the top transistors and P A− , P B− and P C− are the bottom transistors, V DC is the total DC input voltage and v A , v B and v C are the phase voltages refer to ground. We can generate an output three-phase sinusoidal waveform at a desired carrier frequency, f C , and amplitude, V M , using a modulation signal at a switching frequency, f SW , if the gate driver signals of the transistors are opportunely timed. Although there are several techniques to generate the gate drive signals, the SVPWM has better performance in terms of stator current quality and harmonic wave generation [27]. An example of temporal sequence of gate signals of the top transistors in a switching period is reported in Fig.1.b: the interval times of each configuration of the inverter, S i , are called dwell-times, i.e. T 0 , T A and T B . It is worth to note that 1 means that the top transistor is ON and the bottom one is OF F , instead 0 is the opposite configuration.
The SVPWM is based on the representation of the threephase voltage system through the reference vector, V REF , in the α − β plane of Fig.2 obtained from the following twophase transformation: that can be also expressed in the vector form with amplitude V REF = V 2 α + V 2 β and angle respect to the α-axis θ = arctan(V β /V α ), as shown in Fig.2.
Once V REF is defined in the α − β plane, it is projected along the two closest vectors, V A and V B : indeed, observing where T SW = f −1 SW . Solving (2) we have: where V 0 and V 7 are assumed null vectors. Taking into account that the six vectors V i are arranged to each other of an angle π/3, the well-known expressions of the dwell-times are obtained [24]: where i represents the i-th T SW -instant and m a = 2V M /V DC <2/ √ 3 the modulation index. It is worth to note that, for a given sector, V A and V B refer to the vectors, respectively, with the smallest and the largest angle, i.efor Moreover, the discretization of the circumference depends on f SW and f C and the smallest angle, ∆θ, is equal to 2πf C /f SW . The SVPWM technique uses (4) to evaluate the dwell-times and defines their sequence for a single T SW . The complexity to implement SVPWM in a digital controller is precisely the calculation of trigonometric functions and the sequence of the dwell-times, i.e. Fig.1.b or c, in order to have an output signal with low harmonic distortion and low device power dissipation. In this paper we propose a HW architecture for the implementation of the SVPWM in a digital controller that solves such limitations.

III. THEORY OF THE PROPOSED HW ARCHITECTURE
Generally, the SVPWM are performed by using an external processor, like a DSP or a PC, together with a controller, like microcontroller or FPGA. The external processor needs to generate the three-phase reference voltage with the desired V M and f C that is transformed through (1) in the vector form to calculate V REF and θ. Then, the digital controller evaluates the dwell-times and the inverter configurations. Such approach is unwanted when one needs a stand alone or an independent controller. On the other hand, other solutions use an internal memory [25] where the values of the dwelltimes are stored for a fixed f C and f SW , but without the possibility to vary them in real-time. We overcome such limits and, although it is based on the approach to store the dwell-times in an internal memory of the controller, our HW architecture satisfies the following points: • all the system is integrated in the digital controller; • the external processor is avoided or is just used to configure the system; • V M , f C , f SW and θ can be varied in real-times; • the HW resources are reduced thanks to an optimization of the required memory.
The procedure of our proposal can be summarized in the following steps: i the pre-calculation of the normalized dwell-time in terms of the minimum carrier frequency, f Cn , of the maximum switching frequency, f SW n , and of the maximum modulation index, m a ; ii the storing of the pre-calculated data in the internal Look-Up Table, LUT, of the digital controller; iii the setting in real-time of the f C , f SW , θ and of the percentage of the modulation index, m, which are the input of the controller; iv the calculation of the effective dwell-times through the HW architecture; v the generation of the six gate drive signals including the dead-time for the power transistors.
In the next subsections, the modeling of the proposed SVPWM algorithm is reported and, in particular, we show the evaluation of the normalized dwell-time and the managing of the internal memory in order to obtain the desired dwelltimes.

A. NORMALIZED DWELL-TIME
Observing the vector representation of Fig. 2, the six sectors are equally divided in angles of π/3 and, when V REF is in a generic sector S i , we can calculate from (4) the dwelltimes referring either to the angle θ or to the angle ϕ, i.e. ϕ = θ−(S i −1)π/3. Moreover, in each sector the projections of V REF are symmetric around the angle (S i − 0.5)π/3, for example for S i = 2 at θ = π/2 we have T A = T B or we obtain T A (θ = π/3) = T B (θ = 2π/3). Taking into account such considerations and from (4a) and (4b), the normalized VOLUME -, 2022 L. Di Benedetto et al.: Implementation of Hardware Architecture for SVPWM with Arbitrary Parameters dwell-time, T N , is expressed in the following equation: where f CLK is the clock of the controller, 100 is for the variation of m a in real-time from 0% to 100% of its value, l is a constant. The variable is ϕ and its values are from 0 to π/3 with an incremental step of ∆ϕ n = 2πf Cn /f SW n , whereas the variation of the sector is given by the right selection of the inverter configuration. Indeed, once the starting angle is located and, hence, also the starting sector, the sequence of the sectors is always the same and in succession. The constant l is introduced in order to have integer numbers of the normalized dwell-times so that the counter of the HW architecture can easily perform the counting of the times. Its value is l = 2 L where: and it has been calculated by equaling the smallest value of T N to one, i.e. using ϕ(i) = ∆ϕ n and placing (5) equal to 1.

B. MANAGING OF THE LUT
The size of the memory is reduced because only one sixth of the circumference is stored. Indeed, once T N are evaluated from (5), they are stored in a single LUT of the digital controller. The size of LUT and of its cells are equal, respectively, to: where (7b) is calculated by placing ϕ(i) = π/3 in (5). Moreover, we obtain a further reduction of the resource occupation because the reconstruction of the two dwell-times is performed by a double indexing of the memory: as shown in Fig. 3.a, the LUT memory is pointed by two indexes, ind A and ind B , from which the data for the calculation of T A and T B , respectively, are extracted. In particular, for each When θ is defined, we can find the starting cells of the LUT in two sequential steps: 1 the identification of S i is done through a cascading comparators having θ as inputs: In the Section IV, the S i variable corresponds to the ACT U AL SECT OR signal of our architecture 2 the evaluation of ind A and ind B is as follows: Once (9) are calculated, ind A and ind B increases and decreases, respectively, of n C n SW which are defined as follows: For example, when θ = π/3 the starting sector is 2 and ind A = 1 and, then, ind A increases of 4 when n SW = 4 and n C = 1 (see Fig.3.b), of 3 when n SW = 1 and n C = 3 (see Fig.3.c), and of 6 when n SW = 2 and n C = 3 (see Fig.3.d).
The values of the minimum f SW and of the maximum f C are defined by the Nyquist-Shannon sampling theorem [28], from which, defined the accuracy of the reconstruction through the integer number s, i.e. f SW ≥ sf C , we can find the respective values of n SW and n C from (7a) and (10) as follows:

C. EVALUATION OF THE EFFECTIVE DWELL-TIMES
Once the T N -values are stored into the internal LUT, our HW architecture calculates the effective dwell-times, which are expressed in times of clock system pulses, through the following operations: In Fig.4 we report the effective dwell-times evaluated with our approach through the software MATLAB [29]. First of all, we defined f CLK = 50M Hz, f Cn = 10Hz, f SW n = 100kHz, and m a = 1.06: obtaining l = 2 9 = 512 from (6), a LUT size of N LU T = 1667cells from (7a), a cell size of N CELL = 11bits from (7b), and a limit of the sampling of n C n SW ≤ 99.9 from (11) for s = 100, which depends on the user degree of accuracy. After that, we used (12) and the sequential access to the LUT (see Section III-B) to calculate the effective dwell-times. In Fig.4.a and b the three effective dwell-times are reported for m = 100 and n SW = 1, instead the carrier frequency has been changed from 10Hz to 50Hz, i.e. n C = 1 (see Fig.4.a) to n C = 5 (see Fig.4.b): although the values of the effective dwell-times are the same due to the same multiplication factor in (12), they show a different f C . Moreover, six intervals divide each carrier period and correspond to the six sectors of Fig.2. In Fig.4.b and c f SW has been changed from 100kHz to 20kHz, i.e. n SW = 1 (see Fig.4.b) to n SW = 5 (see Fig.4.c), whereas the amplitude changed from 100% to 69% of m a (see Fig.4.c). First of all, we can observe the increase of the values of the effective dwell-times when n SW = 5 because  there is a direct dependency on it in (12); then, for the same f SW the reduction of m induces a decrease of T A and T B and an increase of T 0 , because the reduction of the output threephase voltage amplitudes can be achieved setting the inverter in the null configuration for more time. For all the cases the symmetry of the effective dwell-times in each sector interval time is evident.

IV. HW ARCHITECTURE
The functional block diagram of Fig.5 shows the HW implementation of our system, which we called SV P W M BLOCK. The DATA IN are θ, n C , n SW , m, and L/R and can be changed in real-time during the controller operation. The first four inputs have the same meaning of the Section III instead the signal L/R defines the phase of the three-phase output voltages and it can be useful, for example, to rotate clockwise and counterclockwise the rotor of a asynchronous motor [30]. The output signals are the six gate driver signals and are towards the power converter. The main blocks of the system can be arranged in three subsystems and each of them is described in the following subsections.

A. LUT AND COUNTERS
The first subsystem is formed by the internal memory LU T and by the two counters, P OIN T ER and COU N T ER. The LU T is a memory block in which T N , evaluated from (5), is stored. The sizes of the LU T and of its cells are, respectively, N LU T from (7a) and N CELL from (7b). The two indexes of the LU T , ind A and ind B , point to two different positions in order to give the two normalized dwell-times, T AN and T BN , that are sent to the next subsystem (see Section IV-B) for the evaluation of the effective dwell-times. The P OIN T ER block manages the indexes and its inputs are θ, n C and n SW . During the compilation process of the digital controller, P OIN T ER needs the value of N LU T so that the reset of the counter can be set. Furthermore, P OIN T ER keeps track of S i through ACT U AL SECT OR signal controlling the SECT OR SELECT block: the starting sector is defined from a cascading comparators and the starting indexes are from (9). Then, the P OIN T ER increases and decreases, respectively, ind A and ind B of the quantity equal VOLUME -, 2022 to n C n SW and, when ind A ≥ N LU T or, similarly, ind B ≤ 1, it resets its counters and increases ACT U AL SECT OR by one up to 6, after that restarts to 1.
P OIN T ER operations are done when the EN ABLE signal from the COU N T ER block is high, whereas, once they are completed, the DON E signal is sent to the COU N T ER that ensures the right inverter configuration with the needed dwell-times. In Fig.6 the flow chart of the P OIN T ER operation is shown.
The COU N T ER block has seven input signals, that are the effective dwell-times for each sub-interval time of the switching periods (see Fig. 1.b and c), and the DON E input signal in addition to the LSB of ACT U AL SECT OR signal. The flux diagram of Fig.7 is performed by the COU N T ER and described as follows: • IDLE: in this state the COU N T ER sets the multiplexer to "00", the EN ABLE signal to "1", the ST ART signal to "0", and the internal variable J to 0. It remains in this state until the DON E signal changes to "1"; • Set-Up: once DON E = 1, the counting preparation for  Normalized dwell-times together with n SW and m are the inputs of the DEN ORM ALIZAT ION block that perform the calculation of T A and T B by using (12a). Taking into account that for multiplication operation the bits length of the product is the sum of the bits lengths of the factors, we  performs (12a) in three steps without loss in accuracy, as reported in Fig.8.a: firstly, the multiplication of T AN/BN and m is done; secondly, a left bit shifting is executed for L bit positions; finally, this last is multiplied by n SW . Once T A and T B are calculated, the effective dwell-time T 0 is evaluated in the T 0 −CALCU LAT ION block that performs (12b) using as inputs n SW , T A and T B and the functional block diagram is in Fig.8.b. It is worth to note that L, evaluated from (6), and int[f CLK /f SW ] are constant.
Before sending the effective dwell-times to the COU N T ER block, the T IM E DIV ISOR block (see Fig.8.c) divides the evaluated T A , T B and T 0 in the seven sub-intervals of T SW as reported in Fig.1.b and c. To perform it, a sub-block DIV. makes the following operations: where the check of the LSB of the input T defines whether it is even, i.e. LSB = 0, or odd, i.e. LSB = 1, and its functional block diagram is reported in Fig.8.d. It is worth to note that the operation is a single left bit shifting and requires only a small amount of resources.

C. SELECTION OF THE INVERTER CONFIGURATION
The last sub-system consists of the SECT OR SELECT and DEAD T IM E blocks, of a multiplexer, and of a crossover switch and its functional block diagram is reported  MUX  00  11  01  10   1  000  111  100  110  2  000  111  110  010  3  000  111  010  011  4  000  111  011  001  5  000  111  001  101  6 000 111 101 100 in Fig.9. The SECT OR SELECT block supplies the four 3-bit string, i.e. C 0 , C 7 , C A , and C B , to the multiplexer used to define the inverter configuration during a dwell-time. These four signals depend on the wanted sector, which is selected through the ACT U AL SECT OR input signal. Then, as reported in Tab. 2 the M U X signal from the COU N T ER block selects the right inverter configuration. Before sending the three signals to the DEAD T IM E block, two of the three signals go through the crossover switch, that is controlled by L/R input signal. In this way, the gate signals between the leg B, i.e. P B+ and P B− , and the leg C, i.e. P C+ and P C− , of the power converter of Fig.1.a are switched one to each other introducing a phase shift among the relative phase voltages, i.e. v B and v C : it means inducing a rotating magnetic field in clockwise or counterclockwise directions.
The DEAD T IM E block generates the six signals for all the power transistors of the inverter including the dead-time. A counter performs the delay of integer multiple of 1/f CLK with a minimum value of 1/f CLK and a maximum of (2 10 − 1)/f CLK . It is worth to note that such block has been introduced in our HW architecture for completeness being fundamental for the correct operation of the power converter. It can be removed if analogue dead-time circuit is used or substituted by another implementation of the DEADT IM E block. However, in the next Section the estimated resources for our architecture also consider the DEAD T IM E block.

D. FLOW CHART OF THE PROPOSAL
The flow chart of the proposed architecture is reported in Fig.10  block of Fig.6, we can extract the complexity of the algorithm considering the McCabe's cyclomatic number and nesting complexity metric, which are, respectively, 10 and 12 following the procedure reported in [31].

V. FPGA IMPLEMENTATION
The prototype is a three-phase DC/AC power converter, used to drive a 750W − 380V AC − 50Hz three-phase asynchronous motor without neutral point, and is shown in Fig. 11 together with the motor and the point machine which are used in the railway network. The DC-input voltage is V DC = 600 V with an input capacitor of 250 µF , whereas the power transistors are STMicroelectronics IGBT STGW40M120DF3 that are driven by a maximum f SW of 10 kHz. The digital controller is an Altera CycloneV 5CEBA4F17C17 [32] and it is programmed with f Cn = 10 Hz, f SW n = 100 kHz, m a = 1.06, and f CLK = 50 M Hz, that are equal to those of Section III-C.
In Fig.12.a the waveforms of the gate drive signals for the top transistors show the sequence of the inverter configuration in S i = 3 at f SW = 10 kHz, being n SW = 10, instead in Fig.12.b the top and bottom gate driver signals are compared in a single switching period in order to show the dead-time of 500 ns as expected.
In Fig.13.a and b the phase and the line-to-line output voltages are reported, respectively, by using n C = 5, n SW = 10 and m = 69, which gives a peak of the line-to-line voltage of: Moreover, the third-harmonic injection of the phase voltages  is also evident, which is typical in the SVPWM modulation [33], as well as the good phase displacement of 2π/3 of the three voltages. The possibility to change in real-time the amplitude of the output voltage permits to perform several control, like the ramp up of voltage at the start-up to mitigate the overcurrent into the motor: as shown in Fig. 14, the line-to-line voltage and phase current with a start-up ramp of 1.7 s are performed and overcurrent is avoided. It is worth to note that the time of the ramp and the increasing step of m have been imposed in real-time from the external TLC interface, although they can be generated by FPGA. Moreover, the experimental measurements are obtained using the point machine of Fig.11 as load of the power converter.
In Fig.15 we show the results of our system in several configurations of the signals input and, in particular, we vary n C from 5 to 2 and then to 6 (see Fig.15.a) and the values of m and n C with a constant ratio of 7, i.e. m = const · n C (see Fig.15.b), which can be used as V /f control, and the value of θ to 2π/3 and 0 (see Fig.15.c). In all the cases the change of the system configuration is sudden and distortions of the waveforms are not evident. Moreover, the changes are performed in real-time with the external TLC interface, although they can be generated by FPGA.
In Fig. 16 the comparison of the Fast Fourier Transformation of a gate drive signal is for n C = 9 and n SW = 10 (see Fig. 16.a) and for n C = 3 and n SW = 6 (see Fig.  16.b), whereas in the inset of Fig.16.a, the measured f SW FPGA resources between our HW architecture and the stateof-art. A general FPGA architecture is based on three modules: Input/Output blocks, Interconnection Wires and Configurable Logic Blocks, CLB. These last are used to implement user logic and are disposed in a two dimensional matrix where the user can also design their interconnection. CLBs contain LUT, FF and multiplexers and mainly define the resource of the device. Hence, our metric of comparison is expressly focused on, as follows: [38]: • Look-Up- Table (LUT) is generally a n-bit combinational structure and stores the truth table of an userdefined function. Moreover, it can be used as a memory block where the stored value of the single cell is given as output for each value of the input, namely index; • Flip Flop (FF) is the smallest memory unit and able to store one bit either at the falling or at the rising edge of the clock signal; Moreover, we consider the below metrics for a complete comparison: • Block Random Access Memory (BRAM) is used to store data into a FPGA and are preferred to LUT when a large amount of data needs; • Digital Signal Processor (DSP) is a optimized processor dedicated to the signal processing; • Dynamic Power (Dyn.Pow.) is the power consumption related to the dynamic component of the overall dissipation and is evaluated through Quartus II [39] for [32] and Vivado Design Suite [40] for [34]. From the comparison with the state-of-art of Tab.3 we can state that our architecture avoids the use of the external signal references to generate the three-phase voltages before the Clarke transformation [35]- [36], of less dynamic power [35], of other resources, like DSP [37] or BRAM [17]. For such differences, our purpose is a good candidate for stand alone systems, in which the external controllers are absent or with limited functionalities. Or, for those applications where the diversity of FPGA needs to satisfy the requirements to have different controller suppliers both for the industrial production and for the safety conditions. For example, when a high Safe Integrity Level equal to 4 is needed like in railways applications, a 2oo2 architecture of digital controllers is used to reduce the risk of dangerous failure below a tolerable probability and such functionality is achieved by connecting in parallel two different processors, performing the same tasks, so that the problem of spurious trips, which induce undesired shut-down of the overall system, is reduced.
In order to show the generality of our HW architecture, we also implemented it in a low performance FPGA like Xilinx Artix 7 [34] whose 4.75% and 0.75% of LUT and FF are used. Indeed, although our system needs more resources than other like [25] even to the +2.35 and +1.27 times the required LUT and FF, respectively, or like [17] even to the +1.21 and +1.66 times the required LUT and FF, respectively, the possibility of setting several configurations of the output three-phase voltages in real-time justifies such increase. Moreover, the executive time results equal to three system clock periods and it is due to the presence of FFs between the combinational blocks of the system for the data consistency. It is worth to note that the maximum clock frequency of the system is 100 M Hz, this data is been calculated using the timing analysis of [40].
Finally, the accuracy of the architecture refers on the capacity to describe the trajectory and the amplitude of V REF in the α − β plane of Fig.2 and is reflected on the values of the dwell-times. The trajectory of V REF is imposed by the incremental step of the angle, i.e. ∆θ, and is equal to 2πf C /f SW . It means that it depends on the power converter, i.e. f SW , and on the applications, i.e. f C . Hence, if the conditions reported in Section III on how to size LUT and its cells, are respected, the LUT construction reflects the accuracy imposed by ∆θ. About the output amplitude accuracy, it depends on how much we can change m a , whose maximum value is defined during the LUT construction implementation and corresponds to the maximum values achievable by the power converter in our experimental case. In order to change it in real-time, we introduced the variable m varying the amplitude of V REF with a precision of 1% of the maximum m a value.

A. COMPARISON WITH CORDIC ARCHITECTURES
CORDIC algorithm is generally used to evaluate trigonometrical functions as for example those in (4) and in this subsection we compare our HW architecture with CORDIC ones. In particular, we replaced the blocks P OIN T ER, LU T , and DEN ORM ALIZZAT ION of Fig.5 with CORDICbase hardware: those three blocks are used to evaluate the dwell-times, instead the others are to manage the switching sequences of power converter. In this way, we can better compare the HW architectures. To design CORDIC architecture, we need to define the number of iterations of the algorithm: it depends on the minimum angle θ and, hence, on the incremental step ∆ϕ n . In our application it is 2π10 −4 and imposes 11 bits for the decimal part, that means 11 iterations for the required convergence. Then, we can define two kinds of architectures, namely CORDIC cascade and CORDIC iterative. Both of them are based on the same evaluation layer, but they differ on how to achieve the results of the trigonometric functions: CORDIC cascade is a cascade of 11 single layers and the calculation is done in one system clock; instead CORDIC iterative is a single layer that is iteratively invoked for 11 times, which clearly requires approximately 11 system clock periods. In Tab.4 the results of the synthesis implemented in Xilinx Artix 7 [34] are reported.
Although our HW architecture requires a LUT memory to store the data, our optimization procedure keeps the required resources reduced, at the most equal to those of CORDIC iterative. However, the latter needs a more complex architecture to work, due to the 11 clock period lag between the arrival of the new angle and the correct output. Moreover, the 11 clock period delay may limit the switching frequency whenever f CLK is close to f SW , that is possible when low cost digital controllers are used for high switching converters, i.e. around MHz. On the other side, CORDIC cascade needs more resources and has a higher dynamic power dissipation, making it the worst choice.

VI. CONCLUSION
The proposed HW architecture permits to evaluate the dwelltimes of the gate driver signals used in a SVPWM without the requirement of external reference three-phase signals and with the possibility to change in real-time the values of f C , f SW , θ and V M . Indeed, they are the input signals of our system and can be both internal to the digital controller and external from another controller in order to perform more complex control techniques. It has been possible because trigonometric functions are avoided and an excellent management of the required information to reconstruct the dwelltimes has been proposed. Moreover, the implementation in a FPGA digital controller has shown its compactness in terms of needed resources, which is useful in stand alone system as well as for low cost controller. Such benefits have been also highlighted from a comparison with the well-known CORDIC algorithm. When this architecture is used in a closed-loop system, our block can be seen as a sub-block, which calculates the dwell times and generates the drive signals of the power transistors, and the controller has to define its inputs, namely DAT A IN . It is worth to note that, for the case of the d − q representation, m and θ signals of DAT A IN are, respectively, evaluated through the modulus and the phase of V d and V q , performed by the controller. ALFREDO RUBINO (M'17) received the Laurea degree in physics from the University of Naples Federico II, Naples, Italy, in 1988. In 1989, he was with the Italian National Agency for New Technologies, Energy and the Environment, Portici, Italy. Since 2005, he has been an Associate Professor of Electronics with the University of Salerno, Salerno, Italy. His current research interests include electronics technology and organic electronics. VOLUME -, 2022