A Multipath Output-Capacitor-Less LDO Regulator

A multipath output-capacitor-less low-dropout (OCL-LDO) regulator with feedforward path compensation is presented to achieve low power consumption and fast transient response. The proposed OCL-LDO does not require output capacitance and remains stable at no-load(under 100nA) condition. The proposed OCL-LDO regulator has been implemented and fabricated in a 0.18μm CMOS process, it occupies an active area of 0.0128mm2. The proposed circuit consumes a quiescent current of 0.6μA at no load and 6.9μA at the maximum current load current. Regulating the output at 1V from a voltage supply of 1.2V. It achieves full range stability from 100nA to 100mA, and 100pF is the maximum tolerable parasitic capacitance at output. The measurement results show that the load current rises from 0 to 100mA in 100ns, the undershoot voltage is 388mV, and the settling time is 2.2μs.


I. INTRODUCTION
A system on a chip (SoC) is an integrated circuit that integrates all or most components of a computer or other electronic system. A SoC comprises many sub-circuit blocks, each of which requires different power supply voltages. Analog and mixed signal blocks with high performance and sensitivity have particularly high power quality requirements. This can be achieved by suppressing the output voltage ripple of the switching regulator, making LDO is an ideal choice. The traditional LDO requires adding a large capacitor [1]- [6] to the output to reduce the overshoot and undershoot voltage during load transient response and to maintain LDO stability, but adding a capacitor to the output can be difficult to integrate into a SoC because of space limitations. Integration can minimize the parasitic of bonding and external connections, capacitance, resistance, and inductance. Portable electronic devices such as mobile phones and laptops are very suitable for using OCL-LDO [7]- [11] to solve area limitation.
The OCL-LDO architecture can charge and discharge more quickly due to the less of capacitance at the output, facilitating fast transient response [12]- [17], however, the slew rate required for fast response inevitably causes larger current consumption. In [17], fast transient response is achieved but also a significant quiescent current of 135.1μA, which makes it unsuitable for low power consumption design. On the other hand, the gain-bandwidth (GBW) of LDO is also related to the settling time, the GBW in [18] reaches 3.2MHz, but the transient response is not particularly good. According to [19] [20], the settling time is the time delay caused by the bandwidth of the LDO and the slew rate that regulates the gate of the power transistor to the corresponding voltage. Therefore, to achieve fast transient response, both the bandwidth and slew rate must be increased. A trade-off is also made between bandwidth and gain. By extending bandwidth to higher frequency requires sacrificing the loop gain. According to [19] [20], when the gain is decreased, the error between the output voltage of the LDO and the reference voltage becomes larger.
The line regulation and load regulation will deteriorate due to the decreased gain, and the gain also directly affects the power-supply rejection (PSR). In [18], the dual-loop architecture is adopted to achieve high gain while also improving the bandwidth, which is achieved by the main loop and the sub loop. The overall structure is actually a three-stage amplifier, in which the feedback of the sub-loop is directly connected to the second-stage amplifier, skipping the first-stage amplifier and only passing through the two-  [21], the path from the error amplifier to the power transistor is divided into two, called an adaptive power transistors technique. The main power transistor is responsible for providing current of heavy provides light load current when the main power transistor is turned off. But to maintain system stability at heavy load, 82.4μA of current is needed to make the complex-conjugate poles frequency beyond GBW. Therefore, in [21] requires more quiescent current at heavy load. If quiescent current can be reduced, it means that the same battery capacity can operate at high intensity for a longer period of time. This paper presents a multiple path OCL-LDO with low quiescent current OCL-LDO architecture that uses feedforward path compensation technique. The left halfplane (LHP) zero is generated through a feedforward path to compensate the LDO, ensuring that the LDO remains stable at any load condition, including no-load (under 100nA), and reducing quiescent current at heavy load. Section II discusses the architecture and stability analysis of the OCL-LDO regulator. Section III introduces the proposed architecture and circuit implementation in detail. Section IV discusses the measurement results, and provides a performance comparison. Finally, conclusions are presented in Section V.

A. SMALL-SIGNAL ANALYSIS
In Fig. 2 gmi is the transconductance of each stage, gmpi is the transconductance of individual power transistors, gmf is the transconductance of the feedforward path, Ci is the parasitic capacitance to the ground at the output of each stage, Ri is the output resistance of each stage, and the feedback factor β is 1/2, and CL is much larger than CC and Ci. The equivalent resistance of the output node of the three-stage configuration is defined RO(3-stage) = rO,MP1//rO,MP2//RFB//RLOAD, where rO,MP1 and rO,MP2 are the output resistance of the main power transistor and the sub power transistor respectively. RFB is the resistance of the feedback network, RLOAD is the equivalent resistance of the load, RLOAD is inversely proportional to Iload at time of heavy load, which is the smallest resistance in RO(3stage).

B. ADAPTIVE POWER TRANSISTORS LDO
The small-signal model of the LDO at heavy load in [21] is shown in Fig. 2(a), the simplified transfer function can be expressed as The dominant pole p-3dB is given by From the transfer function (1), the complex-conjugate poles p2,3 and the corresponding Q factor can then be determined as According to (3) and (4), the complex-conjugate poles p2,3 and the value of Q factor depend on gm2, gmp2, and RO(3-stage) in the (3) and (4) terms. At heavy load, the load current is large and RO (3-stage) is small, and the complex-conjugate poles p2,3 is located at high frequency and far away from GBW, which can make the system stable as (8), in [21] a large gm2 was chosen to maintain Q > 1/2. The location of fourth pole is obtained as As the Iload current increases, pushes the pole p4 to a higher frequency. On the other hand, the system exists with two zeros, can be derived as follows: In this case, the relative positions of the pole and zero are shown in Figs. 3(a) and 4(a). At this time, system stability is mainly due to the fact that the frequency of the complexconjugate poles p2,3 frequency is much higher than that of GBW frequency, so the Q factor must be larger than 1/2 otherwise it will split into two real poles. For example, to maintain Q> 1/2, the gm2 is designed to be very large in [21] with IQ is 82.4µA, which is used to maintain the stability of VOLUME XX, 2017 1 Freq heavy load. If cannot be maintained Q > 1/2 to form complex-conjugate poles p2,3 , the system will not be stable regardless of the frequency of z2. On the contrary, if complex-conjugate poles p2,3 can be formed and the frequency is sufficiently high, z2 will be irrelevant to the system stability. However, if the frequency of z2 is too low, it will cause overdamping and affect the settling time. The phase margin of this case is shown as follows

C. PROPOSEDLDO LDO
The overall architecture of the proposed LDO is shown in Fig. 1. The proposed LDO has three paths, and the output of the error amplifier consists of two paths (main path and subpath), and another feedforward path. When the load current exceeds the threshold current ION, it is a heavy load and the operation is performed in the main path. The main path is the first stage amplifier, which compares Vref with the feedback voltage Vfb to generate the VO1 voltage, which is amplified by the second stage amplifier to generate the VO2 voltage, and then controls the main power transistor MP2 to regulate the output current. Because the two-stage amplifier provides higher gain, the main path has better line and load regulation. On the other hand, when the load current is less than the threshold current ION, it is light load, and the operation is in the sub-path. The sub-path includes the first stage amplifier and sub power transistor, by comparing the reference voltage Vref and Feedback voltage Vfb to generate the VO1 voltage, which directly controls the MP1 sub-power transistor to regulate the output current, while the main power transistor MP2 is off, the operation details of which will be described in the next section. The compensation path of the proposed LDO performs by the feedforward path compensation. The feedforward path consists an operational transconductance amplifier as the feedforward amplifier, by comparing reference voltage Vref and the feedback voltage Vfb, and combines its own output current with the output of the second-stage amplifier to generate VO2. The proposed LDO improves the slew rate in the main path and generates a LHP zero for frequency compensation.
The stability of the entire system is achieved by two compensation methods, one of which uses the cascode miller-compensated [22] [23], while the other uses the proposed feedforward path compensation. The cascode miller-compensated is a compensating capacitor CC connected from the output Vout to the source of the firststage amplifier cascode configuration, gmc represents the transconductance of common-source in cascode, 1/gmc is the equivalent input impedance of the small signal modeling of the common-source, and CL is the parasitic capacitance. The OTA in [23] is capable of creating Right-Half-Plane (RHP) zero, and the feedforward path compensation proposed in this paper compensates the stability of the system by turning the RHP zero created in [24] into a Left-Half-Plane (LHP) zero through the feedforward path.
When Iload > ION (Iload > ION → 3-Stage Structure), the main power transistor and feedforward path are activated. The small signal model of the proposed LDO at heavy load is shown in Fig. 2(b). The feedforward path gmf is equivalent to the fast path from the input Vfb to the error amplifier output VO2, the simplified transfer function can be expressed as The low frequency gain Adc and dominant pole p-3dB are respectively given by Hence, the GBW can be obtained as The entire LDO system operation at heavy load, the difference is that since gm2 is no longer as large as Ref. [21], the values of gm2 decreases. Therefore, the Q factor cannot be kept greater than 1/2, when Q <1/2, the complexconjugate poles p2,3 will split into two real poles p2 and p3, as shown in (13) and (14) 1 The highest frequency pole p4 is obtained as As shown in Figs. 3(b) and 4(b), the frequency of p2 will be within the GBW while p3 will be close to the GBW at this case. The zero z1 produced by the feedforward path compensation proposed in this paper, it can compensate for the influence on stability caused by the frequency of pole p2 lower than GBW. The zero z1 generated by the feedforward path is shown below The zero z2 and z3 are as follows The zero z2 is exactly the pole p2 can be observed from the equations (14) and (16), which exactly cancel each other. The zero z3 generated by cascode miller-compensated and the pole p4 formed by the output impedance of the LDO are located at higher frequencies, so the influence on stability is not significant. Therefore, it does not matter if gm2 is not designed to be large enough, even if p2,3 cannot be maintained as the complex-conjugate poles, the feedforward path can still be used for frequency compensation, and the phase margin of this case is shown in the following: The simulated loop gain response of the proposed LDO regulator at different load current conditions is shown in Fig. 5. When no-load (ILOAD = 100nA), the low frequency loop gain is 63.3dB, the phase margin is 56.5° and GBW is 250kHz. When Iload is the smallest and CL reaches the maximum, it is the worst case of this output-capacitor-less LDO stability. So, CL = 100pF is the maximum allowed CL value for this design when no-load conditions. The stability of the LDO can be maintained if the CL does not exceed 100pF.
When light load (ILOAD = 100µA), the low frequency loop gain is 64.5dB, the phase margin is 92°and GBW is 285kHz. On the other hand, when heavy load (Iload = 100 mA) is the maximum load current of the design, the low-frequency loop gain is 85.8 dB, the phase margin is 88° and GBW is 1.21MHz. From the red and blue lines in Fig. 5, it can be observed that as analyzed in II.B and II.C, when [21] is at heavy load (ILOAD = 100mA) the frequency of p2,3 is much higher than GBW, so it has enough phase margin, the z1 in the proposed LDO regulator compensates the influence of p2.
When Iload < ION(Iload < ION → 2-Stage Structure), the error amplifier gm2 turns off the main power transistor and feedforward path, the small signal model of the proposed LDO at light load is shown in Fig. 6 where Adc is the low frequency gain and p-3dB is dominant pole. They are given as Hence, the GBW can be obtained as 1 m C g GBW C  (22) As shown in (19), the non-dominant poles and zeros can be expressed by From (24) and (25), it can be seen that p3 and z1 cancel each other out. At light load, only the frequency of the main pole p-3dB is within GBW as shown in Fig. 6(a), and the main pole p-3dB is formed by the output resistance of the error amplifier.
Ref. [21], I LOAD = 100mA Proposed, I LOAD = 100mA Proposed, I LOAD = 100µA Proposed, I LOAD = 100nA  Due to the frequency compensation, the frequency of p2 is pushed to outside GBW. The pole p2 is proportional to gmp1, and gmp1 is proportional to the load current, so when the load current becomes smaller, the frequency of p2 will decrease. The LDO can maintain stability with noload(under 100nA), the frequency of p2 must exceed GBW, the following equation can be obtained by (22) and (23) as In (26) can be regarded as the ratio of CC 2 /C1CL with gmp1/gm1, considering that when no load condition, the transconductance gmp1 of the sub power transistor is still larger than the transconductance gm1, C1 is the parasitic capacitance of the gate of the sub-power transistor. When at no load condition, the output voltage VO2 of the error amplifier is very close to Vin(supply). The value of C1 is close to the Cgs of the MP1. It can be seen from (8) that as C1 and CL increase, the more difficult to satisfy the equation.
Assuming CL is 100pF (For this design, the maximum tolerable output capacitance is assumed to be), C1 is known to be approximately equal to Cgs,MP1, so the value of the compensation capacitor CC can be calculated and the phase margin of this case is shown in the following

III. CIRCUIT OF PROPOSED LDO REGULATOR
A. SCHEMATIC Figure 7 shows the circuit diagram of the proposed LDO. The first stage of the error amplifier is a folded-cascode configuration with differential input to single-ended output, including transistors M0~M8. MA1~MA7 are dynamic bias gm boosts [11], which are used to enhance the gain and bandwidth of the LDO during heavy load. The second stage of the error amplifier is a single-input single-ended output, composed of M9~M15 transistors. R1 and R2 are the feedback resistances realized by the transistor. β is designed to be 1/2. CL is the equivalent parasitic capacitance of the output node VOLUME XX, 2017 1 Vout. RL is the equivalent resistance of the load, Iload is the LDO output current. The MA1 transistor replicates the load current, and then copy by MA2~MA5 in the dynamic biasing network [11]   bias current of the first stage error amplifier to improve the gm1 transconductance at heavy load. The second stage of the error amplifier consists of the charging and the discharging circuit. The input of the discharge part is the gate of M15. M15 derives the current I15 according to VO1, and copies Idn through the current mirror composed of M13 and M14 transistors. Idn can be regarded as a load current Iload scaled down by a multiple of M such as Iload /M. The input of the charging part is the gate of the M9 transistor, M10 provides the bias current IB2, M9 derives the current I9 according to VO1, and copies I11 by the current mirror composed of the M11 and M12 transistors, and IB2 -I9 = I11, thus IB2 -I9 = Iup. When VO2 ≈ Vin(supply), the main power transistor MP2 will be turned off making the entire LDO system a two-stage configuration. On the contrary, if Iup < Idn, VO2 will be discharged gradually, and the main power transistor MP2 will turn on when Vgs,MP2 is larger than Vt,MP2, and the entire LDO system is a three-stage configuration. To clearly indicate the boundary between the two and three stage configurations, excessive current load will cause the system to switch. Thus the threshold current VOLUME XX, 2017 1 ION is defined according to the condition of the three stage configuration.
The feedforward path can be connected to VO2 as a fast path, and can contribute a left-half-plane zero for frequency compensation, consisting of MF1 ~ MF4 and MF transistors.

B. LOAD TRANSIENT OF SECOND STAGE
Case I (ILIGHT IHEAVY): The circuit operation details when switching from light load to heavy load are shown in Fig.  8(a). By M15, the voltage of VO1 is sensed to replicate the current I15, and then the Idn current is replicated through M13 and M14 to pull down the VO2 voltage. While M9 due to lower VO1 voltage, so that I9 is close to IB2, thus the current of I11 and Iup tend to be nano current. Set Iup = Idn = IB2 -I9 = Iload /M = ION can be obtained (IB2 -I9) M = Iup = ION. When Iload > ION, the LDO changes to a three stage structure. In this design, M is 10000 and IB2 -I9 is approximately 100nA at light load. Theoretically ION = 10000*100nA = 1mA, the difference between 750µA and 1mA is due to the combined feedforward path and channel length modulation. Case II (IHEAVY ILIGHT): The circuit operation details when switching from heavy load to light load are shown in Fig. 8(b). At this moment, VO1 voltage is pulled up, so I9 and I15 currents are reduced, Therefore, I11 approximation Ib2 is equal to Iup and Idn tend to be nano current. When Iup > Idn, the M12 is operating in the triode region, and VO2 will gradually charge to Vin(supply) while turning off MP2.

C. FEEDFORWARD OTA
When switching from light load to heavy load, VFB returns a lower voltage, so the current generated by MF1 is duplicated from MF3 to MF4 to pull down the VO2 voltage, as shown in Fig. 9(a). When switching from heavy load to light load, the VO1 voltage is pulled up and the IF current drops to turn off the feedforward OTA as shown in Fig.   9(b). When VO2 is charged by the second stage error amplifier approximately equal to Vin(supply), so the Vgs of MF2 transistor too small and cut it off, so it is ignored in the small signal model of the two-stage configuration.

IV. EXPERIMENTAL RESULTS AND DISCUSSIONS
The proposed LDO is fabricated in 0.18μm CMOS process. The chip is shown in Fig. 10, and the chip size is 0.128 mm 2 , including a 0.7pF on-chip Cc.  Fig. 11, the proposed LDO consumes quiescent current of 0.6µA at no-load condition and 6.9µA at maximum load. The proposed OCL-LDO keeps the system stable with a parasitic 100 pF capacitor at the output. The load transient response is shown in Fig. 12, where the input voltage of the LDO is 1.2V, the output voltage is 1V. The load transient response is measured without capacitor CL=0 in Fig. 12(a) and with CL=100 pF in Fig.  12(b), Fig. 12(a) shows the transition response when Iload change from 100nA to 100mA with 100ns transition edge times, the undershoot voltage is 388 mV, and the settling time is 1.8μs. On the other hand when Iload change from 100 mA to 100nA, the overshoot voltage is 200mV, and the settling time is 2.2μs. Fig. 12(b) shows the transition response when Iload change from 100nA to 100 mA with 100 ns transition edge times, the undershoot voltage is 383 mV, and the settling time is 1.8 μs. On the other hand when Iload change from 100 mA to 100 nA, the overshoot voltage is 200mV, and the settling time is 2.3μs. The bond wire inductance and ESR (Equivalent series resistance) of the external capacitor will further increase undershoot and overshoot voltages, canceling out the benefits of the capacitor. As can be seen, Vout can track the Vin(supply) changing. The overshoot is 6mV, and undershoot is 6mV at light load (100 µA) and no capacitor. The load transition with Vin is 1.8V is shown in Fig.14, the Iq of the LDO and the VDS of the power transistor are larger Vin is 1.8V than Vin is 1.2V, so the transient and shoot voltages are much better. Fig. 15 shows the measured PSR, while Iload = 100 mA, Vin(supply) = 1.2V, Vout = 1V, and CL = 0. As shown in Fig.  15, using the PSR analysis function of the DSOX4104A oscilloscope, the proposed OCL-LDO regulator achieved a PSR of -35dB at 10kHz. The measured load and line regulations of the proposed LDO is shown in Figs. 16 (a) and (b). Fig. 16(a) shows the effect of changing ΔVin(supply) from 1.2V to 1.8V on Vout at Iload=100μA, the variation of 1mV occurs when Vin(supply)=1.8V. Fig. 16(b) shows the load regulation for Vin(supply)= 1.2V, the maximum variation of output voltage Vout is 3 mV for load current Iload change from 100nA ~ 100 mA.  The measured IQ versus Iload is shown in Fig. 17, with IQ increases as Iload increases until Iload is 100mA. As the main power transistor is slowly turned on, the IQ of the second stage of the error amplifier increases as well. The second stage of the error amplifier and the main power transistor MP2 are activated gradually when the load current is approximately 750μA, which is similar to the design mentioned in section III.B. At full load condition, the current efficiency is greater than 99.99%. The measured performance of the proposed OCL-LDO regulator is compared with recent research in table I. The figure-of-merit (FOM) in this paper uses the definition provided in [18], where ∆t in the FOM definition is the edge time, ∆Vout is the largest of the overshoot or undershoot voltage, IQ is the quiescent current, ∆Iload is the range of the load current that the LDO can supply, and L is the process. The smaller the FOM is the better, although the FOM values in comparison table Ref [14] and Ref [17] are better than the LDO proposed in this paper. But load regulation and line regulation are not good enough. The [18] showed the best load regulation and line regulation, but the largest overshoot and undershoot voltage during load current transition. Ref [21] has a larger bandwidth due to the advantage process than the proposed circuit, so the main difference is the component parameters and Iq. And it cannot be stabilized during heavy load after shrinking Iq. Also, a current of about 80uA is used in the pre-stage of the power transistor to improve load transition and system stability.

V. CONCLUSION
The output capacitor-less low-dropout regulator (OCL-LDO) proposed in this paper uses a 0.18 μm CMOS process and achieves a lowest quiescent current of 0.6μA and capacitorless architecture can still be stable at a load current of only 100nA by using the proposed feedforward compensation and multipath structure, the quiescent current at the maximum load current is 6.9μA. The load current range is from 100nA ~ 100mA, and the settling time is 2.2μs, the maximum undershoot voltage is 388mV. Good load regulation and line regulation of 10(μV/mA) and 5(mV/V) are obtained by using a multistage and multipath LDO architecture