Theory and Original Design of Resistive-Inductive Network High-Pass Negative Group Delay Integrated Circuit in 130-nm CMOS Technology

This paper develops an original design method of high-pass (HP) negative group delay (NGD) integrated circuit (IC). The considered HP-NGD IC is based on a passive topology which is essentially composed of resistor-inductor (RL) network. The paper presents the first time that an unfamiliar HP-topology is designed in miniaturized circuit implemented in 130-nm CMOS technology. The theory of unfamiliar HP-NGD topology based on the voltage transfer function (VTF) analysis is elaborated. The design equations with synthesis formulas of the resistor and inductor are established. The HP-NGD IC CMOS design methodology is introduced. The feasibility of the miniature NGD IC implementation is approved by design rule check (DRC) and layout versus schematic (LVS) approaches. The HP-NGD passive IC is designed in 130-nm CMOS technology. The HP-NGD topology is constituted by RL-network based on CMOS high Ohmic unsalicided N+poly resistor and symmetrical high current spiral inductor. Then, the schematic and layout simulations are presented. The validity of the 130-nm CMOS HP-NGD design is verified by the investigation of 225 μm × 215 μm chip two different miniature circuit proofs-of-concept (POC). The HP-NGD behavior is validated by comparison between the calculated, and schematic and post-layout simulations of the HP-NGD POCs carried out by a commercial tool. As expected, the group delay and VTF magnitude diagrams are in very good correlation. HP-NGD optimal value, NGD cut-off frequency and attenuation, of about (-31 ps, 141 MHz, -3 dB) and (-47 ps, 204 MHz, -5 dB) are obtained from the miniature POCs.

Nevertheless, because of its counterintuitive property, so far, few electronic design and fabrication engineers are familiar to the NGD circuit designing. For this reason, further academic and more didactical research must be developed for the non-specialist engineers to open world widely the NGD engineering.
The NGD function was initially experimented with optical system operating with negative group velocity (NGV) [13][14]. Then, the existence of the NGD function was an attractive topic for some curious RF and microwave design researchers. It was found that the negative refractive index (NRI) metamaterials are susceptible to operate with NGD effect [15][16][17]. Some remarkable microstrip microwave passive circuits with left-handed metamaterial structures were designed and experimented in the microwave frequency range [15][16][17][18][19][20]. The NRI metamaterials based NRI circuits were initially implemented with periodical passive cells [16][17]. To overcome to such technical bottleneck, deeper design study of lumped circuits was performed based on the equivalent resonant circuit approach. The topology of split ring resonator based microstrip structure [18] was identified as one of the most elementary NGD cells. However, it was emphasized that the metamaterial based NGD passive circuits [15][16][17][18] are either significantly lossy or implemented with large size printed circuit boards (PCBs). Then, more complex microwave function was innovatively imagined with tunable metamaterial resonator using varactor diodes [15]. Another variant of metamaterial NGD circuit with resistive lossy left-handed transmission lines (TLs) was proposed [20]. To overcome the challenge in term of size reduction, NGD compact circuit designs based on TL elements were raised last decade [21][22][23].
Despite the progress of the microwave NGD circuit design methods and identified passive circuit topologies, there is a lack of understanding about the basic physical meaning of the NGD function.

C. NGD CIRCUIT TYPE CLASSIFICATION
To answer to such a curious question, an innovative pedagogical theory enabling to classify the different categories of NGD topologies was initiated [24]. This fundamental NGD circuit theory was inspired from the similitude with the filter theory [24]. In different with the filter, the NGD circuit classification depends on the group delay (GD) diagram. The NGD function class can be easily understood with the frequency band where the GD is negative. For example, the class of low-pass (HP) NGD function was identified [25][26]. However, because the magnitude behavior of HP-NGD circuit, some confusions maybe raised by electronics design engineers.
Some curious remarks maybe stated on the confusion between the HP-NGD function and high-pass (HP) filter. To clarify the difference between these two electronic functions in the present paper, we study the design of HP-NGD circuit. VOLUME XX, 2021 1

D. NOVELTY OF THE PAPER
The main originality of the research work is focused on the miniaturization of the HP-NGD circuit based on the resistive-inductive (RL) passive network. In the best of the authors knowledge, despite the development of integrated circuit (IC) microelectronic design [27][28][29][30][31], no research work is available in the literature on the HP-NGD circuit. A lot of study was conducted on the CMOS design of electronic devices as frequency synthesizer [27], wireless transceiver [29], inductors and transformers [30] and active inductors [31]. The present paper develops, the first time, the design study of miniature HP-NGD IC in 130-nm CMOS technology.

E. OUTLINE OF THE PAPER
The present research work is organized in five main sections described as follows: • Section II introduces the theory of unfamiliar HP-NGD circuit. The considered passive topology is based on RL-network. The theoretical study is based on the voltage transfer function (VTF) elaboration. • The synthesis formulas allowing to determine the resistor and inductor components in function of the desired HP-NGD specifications are established in Section III. • Section IV develops the design method of the HP-NGD IC in 130-nm CMOS technology. The design methodology including the schematic and layout implementation in the CADENCE-VIRTUOUSO® environment is described. • Section V discusses the validation of the HP-NGD theory and the 130-nm CMOS design in the frequency domain. The feasibility study is based on the comparison of results from the theoretical model, schematic circuit simulation and post-layout simulation (PLS). • Finally, the paper conclusion is drawn in Section VII.

II. THEORETICAL STUDY OF THE RL-NETWORK BASED HP-NGD PASSIVE TOPOLOGY
The present section introduces the HP-NGD passive circuit theory including the associated basic specifications. After the VTF consideration, the design and synthesis equations are developed in the following subsections. It is composed by a series resistor Ra associated to parallel RL-network constituted by resistor R and inductor L. The initial step of the VTF calculation is based on the Laplace variable s=jω, in function of angular frequency ω and complex number j²=-1. Similar to all classical RLnetwork based electronic circuit, the HP-NGD analysis is elaborated by considering the input and output voltages Vin(s) and Vout(s), respectively. By definition, the VTF model is obtained by:

A. TOPOLOGICAL DESCRIPTION
The associated transmittance is a complex number () Nj  which can be expressed as: The phase is defined by: Then, the less familiar parameter for the HP-NGD analysis is the GD expressed as: These basic parameters serve to develop the HP-NGD specifications.

B. IDEAL SPECIFICATIONS OF HP-NGD FUNCTION
The NGD analysis depends essentially on the responses of the frequency dependent GD expression defined by equation (5). The familiarization to the NGD analysis consists in the interpretation of sign of the GD in function of the frequency band.

1) EXISTENCE CONDITION OF HP-NGD FUNCTION
An electronic circuit can be assumed as a HP-NGD function if its VTF satisfies the following three conditions: VOLUME XX, 2021 1 • Condition 1: The GD must be positive at very lowfrequencies (VLFs) where the frequency is approximately equal to zero. The condition in function of GD at VLFs denoted GD0 can be written as: • Condition 2: The GD must present a cut-off angular frequency denoted by 2 nn f =  . This frequency parameter is the roof of equation: • Condition 3: The two previous condition implies that the GD at the higher frequency must be ideally always negative. Therefore, in the NGD frequency band indicated by Fig. 2(a), we must satisfy the following inequation: The graphical illustration of these conditions is represented by the GD diagram depicted by Fig.  2(a). In addition to the GD response, the VTF magnitude response behave generally as shown in Fig.  2 ) is associated to typical passive topology as introduced by Fig. 1.

2) PARTICULAR CHARACTERISTIC FREQUENCIES OF HP-NGD FUNCTION
Similar to the typical LP-NGD one, the HP-NGD function is characterized by certain frequencies associated to particular values of the GD defined by equation (5).
In the following paragraph, we take the real positive variables N0 and Na, and angular frequency ωa. The following three particular frequencies are considered to characterize an HP-NGD circuit: We can remark from the diagram of Fig. 2(b) that the magnitude at VLFs can be specified by: • Cut-off frequency ( n   ): The magnitude can be defined by: • Optimal frequency ( a   ): This frequency is the root of equation: At this optimal frequency, the GD reaches its minimal negative value: Then, the optimal magnitude can be defined by: The concrete application of these specifications to our RL-network based topology is elaborated in the following subsection.

C. FREQUENCY-DEPENDENT RESPONSES
The NGD analysis is based on the RL-circuit VTF model defined by equation (1). From where, we determine the transmittance: As defined by equation (3), the associated magnitude is equal to: Emphatically, the associated phase, which is defined by equation (4), is written as: Then, it yields the GD of the RL-network topology under study is given by: The exploration of each of these expressions lead to the synthesis method of the HP-NGD circuit in the following section.

III. HP-NGD NGD ANALYSIS AND SYNTHESIS EQUATIONS
The theoretical approach including the HP-NGD analysis and synthesis of the circuit topology under study is developed in the present section.

A. ANALYTICAL VERIFICATION OF HP-NGD EXISTENCE CONDITION
The three conditions cited in previous Subsection II-B can be explored in more details as follows: • Verification of Condition 1: At VLFs, we can demonstrate that the GD established previously becomes: We can remark that condition of inequation (6) is unconditionally verified for any values of R, Ra and L.
• Verification of Condition 2: By means of GD written in relation (17), the NGD cut-off frequency defined by equation (7) implies the equation: The positive real solution of the previous polynomial equation is: We underline that the VTF magnitude at the cut-off frequency defined by equation (10) is equal to: a n a R N RR • Verification of Condition 3: Let us denote a>1 a real positive defined by: For the optimal frequency determined from equation (11), this coefficient is equal to: We can demonstrate that by means of GD expressed in relation (17), the optimal GD can be expressed as: We remark that this GD, , is always negative whatever the values of resistors, R and Ra, and inductor L. At the same frequency, the magnitude expressed in equation (15) becomes: We can analytically demonstrate that Na and Nn are linked by the relation: 3 an NN = (26) which implies: (27) In inference, the RL-network topology is theoretically classified as an HP-NGD topology.

B. INPUT AND OUTPUT IMPEDANCE ANALYTICAL EXPRESSIONS
The access impedances can play a significant role on the performance of electronic circuit matching in function of the surrounding interface components. The present section investigates analytically on the access impedance of our HP-NGD cell.
The input impedance of the circuit introduced by Fig.  1 can be expressed as: From this expression, we can underline that: • At VLFs which corresponds to ω≈0:

C. HP-NGD SPECIFICATION OBJECTIVES
The HP-NGD circuit parameters can be established in function of: • The targeted value of NGD cut-off frequency fn, • The optimal frequency fa, • The GD optimal value GDa<0.
• And the voltage amplitude Vmax and maximal power P0 which are linked by relation: By taking into account the input impedance, this power can be reformulated by: VOLUME XX, 2021 1 In addition to the previous relation, the other resistor and inductor values can be determined from equation system: The following subsection treats the synthesis equations of the HP-NGD topology. The synthesis formulas consisting in calculating the values of components R, Ra and L as components of the RL-network topology under study will be established in the next subsection.

D. ELABORATION OF THE HP-NGD SYNTHESIS EQUATIONS
The resistor Ra can be determined knowing the input voltage amplitude and IC maximal power by means of equation (28): Emphatically, substituting the previous expression into the attenuation given by equation (21), we have the following resistor synthesis formula: During the synthesis, the NGD optimal attenuation Na<1 is linked to the optimal frequency and GD by the relation:

E. ANALYTICAL RELATIONS BETWEEN THE HP-NGD PARAMETERS
Knowing the previous formulas of resistors, we can demonstrate that the optimal and cut-off frequencies given by the coefficient expressed by equation (23)  Furthermore, the HP-NGD topology presents a property linked to the different parameters, Na, GDa, and a  .
Substituting the formulas of resistors established by equation (35) and equation (36) into the GD expression proposed by equation (24), we have: By using the coefficient of equation (36), the previous expression transforms as: With these expressions, a HP-NGD IC in 130-nm CMOS technology can be designed with the following method.

IV. HP-NGD CMOS IC POC DESIGN METHOD AND PROCESS
The present section deals with the HP-NGD IC design methodology. The different steps to be fulfilled allowing to design the HP-NGD chips are described. The HP-NGD POC is aimed to be designed in 130-nm CMOS technology.

A. DESIGN METHODOLOGY
Similar to classical CMOS ICs of classical electronic functions (filter, amplifier, oscillator and many other devices) [27][28][29][30][31], the HP-NGD function design must start from the circuit specifications to the final layout design. In more clear view, the methodology of HP-NGD ICs can be illustrated by the design flow summarized by the successive steps of Fig. 3. This HP-NGD CMOS IC design flow can be described as follows. In Step 1, the design process must begin with the choice of the HP-NGD cut-off frequency and NGD optimal value which will imply the optimal attenuation. The designer can refer to the specifications of Figs. 2.
In Step 2, knowing the HP-NGD specifications, the constituting resistor and inductor values can be calculated in the present step. The ideal component values can be calculated via formulas (35), (36) and (40). In Step 3, the range of the calculated component value must be verified in the library of the simulation software (for the present study, Cadence-VURTUOSO®). Then, the feasibility of the HP-NGD can be verified by the VOLUME XX, 2021 1 comparison between the calculated results from the VTF model given in equation (14) and the schematic simulation. In Step 4, after schematic ideal simulation, the layout can be drawn according to the schematic. The IC is implemented with respect to the design rule check (DRC) with high Ohmic unsalicided N+poly resistor and symmetrical high current spiral inductor. The DRC is a program that uses layout database to check every design rule involved in layout. After the preliminary drawing of the layout, the DRC is needed to ensure the ideal schematic and layout IC consistency. For example, the width and spacing of each wire constituting the layout must be correctly implemented and should not violate the specified minimum value. The DRC ensures that the design can be manufactured within the limits of production process. The layout versus schematic (LVS) step then makes it possible to compare the diagram of a circuit with its layout in order to check whether they are comparable, and list any differences between them In Step 5, this step consists of analyzing the content of the HP-NGD circuit layout in order to extract the active elements (transistors, diodes) but also the parasitic capacitances and resistors. An extracted view is thus obtained, permitting to simulate the circuit while considering the parasitic components.
In Step 6, the results of the PLSs are compared with the specifications of the HP-NGD circuit. Any modifications are then made, in particular at the layout level, to improve the results.
Following the previous design flow, HP-NGD IC POC result is investigated in the following subsection.

B. DESCRIPTION OF THE SCHEMATIC DESIGN OF HP-NGD LUMPED CIRCUIT
The first stage of the pre-simulation was carried by the lumped HP-NGD POC design from two different software standard tools for electronic and microwave circuits. The present study is performed in the frequency band from 1 MHz to 1 GHz.
The design of the passive circuit POCs were performed in the schematic environment of: • The ADS® software from Keysight Technologies®: The ADS® schematic of the designed RL-network based HP-NGD POC is presented in Fig. 4. Two circuits with different parameters were considered. The main parameters of the RL lumped elements constituting the circuit are R, Ra and L. The schematic circuit design includes the AC voltage source. The input and output accesses are represented by Port1 and Port2, respectively.
• And the CADENCE®-VIRTUOSO® software: The corresponding chip design was designed by taking into account the 130-nm BiCMOS parameters. The schematic displayed in Fig. 5 represent the two different ICs of the HP-NGD POCs.
The HP-NGD IC schematic parameters were calculated from synthesis formulas (35), (36) and (40) with respect to the desired specifications. The chosen circuit parameters are indicated by Table I. From the chosen lumped components, we can design the corresponding layout. The CMOS components are designed following the library of 130-nm technology CADENCE-VURTUOSO®.
The following subsection describes the DRC based on the HP-NGD IC layout designs. VOLUME XX, 2021 1

C. DESCRIPTION OF THE LAYOUT DESIGN
The STMicroelectronics BiCMOS-130 nm manufacturing process was chosen for this study because of its component integration potential in the range of HP-NGD desired specification values. Due to the relatively large size of the components, expensive manufacturing processes such as 28 nm-FDSOI are not needed. Figs. 6 display the two layouts of the designed CMOS IC chipsets.
Each layout is designed with 225 µm × 215 µm size. The circuit is expected to operate with Vmax=5 V. The resistors and inductor were expected to be implemented under the manufacturing process minimum square area. The SISO circuit whole layout area is occupied by the two resistors in left and the large spiral inductor. The 100 µm × 4.9 µm size resistors are implemented in 100nm thickness poly-Si on 4.5-relative permittivity dielectric insulator. Each resistor is guard-ring surrounded in order to ensure their polarization and the ground plane connection through the dielectric substrate. The inductor is implemented in Al-metal spiral octagon with 0.0145 mm² surface over 1 µm thickness. All the layout component interconnections are Cu-based interconnect metallization with 0.1 µm thickness. The range of the geometrical parameters (width, length, number of turns, diameter, Silicium area) of the considered resistor and inductor layouts in function of the constituting materials are addressed in Table II and Table  III, respectively. The minimal resonance frequency is also indicated.  The feasibility study based on the HP-NGD function validation will be examined in the following subsection.

V. FEASIBILITY STUDY OF THE HP-NGD THEORY AND THE DEVELOPED CMOS IC POC DESIGN
To validate the HP-NGD function of the designed CMOS IC, frequency (AC) and transient Cadence-VIRTUOSO® simulations were performed. The present section deals with the feasibility study of the HP-NGD 130-nm CMOS IC. Then, the calculated and Cadence® simulated results are discussed. Comparisons between the calculated ("Calc."), schematic ("Schem.") and post-layout simulation ("PLS") simulated VTFs were carried out. The calculated results were generated from MATLAB® program of VTF modeled by equation (1).
The following subsections discuss the obtained validation results.

A. HP-NGD VALIDATION OF CMOS CHIP1
The results discussed in the present subsection correspond to VIRTUOSO® AC schematic and PLS results from CMOS chip1 shown in Fig. 5 and Fig. 6(a), respectively. Figs. 7, Figs. 8 and Figs. 9 reveal the GDs, magnitudes and phases of POC represented by CMOS chip1, respectively. The plot of Fig. 7(a) presents the large frequency band representation. Then, narrower frequency band result of GD from 100 MHz to 900 MHz is introduced by Fig. 7(b) to highlight the HP-NGD characteristics as expected from diagram of Fig. 2(a). These plots highlight the HP-NGD function validity by means of the comparisons of the calculated, schematicbased and PLS results. Figs. 7 validate the HP-NGD behavior with a good correlation between the calculation, schematic simulation and PLS. Table IV addresses the associated HP-NGD parameters. The notable differences of the magnitudes displayed by Figs. 8 between the schematic and postlayout simulations are mainly due to via effect of the interconnect due to layout step which involves the creation of parasitic resistances and capacitors.

Calc.
Schem. PLS  Because of the CMOS inductance parasitic and design imperfection, it can be found that the NGD optimal value and attenuation from CMOS IC present a difference of about GDa≈-31 ps and Na≈-1.45 dB at fa≈246 MHz. For more convenient illustration of the validation, the following subsection examines the AC responses of the other POC.

B. HP-NGD VALIDATION OF CMOS CHIP2
Figs. 10, Figs. 11 and Figs. 12 present the frequency domain comparison results of GDs, magnitudes and phase results from chip2. The designed schematic and layout are shown in Fig. 6(a) and Fig. 6(b). Once again, Figs. 10 confirm the HP-NGD behavior. In addition, a good correlation between the calculated model, and schematic simulation and PLS of GDs proposed by Figs. 10 and the associated phases of Figs. 12 is observed. in the frequency domain. Table V addresses the associated HP-NGD parameters. In this case of study, the calculated optimal GD and attenuation are of about GDa≈-47 ps and Na≈-3.3 dB at the frequency fa≈357 MHz. It can be pointed out that the magnitude attenuation of Figs. 11 from CMOS IC presents a difference of about 1.7 dB.

Calc.
Schem. PLS  The observed difference corresponds to around 18% relative error. The differences between the calculation, schematic simulation and PLS are mainly due to the interconnect. The resistor CMOS design induces an undesired losses and imperfection. Hence, the inductor CMOS design is susceptible to operate with undesired resonance and parasitic effects. To reduce these parasites to a minimum, the layout is re-worked in order to use large metal lines as well as a large number of vias in parallel.

C. ACCESS IMPEDANCES ANALYSIS
By curiosity, one may curiously wonder about the input and output matching of the HP-NGD CMOS circuit under investigation. To address such a curiosity, the present subsection is dealing with the analysis of the input impedance Zin expressed in equation (28). We remind that the output impedance shown in equation (31) is equal to Ra=20 Ω and Ra=15 Ω for chip1 and chip2 POCs, respectively. The frequency dependent plots of the input impedance magnitudes and phase of the two POC circuits analyzed in the previous subsection are displayed in Figs. 13. As pointed out in Subsection III-B, the input impedance is approximately equal to Ra=20 Ω for chip1 and Ra=15 Ω for chip2 at VLFs. Then, the input impedance is equal to R+Ra=25 Ω for both chip1 and chip2 at very high frequencies. We can underline that the proposed HP- For more convenient illustration of the validation, the following subsection examines the sensitivity analyses with respect to the geometrical parameters of the resistor and inductor layouts.

D. MONTE CARLO (MC) SENSITIVITY ANALYSES (SAs)
The present SAs were performed by considering the geometrical parameter +/-5% variations of the implemented resistor and inductor by means of schematic and PLSs. For the last case, the resistor and inductor parameters are indicated by Table II and Table III, respectively.
The following paragraphs present the obtained results following the MC analyses via distribution statistical probability (DSP).

1) SCHEMATIC MC SA WITH N1=1000 TRIALS
In this first case of study, the SAs were based on the CADENCE-VIRTUOSO® simulations by considering +/-5% variations of the HP-NGD POCs initial parameters (through standard deviations). The present paragraph reports the MC SAs of HP-NGD POC with N1=1000 trials. The obtained data was considered for the statistical analyses of the samples in the intervals delimited by the one, two and three times multiple of standard deviation. The statistical analyses from the computed results lead to the flat typical Gaussian variations with assessed values addressed by Table VI. Fig. 14(a), Fig. 14(b), and Fig. 14(c) present the histograms and DSPs of the NGD cut-off frequency, GD optimal value and magnitude attenuations from chip1 POC schematic, respectively. Then, Fig. 14(d), Fig. 14(e), and Fig. 14(f) illustrate those of from the schematic of the other POC represented by chip2, respectively.
The following paragraph examines the results of the post-layout analyses.

2) POST-LAYOUT MC SA WITH N2=300 TRIALS
The SAs were carried out based on the CADENCE-VIRTUOSO® simulations of the HP-NGD POCs by considering +/-5% variations of each geometrical parameter from the initial POC characteristics (through standard deviations). In this case, the simulations were performed on an extracted view of the circuit. This model view considers all the parasitic resistors and capacitances created during the layout-design step. The MC analyses of the post-layout MC SAs of HP-NGD POC were run with N2=300 trials.

VI. CONCLUSION
An original investigation on the HP-NGD miniature circuit is developed. The analytical theory enabling to determine the resistive and inductive parameters in function of the desired HP-NGD specifications is established. An innovative design method of HP-NGD IC in 130-nm CMOS technology based on the Cadence-VURTUOSO® commercial tool is presented. After the synthesis equation formulation, the HP-NGD CMOS chip design methodology is described in function of the technological requirement. The different design steps including the DRC and LVS consideration are described.
To validate the theory, two POC of RL-network are designed and simulated. The design feasibility of each components and the overall chip is introduced. Then, the validity of the HP-NGD behavior is validated by the comparison between the calculations, schematic simulation and PLS. The obtained results showing the NGD cut-off frequencies and the NGD optimal values are in good agreement. It can be summarized from the present study that the main challenges to conquer during the design phase of CMOS HP-NGD circuit are: • The choice of the HP-NGD specifications in function of the considered CMOS technology.  Table II. • And the geometrical parameter limitations of the inductor width, diameter of the loop and number of turns in 130-nm CMOS technology as indicated in Table III. The manufacturing process and test is scheduled as the next step of the present study. In addition, the feasibility study will open the NGD circuit applications in many electronic systems. For example, a technique of electronic system unwanted effects can be avoided with NGD equalization [7][8][32][33] and the design of improved UWB system with reduced delay [34]. VOLUME XX, 2021 1 Prof. Dr. Blaise RAVELO (M'09) is currently University Full Professor at NUIST, Nanjing, China. His research interest is on Multiphysics and electronics engineering. He is a pioneer of the negative group delay (NGD) concept about t<0 signal travelling physical space. This extraordinary concept is potentially useful for anticipating and prediction all kind of information. He was research director of 11 PhD students (10 defended), postdocs, research engineers and Master internships. With US, Chinese, Indian, European and African partners, he is actively involved and contributes on several international research projects (ANR, FUI, FP7, INTERREG, H2020, Euripides², Eurostars…). He is member of IET Electronics Letters editorial board as circuit & system subject editor. He is member of scientific technical committee of Advanced Electromagnetic Symposium (AES) 2013 and IMOC2021. He is ranked in Top 2% world's scientists based on years (2020-2021) by Stanford University, US (https://elsevier.digitalcommonsdata.com/datasets/btchxktzyw/3) with Google scholar h-index(2021)=24 and i10-index(2021)=72. He is member of research groups: IEEE, URSI, GDR Ondes, Radio Society and (co-) authors of more than 360 scientific research papers in new technologies published in int. conf. and journals. He is lecturer on circuit & system theory, STEM (science, technology, engineering and maths) and applied physics. Dr. Ravelo is IEEE member since 2007 and regularly invited to review papers submitted for publication to international journals (IEEE TRANSACTIONS ON MICROWAVE  THEORY AND TECHNIQUES, IEEE TRANSACTIONS