An Optimized Space Vector Based Switching Algorithm With Reduced Switching Transitions for Impedance Source Inverter

In a 3L-VSI, to realize reference vector, maximum of six switching per sub-cycle are permitted. A similar condition is looked for in 3L-ZSI (z source inverter). The current continuous SVPWM methods of 3L-ZSI have adopted two approaches to meet the desired condition. These are a selection of sub-cycles generating six and eight switching employing correct volt-second balance. The sub-cycles generating eight switching has the demerit of increased losses. Here a new switching pattern has been proposed to optimize the number of switching. The dependency of the modulation index and sub-cycle duration on the switching frequency has also been discussed. With the increase in carrier frequency, the proposed PWM technique offers a decrease in switching losses compared to the existing ones. This leads to the improved efficiency of 3L-ZSI.To verify the efficacy of the proposed technique, simulation and prototype results are presented.


I. INTRODUCTION LIST OF SYMBOLS AND ABBREVIATIONS
The Z-source inverter [1] is used for various applications in 2-L and multilevel [2]- [18] inverters. Topology and PWM technique development [4]- [18], are two major research areas of 3L-ZSI. As compared to the two level ZSI, the operation principle and switching state selection procedure of the 3L-ZSI is more complex. The early attempt to extend the concept of ZSI to the three-level dc to ac conversion can be seen in [4] where two LC impedance network has been used between input dc source and neutral point clamped three level inverter circuitry. The two major modifications in VSI which transform it to a ZSI are; (i) the placement of LC network between dc source and inverter switches, and (ii) suitable modification in the PWM technique. The modified switching pattern of ZSI has one added state called shoot-through state (ST). During shoot-through state, the LC network is intentionally shorted through one or all phase legs for charging the inductors. The sine triangle comparison based on various PWM techniques of 3L-ZSI can be seen in [4]- [17]. It is clear from [4]- [17] that, at least five reference signals and two triangular carrier signals are required to achieve the shoot through condition. So, the practical implementation of the sine triangle comparison-based technique is too much complex. On the VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ other hand, the space vector PWM (SVPWM) approach offers easier implementation with more flexibility in the switching states selection. The SVPWM for the 3L-ZSI has been reported in [18], [24] and [25]. In these SVPWM techniques, ST state has been implemented using the time duration of small vectors only. In this aspect, these SVPWM techniques are equivalent to the continuous edge insertion sine triangle PWM proposed in [4]. However, the main difference between the continuous edge insertion PWM of [4] and SVPWM techniques of [24]- [25] is that, in former, every sub cycle causes exact eight switching and in later, the number of switching per sub cycle depends upon the position of reference vector (i.e. some sub cycle offers eight switching and other offers six switching. Reference [24] concludes that the number of switching per sub cycle are six in their SVPWM technique. But it is not true. For example, consider the condition when reference vector is in the region 2(a) (Fig.4 of [24]). The switching pattern in this region is shown in Fig. 5(b) of [24]. This switching pattern causes eight switching per sub cycle. These types of regions have not been noticed in [25] also. There is maximum six permissible switching states when any continuous/discontinuous PWM (sine triangle or SVPWM based) technique is applied to the 3L-VSI. The researchers tried to achieve similar condition in 3L-ZSI in order to ensure that the insertion of ST states does not cause increase in switching losses. As discussed earlier, when continuous edge insertion PWM of [4] is used in 3L-ZSI, none of the sub cycle offers six switching. This is the main drawback of [4]. However, the authors of [4]   proposed technique is implemented in a new configuration of the inverter, CDBC 3L-ZSI. As compared to the T-type and diode clamped ZSI configurations, CDBC ZSI offers some advantages, explained in section II. Section III discusses the concept of SVPWM and the ways of ST state introduction. The proposed and existing SVPWM is discussed in section IV. A brief comparison of frequency, losses, efficiency and THD is presented in section V. To verify the merits of the proposed technique, simulation and prototype results are presented in section VI. Finally, section VII concludes this paper. Fig. 1 represents a new topology of 3L-ZSI. The conventional LC impedance network has been considered in combination with CDBC (controlled diode bridge clamped) 3L-VSI topology [19]. Each phase leg of 3L-ZSI is linked to the midpoint of dc bus through a bidirectional switching device, a combination of single IGBT and four diodes; so, the naming, CDBC 3L-ZSI is given in this paper. Table 1 shows the voltage levels corresponding to different switching states of this inverter configuration. A = R, Y, B and X = r, y, b For the medium power application, the CDBC version has the following merits: At any instant, for powering the load, conduction of one switch per phase leg is needed compared to two switches as in diode clamped ZSI. So, switching and conduction losses are comparatively less. Saving of one IGBT and associated gate driver circuitry compared to diode clamped and T-type ZSI [25].

III. SPACE VECTOR BASED PWM TECHNIQUE FOR 3L-ZSI
The 3L-VSI has been controlled effectively as a 2L-VSI in [21], [24]. A similar approach is implemented in 3L-CDBC ZSI and the corresponding diagram is presented in Fig. 2(a)  and (b). The equivalent null vectors are small vectors used as shoot-through states. Medium and large vectors are treated as equivalent active vectors in each two-level hexagon. As per the location of the original reference vector, the corresponding corrected reference vector is shown in 2L-hexagon. Then, the dwell time of each voltage vector is found out using two level SVPWM principal. For example, please see Fig. 2(b) subsector 1, the corrected reference vector (Vcr) can be realized using V1, V13 and V7 having time interval Ta, Tb and Tz respectively.Description of switching vectors is presented in Table 2. Following equations are used for dwell time calculation (hexagon-1, subsector-1) [24].
T a , T b are the equivalent active vector durations and T z is the equivalent null vector duration per half sub cycle. The original reference vector (V cr ), for modulation index range '0.66-1.15' pass through four sub-sectors namely 1, 2, 5 and 6 as shown in Fig. 2(b). For ease of explanation, the sub-sectors are further designated as outer (5, 2) and inner sub sector (6, 1). The small vectors in 3L-ZSI are equivalent to null vectors in 2L-ZSI. Though, these small vectors do not produce zero line-voltage. So, at higher modulation index it is not possible to achieve nearest three vector approach using full shoot through. So, upper lower shoot through is adopted here for the analysis of 3L-ZSI.

A. SELECTION OF SHOOT THROUGH STATES
In order to have balanced voltage boosting in 3L-ZSI, the time interval of upper shoot through and lower shoot through must be equal within a sub cycle. Also, the corrected reference vector should be realized using the nearest three vectors to achieve quality waveform. Keeping above mentioned conditions in mind, there are following two main approaches for shoot through selection.

1) USING SMALL AND MEDIUM VECTORS DURATION
In this approach switching vectors are generated by comparing sinusoidal and triangular signals. This approach has been chosen in [6]. It offers desired six switching per sub cycle over full fundamental period but the shoot through states duration is not equal resulting unequal voltage boosting. The complexity of equalizing the both shoot through state (U_ST/L_ST) of a sub cycle is the major demerit of this approach. So, this approach is not popular in SVPWM domain.

2) USING ONLY SMALL VECTOR DURATION
ST state can also be implemented using the duration of small vectors only. For example, for shoot through insertion, continuous edge insertion PWM technique proposed in [4] uses only small vectors. The main drawback of this technique is that it generates eight switching in every sub cycle. The SVPWM switching pattern of [24], [25] also uses small vectors for ST state insertion, but in these cases, not all the sub cycles cause eight number of switching. For example, when SVPWM switching pattern of [24], [25] is applied, the outer sub-sectors of each hexagon cause eight switching and inner sub-sector of each hexagon cause six switching per sub cycle. The analysis of [24] and [25] reveals that the modulation VOLUME 10, 2022 index and switching cycle duration cumulatively decides the spent duration of reference vector in these sub-sectors. This is discussed in next section. The proposed technique also uses small vector duration for the insertion of shoot through states.

IV. PATTERN OF SWITCHING STATES
In this paper maximum constant boost (MCB) control technique [25] has been used to decide shoot through duration within a sub cycle. The total duration of small vectors is minimum when original reference vector is at α = 30 • . As per MCB principal, the small vectors duration when original reference vector is at α = 30 • should be taken as the reference duration of ST state for each sub cycle. Mathematically, it can be stated that: T Z is equivalent null vector duration within a sub cycle and T ZSC is the equivalent null vector interval at angle α = 30 • of the reference vector V cr . Or it can be said that, this is the reference duration for ST state of each sub cycle. T ZSX is leftover equivalent null vector duration in a sub cycle. When upper and lower ST states are used using single LC impedance network, the relation between modulation index and ST duty ratio can be written as: With single LC impedance network, 'd sh offered by UL_ST scheme is half as compared to the F_ST scheme. This is written as: Boost factor is related to shoot through ratio as: From (5), (6) and (7) it is concluded that for a particular value of modulation index, boosting offered by UL_ST scheme is lower as compared to the F_ST scheme of 3L-ZSI using single LC impedance network. This paper considers UL_ST scheme. This technique offers better output waveform quality because of the nearest three vector (NTV) switching. NTV switching is not possible using F_ST scheme.

A. LATEST SVPWM SWITCHING STATES PATTERN
The latest SVPWM switching sequences of 3L-ZSI are reported in [24], [25] is explained here as under.     Fig. 3(a) represents the switching pattern for inner subsec-tor1, hexagon 1, for 3L-VSI. Fig. 3(b) represents the switching pattern for 3L-ZSI. The switching per sub cycle is just six in both switching patterns of Fig.3. Table 4 displays the switching sequences of outer subsectors (5, 2) of the hexagon 1. These are same as that of inner subsectors (i.e. ST state is always applied after first switching state and before the last switching state) using the existing SVPWM technique of 3L-ZSI [24], [25].

2) SHOOT THROUGH INSERTION PROCESS IN THE OUTER SUBSECTORS
Consider subsector 5 of the  Fig. 4(a) and Fig. 4(b) displays the switching pattern of 3L-VSI and 3L-ZSI respectively. The number of switching per sub cycle are six and eight using the switching pattern of Fig. 4(a) and Fig. 4(b) respectively. Similarly, all the outer subsectors of equivalent 2L-hexagons cause eight switching per sub cycle for the case of 3L-ZSI using existing SVPWM [24], [25].   Table 3, the inner subsectors already offered minimum switching (six per sub cycle) using existing SVPWM switching pattern. It is not possible to further reduce switching per sub cycle using any continuous SVPWM technique in these regions. So, the switching pattern in the inner subsectors is kept same with the proposed SVPWM. Table 4 shows that there is total 8 switching per sub cycle using existing SVPWM switching pattern. Similarly, other 5 hexagon offers 8 switching per sub cycle in the outer subsectors. Another important observation form the Table 4 is that, the ST state is always applied after first equivalent null state (i.e. ' + O O ) and before second equivalent null state (i.e. 'O − − ). However, when the upper ST state 'U − − of Table 4 is shifted to the position after the state 'O − − (i.e., at last position as shown in Table 5), one switching per sub cycle is reduced.

2) SHOOT THROUGH INSERTION IN THE OUTER SUBSECTORS
The proposed pattern is shown in Fig. 4(c). It is found that the proposed technique generates seven switching per   sub cycle in all outer sub sectors. It is also observed that the location of the shoot through state is not same in outer and inner subsectors. For example, the position of ST states in the Fig. 3(b) is different from the Fig. 4(c).

V. COMPARISON OF EXISTING AND PROPOSED SVPWM PATTERN A. SWITCHING FREQUENCY
Previous section concludes that the outer subsectors switching are more compared to inner sub subsectors of each 2Lhexagon. Table 6 summarize the switching per sub cycle.
It is also observed that for a fixed carrier frequency, with decrease in modulation index, the half sub cycles in the inner subsectors decreases and outer subsector increases. In Table 7, three sets of carrier frequency have been taken and the mapping of half sub cycles has been done depending upon their position in the corresponding subsector. Each equivalent VOLUME 10, 2022 two-level hexagon is symmetrical (i.e., number of sub cycle and pattern is same for each). As in the outer sub sectors, number of half sub cycles increases, the inverter switching frequency also increases. Therefore, switching frequency of 3L-ZSI increases with the decrease in modulation index. This is contrary to the case of 3L-VSI where switching frequency is independent of reference vector position.
Proposed and existing patterns are implemented in CDBC 3L-ZSI and corresponding switching frequencies are summarized in Table 8. Again, three cases of carrier frequency have been considered and the switching frequency is calculated for the different values of modulation index. The switching transitions during hexagon-to-hexagon changeover has also been taken into account in order to have exact value of switching frequency. Consider a case of Table 8, when carrier frequency is 10.65 kHz and modulation index is 1. At this condition, switching frequency using proposed and existing SVPWM switching pattern is 5700Hz and 6025Hz respectively. This shows, a reduction of 325Hz per switch is achieved using proposed switching pattern. It suggests the merits of proposed pattern even at higher modulation index. The same advantage of the reduced switching frequency is equally valid in diode clamped and T-type ZSI using proposed SVPWM switching pattern.

B. LOSSES AND EFFICIENCY
Switching and conduction loss contributes a significant portion of total power loss in an inverter. The average conduction loss per sub cycle across IGBT and diode can be obtained as follows: The switching losses can be further categorized as turn-on and turn-off energy losses and in case of IGBT it is defined as: For diodes, only reverse recovery losses are considered and can be expressed as: The above-mentioned parameters are taken from datasheets. The total power losses using proposed SVPWM pattern and the existing SVPWM pattern has been plotted in Fig. 5. Fig. 5(a) and 5(b) shows the total power losses of the inverter at the carrier frequency of 1.65 kHz and 5.25 kHz respectively. It is clear from the Fig. 5(a) and Fig.5(b) that, for a fixed carrier frequency, as the modulation index decreases the difference between the total power loss of proposed SVPWM pattern and existing SVPWM pattern increases. Fig. 6(a) and Fig. 6(b) shows the comparison of efficiency between proposed and existing switching pattern at the carrier frequency of 1.65 kHz and 5.25 kHz respectively. From Fig.6, it can be concluded that the proposed SVPWM pattern offers better efficiency as compared to existing pattern. The difference between the efficiency offered by both approaches increases with decrease in modulation index and increase in carrier frequency.

C. THD CONTENT
The line voltage and line current THD offered by both approaches is listed in Table 9. The THD percentage is almost same in the both approaches. It confirms the suitability of proposed switching pattern without compromising the quality of the output waveforms.

VI. PASSIVE COMPONENT DESIGN
Considering the high frequency ripple component, LC network is designed as follows. The inductor current peak to peak ripple is expressed as: 28970 VOLUME 10, 2022  The average capacitor voltage is expressed as: The allowable ripple in inductor current is: Here r L is the allowable ripple current in percentage and the average inductor current is represented as: Putting (5), (12) and (13) into (11), the expression for 'L' can be written as: Similarly, the capacitor voltage ripple component is expressed as: The allowable ripple of capacitor voltage is: Using (5), (12), (16) and (17), the expression for 'C' is obtained as:

VII. RESULTS
The proposed SVPWM switching pattern have been validated using Matlab/Simulink software and experimental prototype using the parameters mentioned in the Table 10. Fig. 7 shows the simulation waveforms of gating pulses for switch SR1, SR2 and SR3 employing proposed switching pattern. For the positive half cycle of output pole voltage, switch SR1 conducts in conjunction with bidirectional switch SR2. Switch SR3 remains OFF during this period. For negative half cycle of output pole voltage, switch SR3 conducts in conjunction with bidirectional switch SR2. Switch SR1 remains in OFF position during negative half cycle of pole voltage. Output line voltage (V ry ) is shown in Fig. 8(a). The line voltage waveform confirms that the proposed technique VOLUME 10, 2022  follows nearest three vector approach for generating correct volt sec balance. For 'M = 1 , 'B' comes out to be 1.15 using equation (5) and (7). Simulation waveform of line voltage has a peak of 113.5V which is almost equal to the expected theoretical value of 115V according to the relation 'B.V dc . Simulation waveform of the pole voltage (V ro ) shown in Fig. 8(b) has a peak of around ±56.5 V. This value matches with the expected theoretical value of ±57.5 V according to the relation ±B.V dc /2.
The lower dc link voltage (V nx ) is shown in Fig. 8(c). It switches between zero and −B.V dc /2.Upper dc link voltage (V px ) is shown in Fig.8(d). It switches between zero and +B.V dc /2. Fig. 9(a) and Fig.9(b) shows the neutral point capacitor voltages for 'M' = 1 and 'M = 0.73' respectively.    The neutral point capacitor voltages(V C1 , V C2 ) are balanced around the half of the source voltage (V dc ). In order to have experimental verification of the proposed SVPWM switching technique, a laboratory prototype has been built. The photograph of laboratory prototype is shown in Fig.10. Fig.11 represents the switching pulses of the three IGBTs of 'r' phase leg. These are exactly similar to the simulation waveforms of Fig7. This ensures the practical feasibility of the proposed technique. Fig. 12(a) presents the prototype results of line-voltage (V ab ), pole-voltage (V ao ),inductor current and line current. Dc link and capacitor voltages are shown in Fig. 12(b). The prototype results are same as that of simulated one.

VIII. CONCLUSION
This paper highlights the specific locations of the three-level space vector diagram where switching can be optimized for the case of three level Z-source inverter. One switching per sub-cycle has been reduced using the proposed SVPWM pattern as compared to the existing techniques. It reduces the inverter switching frequency and total power losses without compromising the output voltage/current THD. So, an increase in the inverter efficiency has been observed. This paper also highlights the dependency of switching frequency on modulation index. The CDBC 3L-inverter configuration has been successfully employed in 3L-ZSI. This SVPWM approach is equally applicable with the same advantages to T-type 3L-ZSIs.