A Generalized High Gain Multilevel Inverter for Small Scale Solar Photovoltaic Applications

The contribution of renewable energy, especially small-scale solar photovoltaics (PV), is increasing exponentially in the energy sector. In general, high gain DC-DC converters are used as front-end converters to increase the low voltage of PV panels; further, the DC-AC converter (multilevel inverters) is used for standalone AC loads or grid integration. To avoid the front-end converter and achieve both objectives, this paper proposes a nine-level quadruple boost inverter topology for small-scale solar PV applications. The proposed topology operates on a switched capacitor technique to boost the voltage, and has self-voltage balancing of capacitors. This paper presents the detailed operation of the proposed nine-level inverter, voltage stress calculations, loss analysis, and designing of circuit parameters. In addition, a high-gain generalized multilevel inverter (MLI) topology is also reported. Furthermore, the proposed MLI is compared with competitive inverters available in the recent literature. The proposed MLI topology has advantages such as a minimum total standing voltage and a reduced component count; it can also produce bipolar voltage inherently. The performance of the proposed MLI topology is validated through the MATLAB-based simulations and an experimental prototype. Further, the experimental results are presented by considering load variations, modulation index variations, and output frequency variations. The experimental efficiency obtained is in the range of 96.2% to 92.8% for proposed 9-level inverter.


I. INTRODUCTION
The energy consumption of the world is continuously increasing day-to-day. To meet the increased load demand, largescale renewable sources, especially solar photovoltaic, are integrated into conventional power generation. Generation of photovoltaic energy at a single location in large amounts and transmission of its power to long distances reduce the efficiency of the system. Recently, distributed generation has been introduced to overcome this problem and increase the efficiency of the system [1], and, the percentage of PV generation through solar rooftop has increased by a large quantity, approximately more than 20% of total PV generation capacity is through solar rooftop [2]. The small-scale solar PV system for rooftop applications is of 0.5kw to 2kw, and voltage ratings range are from 60 Volts to 100Volts [3].
The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao .
Generally, solar PV is preferred to operate in a grid-connected mode to avoid bulky and costly batteries. The solar rooftop is connected to a low voltage distribution network of 415V (3-) and 230V (rms) for 1-shown in Figure.1. To get compatibility between low DC voltage PV systems and AC grid voltage, the high gain DC-DC converters [4] are used at the front end for the DC-AC converters. For DC-AC conversion, an enormous number of MLI topologies are proposed in the literature. Among those, diode clamped [5], flying capacitor (FC), and cascaded H-bridge multilevel inverters are the popularly known topologies. Diode clamped MLI and FC MLI have the problem of unbalanced capacitor voltages, which requires an additional voltage balancing circuit [6]. Cascaded H-bridge MLI is modular in structure, requiring more isolated DC sources [7].
Recently, various reduced switch nine-level inverter topologies have been presented in [8]- [11]. These topologies use fewer switches and diodes to get the same number of VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ levels compared with the basic MLI topologies. In the topologies mentioned above, the gain of the topologies is limited, and they may not be suitable for applications that require boost in input voltage. In [10], [11], topologies require more isolated DC sources, and the number of sources increases with an increase in voltage levels. In [12]- [21] are some recently proposed topologies based on the switched-capacitor (SC) technique. In these topologies, each capacitor is connected alternatively in parallel and series with the DC source in each cycle of output voltage. They are charged in parallel and discharged to load in series. In [12]- [14], the topologies generate five-level output with a gain of two. In [15]- [17], topologies produce seven-level output voltage with a triple boost. In [19]- [21] topologies generate nine-level output voltage. Although these topologies generate a nine-level output voltage, they have a low voltage boosting ability (gain = 2). In [24], a generalized boost MLI is proposed based on the switched-capacitor technique; it consists of series-parallel connection of switches, diodes, capacitors for level generation, and H-bridge for polarity generation. Reference [25] Topology has a hexagonal switched cell and switches capacitor units with two isolated DC sources. The inverter in [26] has a quasi-resonant unit with switched capacitor technique for level generation. It uses one inductor in the resonance circuit, and H-bridge is used for polarity generation. In [27], a generalized step-up MLI has repeating switched capacitor units and one DC source. Each switched capacitor unit has five switches and one capacitor, and for an increase in two levels, it requires a switched capacitor unit. The inverter in [28] has two T-type modules connected both ends of repeating cross-connected SC units. Each cross-connected unit has six switches and two capacitors. The number of levels and the gain of the MLI increase with the number of SC units. In [29], a cascaded H-bridge is formed with capacitors in place of DC sources. The capacitors are charged using a switched capacitor technique with a single DC source and additional switches and diodes. Reference [30] Generalized MLI with ladder structure has a repeating unit of one isolated DC source and three switches. It has only one capacitor to get a gain of two by using the switched capacitor technique. In [31], a generalized switched capacitor MLI consists of a T-type module, a halfbridge, a repeating SC unit, and cross-connected switches. Each switched capacitor unit has one capacitor and three switches. In [32], a nine-level switched capacitor-based MLI with quadruple boost has been introduced for PV grid integration applications. It has been introduced for transformer-less grid integration. In [33], a hybrid T-type nine-level inverter with gain three is introduced for PV applications. It has four capacitors for voltage boosting, and a five-level T-type module is used at the output end. In [34], a reduced switch quadruple boost nine level inverter is introduced for electrical vehicle and industrial drive applications. In [36], a five-level switched capacitor-based inverter and is extended to generalized topology with high gain. The repeating unit consists of four switches and a capacitor. In [37], a generalized high gain inverter is formed by a repeating switched capacitor (SC) unit of two switches, one diode, a capacitor and a H-bridge is used for polarity generation. In [35], a seven-level switched capacitor topology is proposed. The gain of the topology is three and the total harmonic distortion (THD) ranges for seven-level is of 25%. In small scale PV grid integration applications, the input DC voltage is much less compared to the grid voltages. To get compatible grid voltages with the low voltage PV panels, it requires more gain and low THD limits. To meet these requirements in this paper the topology in [35] is improved to produce nine-level with gain of four and better THD which also reduces the size of filter requirement. Further, its high gain generalized structure has (2N+1) levels with a gain of N is proposed. It is based on the switchedcapacitor technique, and each repeating SC unit has three switches and one capacitor. It has low voltage stress on the switches, leading to low TSV of the topology. The proposed topology has the following merits: • Single DC source is used to get 9-level voltage and 2N+1 in generalized topology.
• The minimum voltage stress on switches.
• Self-voltage balancing of capacitors.
• Four out of 13 switches have only one transition in a cycle and are operated at a load frequency (50Hz).
• Inherent polarity generation without H-bridge. The remainder of the paper is organized as follows. Section 2 explains the proposed nine-level topology, generalized topology, voltage stress on switches, self-voltage balancing of capacitors, modulation scheme, calculation of capacitance and efficiency. The comparative study is done with recently proposed nine-level and generalized topologies in Section 3. Section 4 contains a simulation results and analysis. Section 5 contains experimental analysis of the proposed topology. Finally, in Section 6, the complete work is concluded.

II. PROPOSED TOPOLOGY
The proposed quadruple boost nine-level topology shown in Figure.2. It is structured with 1 DC source, 3 capacitors (C 1 , C 2 & C 3 ) and 13 switches in which 11 unidirectional switches (g 1 -g 6 & g 9 -g 13 ) and 2 bidirectional switches (g 7 & g 8 ). These switched capacitors are charged by using a series-parallel technique. Each capacitor is individually charged to V dc and discharged to load by connecting in series with the DC source to obtain a high voltage gain. The output voltage of nine levels has ±4V dc , ±3V dc , ±2V dc , ±V dc , and zero levels. To avoid source and capacitor short circuit, switches pair (g 12 , g 13 ) and (g 10 , g 11 ), are operated complimentary. Switches g 10 , g 11 , g 12 , and g 13 have only transitions (on to off & off to on) for each load voltage cycle. Therefore, these switches operate at the load frequency (50Hz) and have low switching losses, which improve the overall efficiency of the topology. Switches (g 1 -g 5 ) and (g 12 -g 13 ) have a maximum blocking voltage (MBV) of V dc , since most of the switches have low voltage stress, the total standing voltage (TSV) of the topology will be a low value. The voltage stress on each switch (g 12 -g 13 ) are represented beside every switch in multiples of V dc as shown in Figure.2. where '1' denotes V dc and '3' denotes 3V dc . The proposed topology has 3 capacitors; each of them is charged to V dc . The 3 capacitors are made to balance at V dc by sequential charging and discharging in every cycle of load voltage. The gate signals for the switches of the proposed topology are given according to Table 1. In this table at each voltage level turn-on and turn-off states of the switches are shown as 1 & 0 respectively. The charging, discharging, and floating conditions (without charging or discharging) of the capacitors are represented as '↑', '↓' and '-' respectively.

A. OPERATING MODES OF PROPOSED TOPOLOGY 1) POSITIVE VOLTAGE LEVELS
It has two possibilities for zero voltage level; the switches g 1 , g 6 , g 10 , and g 12 are turned on to get zero voltage.
Simultaneously, C 1 is charged to V dc by turn-on the switches g 3 , g 4 , g 5 , and g 7 as shown in Figure.4(a). zero voltage level can also be obtained by turn-on the switches g 5 , g 9 , g 11 , and g 13 and simultaneously, switches g 1 , g 2 , g 3, and g 8 are turned on to charge C 3 to V dc . In the +V dc state, switches g 1 , g 6 , g 10 , and g 13 are turned on to obtain the +V dc voltage level. Simultaneously, switches g 3 , g 4 , g 5 , and g 7 are turned on to charge C 1 . During this time, C 2 and C 3 are in floating condition, as shown in Figure.4(b). In +2V dc state, charged C 1 is connected in series with the DC source to obtain +2Vdc level by turning on the switches g 1 , g 2 , g 7 , g 10 , and g 13 . Simultaneously, C 2 is charged by turning on the switches g 4 , g 5 , and g 8 . During this voltage level, C 3 will be in floating condition as shown in Figure.4(c). To obtain the +3V dc voltage level, charged C 1 & C 2 are connected in series with the DC source by turning on the switches g 1 , g 2 , g 3 , g 8 , g 10 , and g 13 . Simultaneously, by turning on the switches g 5 and g 9 ; C 3 is charged to V dc as shown in Figure.4(d).
In +4V dc voltage level, charged C 1 , C 2 and C 3 are connected in series with DC source by turn on switches g 1 , g 2 , g 3 , g 4 , g 9 , g 10 , and g 13 as shown in Figure.4(e).

2) NEGATIVE VOLTAGE LEVELS
In −V dc state, the switches g 5 , g 9 , g 11 , and g 12 are turned on to get the −V dc level. Simultaneously, switches g 1 , g 2 , g 3 , and g 8 are turned on to charge C 3. During this state, C 1 & C 2 are in floating condition as shown in Figure.4(f). In −2V dc state, the switches g 4 , g 5 , g 8 , g 11 , and g 12 are turned on to connect the charged C 3 in series with the DC source. Simultaneously, switches g 1 , g 2 , and g 7 are turned on to charge C 2 to V dc . At this level, C 1 is in floating condition as shown in Figure.4(g). In −3V dc state, the switches g 3 , g 4 , g 5 , g 7 , g 11 , and g 12 are turned on to connect charged C 2 and C 3 in series with the DC source. Simultaneously, by turning on switches g 1 , g 6 ; C 1 is charged as shown in Figure.  In −4V dc state, the switches g 2 , g 3 , g 4 , g 5 , g 6 , g 11 , and g 12 are turned on to connect C 1 , C 2 and C 3 in series with the DC source as shown in Figure.4(i).

B. PROPOSED GENERALIZED 2N+1 LEVEL MLI
In grid integrated PV applications, due to the requirement of higher grid voltages, the gain of proposed quadruple boost 9-level inverter may not be compatible in some cases. To achieve high gain with better THD, a generalized topology is proposed with extension circuit consists of one unidirectional switch, one bidirectional switch, and a capacitor for PV grid integration applications. By adding 'x' extension circuits to the proposed topology, the output voltage with '2x+9' levels and 'x+4' gain can be obtained. A generalized 2N+1 level with gain = N is shown in Figure.3 by extending this repeating unit highlighted in blue. The generalized topology consists of N+7 unidirectional switches, N-2 bidirectional switches, N-1 capacitors and one DC source. The proposed  generalized topology has a MBV of (N-1) * V dc for only four switches and (N+3) switches are having a low blocking voltage of V dc . This makes the TSV lower even with an increase in levels. The TSV (p.u) for the proposed generalized topology is (7N-5)/N.

C. VOLTAGE STRESS ON THE SWITCHES AND SELF-VOLTAGE BALANCING OF SWITCHED CAPACITORS
In the proposed topology, the maximum blocking voltage (MBV) of 3V dc is for 4 switches (g 6 , g 9 , g 10 & g 11 ). Bidirectional switches g 7 & g 8 block the voltage of is 2V dc and 7 switches (g 1 -g 5 & g 12 -g 13 ) have low blocking voltage of V dc . As the proposed topology is having low blocking voltages for more number of switches, it is having minimum total standing voltage (TSV).
The TSVp.u of the inverter is calculated using Equation (1).
Here, Vsw_off is the blocking voltage of each switch, VD_off is the diode reverse blocking voltage, and Vomax is the maximum output voltage.
TSVp.u. for the proposed quadruple boost nine-level inverter topology is 5.75. To represent the voltage stress on each of the switches at different voltage levels a bar chart is drawn in Figure.5. Where, the voltage stresses on switches are represented with different colours in multiples of Vdc over each level of output voltage.
Capacitors are balanced by continuously connecting in series, parallel with DC source which continuously discharge and charge respectively in each cycle of output. C 1 charges in +V dc and zero levels and discharges in +4V dc , +3V dc and +2V dc . C 2 charged at +2V dc and discharges at +3V dc & +4V dc levels. C 3 charged at +3V dc and discharges in +4V dc voltage level. Similarly, in the negative cycle by alternatively charging and discharging, the capacitor voltages are balanced.

D. MODULATION SCHEME
The level-shifted pulse width modulation (LSPWM) scheme is used to generate gate signals to the switches. To generate gate signals for a nine-level inverter LSPWM has 8 triangular carrier signals (Cr 1 -Cr 8 ) and 1 sinusoidal modulating sinusoidal signal (M) as shown in Figure.6. By comparing this modulating signal with carrier signals, it generates 8 pluses (X 1 -X 8 ) and these pulses are given to 13 switches through the logic gate pattern shown in Figure.7 according to Table 1. The logic pattern is obtained by adding these pulses. Here, X 1 represents comparison of (M, C r1 ), X 2 represents (M, C r2 ), and so on. Similarly for negative cycles X 8 represents comparison of (M, C r8 ), X 7 represents comparison of (M, C r7 ), VOLUME 10, 2022 and so on. The amplitude modulation index (Ma) is changed from 0 to 1 by varying the magnitude of the sinusoidal signal from 0 to 4 and the carrier amplitude is kept constant as 1. Frequency modulation is varied by changing the carrier signal frequency, and modulating signal frequency is kept constant at load frequency (50Hz). With the increase in carrier frequency the harmonics are shifted to higher order but with the increase in carrier frequency to large value the switching losses increases, as number of turn-on and turn-off transitions increases per cycle of output. Therefore, the carrier frequency here is limited to 5 kHz.

E. CALCULATION OF CAPACITANCE
The value of capacitors used in any circuit is defined by considering the longest discharge time of the capacitors. In the proposed nine-level topology the capacitor C 1 will discharge during 2V dc , 3V dc and 4V dc voltage levels. C 2 discharges during 3V dc & 4V dc voltage levels of 3V dc and the C 3 discharges at 4V dc voltage level. In Figure.6 the times of transitions of each voltage level are shown as t 1, t 2, t 3 . . . t 6 . These values are calculated as shown in equations (2)- (7): The maximum amount of discharge in each cycle is obtained by integrating the current through the capacitors during the longest discharge time at maximum loading conditions (Equation (8)).
where, Q Ci is the maximum amount of discharge in i th capacitor. t a , t b are start and end times of discharge period.
To design a capacitor with k (p.u) ripple, the amount of charge that a capacitor can store should be greater than Q/k.
The value of i th capacitor is Similarly, the values of capacitors C 1 , C 2 , and C 3 are calculated from equation (9) [22].

F. LOSS AND EFFICIENCY CALCULATIONS
There are two types of losses in semiconductor devices: switching losses and conduction losses. Switching losses occurred due to delay in turn-on and turn-off process. Conduction losses are due to on-state resistance of the semiconductors [23].

1) SWITCHING LOSSES
Switching losses occur due to non-instantaneous turn-on and turn-off processes. When the switch is turned on, the collector current (I C ) starts rising after the gate-emitter voltage (V GE ) becomes higher than threshold voltage (V T ). After the V GE becomes greater than the V T , the collector-emitter voltage (V CE ) starts to decrease. It takes a t on of time for V CE to reach V sw_on and I C to reach I sw_on . During this t on , both V CE and I C have finite nonzero values which lead to on-time switching losses, as shown in Equation (10). Similarly, during the turn-off process, both I C and V CE are finite values for t off time as shown in Figure.8, which leads to the turn-off switching losses as shown in Equation (11). where P SL,i(ON) is the turn-on switching loss of the i th switch, and P SL,i(OFF) is the turn-off switching loss of the i th switch.
The number of turn-on and turn-off of each switch and diode are calculated from the equation (12). Where, N s_on & N s_off are the number of turn-on and turn-off in one cycle respectively. f m is modulating frequency and f cr is carrier frequency.
The total switching losses of all switches are calculated by adding the total turn-on and turn-off losses of all switches from Equation (13).
where P SL(Total) is the total switching losses and N sw is the total number of switches in the MLI topology.

2) CONDUCTION LOSSES
Conduction losses in the semiconductor switches occur during the on-state of the switches. During the on-state, losses occur due to on-state resistance of the switch and voltage drop across the switch. The conduction losses of the switches and diodes can be calculated by Equation (14) and Equation (15), respectively: where, P con_sw is conduction loss of semiconductor switch, P con_D is conduction loss of diode, V sw_on is on-state voltage across switch (V DS ), V D_on is on-state voltage across diode, R sw_on and R D_on are on state resistance of switch and diode respectively. i sw_avg , i sw_rms , I D_avg , i D_rms are average & RMS currents of switch and diode respectively.
In each level of output voltage, the number of switches and diodes are in conduction changes, therefore the conduction losses are separately calculated in each voltage level. In +V dc , +3V dc levels seven switches and two diodes are in conduction. During the +2V dc level eight switches and two diodes are in the conduction, and in +4V dc voltage level VOLUME 10, 2022  only seven switches are in conduction. The same repeats for the negative cycle of the output voltage as shown in Equation (16).
The total conduction losses are obtained by adding the conduction losses at each level as shown in Equation (17).
The overall efficiency of the multilevel inverter is given from Equations (18) and (19): where, η is MLI efficiency, V dc & I dc are input DC voltage and current respectively, P con(total) and P SL(total) are total conduction and switching losses respectively of all switches.

III. COMPARISON WITH OTHER RECENTLY PROPOSED TOPOLOGIES
The proposed 9-level quadruple boost inverter topology is compared with some of the recently proposed topologies shown in Table 2. The comparison is done based on the number of switches, number of series diodes, number of capacitors, number of DC sources, number of gate drivers, gain of the topology, TSV (p.u) of the topology, MBV (in multiples of Vdc) of the topology and whether polarity is generated inherently or not. In topology [24] having eight switches and six diodes. Even though it is having less number of switches the TSV of the topology is very high which increases the rating of the switches. It also uses H-bridge for polarity generation. In [26], the quasi-resonant structure for boost in voltage and having high TSV. It has an extra inductor in the resonance circuit, and uses an H-bridge for polarity generation. The topology [27] has a large number of switches and driver circuits that decrease the efficiency of the inverter. In [28], have more switches compared to the proposed topology, it also has an additional capacitor, and the TSV is higher compared to the proposed topology. In [29], topology has more number of switches, five additional diodes, and one additional capacitor compared to proposed topology. In [32], topology has one switch less than proposed topology but it is using an extra capacitor and more gate drivers than proposed topology. The TSV and MBV are higher than the proposed topology. In [33], topology has an equal number of total components but it has high TSV and it has low voltage gain of three. In [36], topology uses a greater number of switches and having high value of TSV compared to the proposed topology. In [34], topology is having is having large MBV and more voltage rating capacitor than proposed topology. Reference [37] uses H-bridge for polarity generation which leads to a high value of TSV and MBV. The proposed topology is having less TSV and MBV then compared to other topologies in Table 2, which shows it is having low voltage stresses on the switches. It has an equal or less total number of components while compared with others in Table 2.
The comparison for proposed generalized topology and recently proposed other competitive generalized topologies is shown in Table 3. In [25], the topology consists of N+3 more switches compared to the proposed topology and uses the H-bridge for polarity generation. [26] uses fewer switches compared to the proposed topology, but the total number of components are equal and TSV and MBV are high compared to the proposed topology. It also uses H-bridge for polarity generation. In [27], topology is having 2N-4 more switches compared to the proposed topology. In [28], the topology has two additional switches & one additional capacitor than the proposed topology. Topology in [29] is having a greater number of switches, diodes and capacitors compared to proposed topology. In [30], topology has fewer switches compared to the proposed topology, but it has a gain of only 2. In [31], topology has five switches more than proposed topology and has low voltage gain of N/2. In [36], topology has a greater number of switches compared to proposed topology and TSV is increasing largely with increase in levels. The TSV of [37] is more compared to the proposed topology and it uses additional H-bridge for polarity generation which increases the MBV. In Figure.9 (a) a comparison is made for the number of semiconductor switches (N sw ) with respect to gain (N) of generalized 2N+1 level inverters. In Figure.9 (b) total number of components (N Total ) sum of switches, diodes and capacitors is plotted with respect to gain (N). In Figure.9 (c) the total standing voltage (TSV) is plotted with respect to gain (N) for the topologies listed in the Table 3.

IV. SIMULATION RESULTS AND ANALYSIS
The performance of the proposed topology is analyzed under different conditions in MATLAB/Simulink. The ratings of the components used in the simulation are V dc = 100V and C 1 = C 2 = C 3 = 2200µF. In Figure.10, the load voltage, current, and balanced capacitor voltages of the proposed topology under RL load of 100 +120mH are shown for the DC source voltage of 100V and the amplitude modulation index (M a = 1). The output voltage is nine levels with 400V peak amplitude, and three capacitor voltages are balanced at 100V. The voltage THD during this case is 16.49% and fundamental component magnitude of 389.9V shown in Figure.11.   In Figure.12 the load variations are made for no-load, 50 and 50 +100mH and their respective load voltage, current and capacitors voltages are analyzed. During these load   changes, the load voltage is maintained constant and the load current is varied as zero current, phase current, and lagging current. And capacitors voltage ripple is in permissible limits of below 10% during these load changes. In Figure.13 the load variations are done from 100 +25mH to 100 +75mH   to 100 +150mH and their load voltage and current are shown. The load current decreases in magnitude and becomes more lagging as inductive load increases.
In Figure.14 the input DC voltage is varied from 50V to 100V and the corresponding load voltage, current, and capacitors voltages are displayed. In both the cases the load voltage is having nine levels but the magnitude of peak has been doubled. The capacitor's voltages are balanced from 50V to 100V. In Figure.15 modulating signal frequency has changed from 50Hz to 250Hz and the corresponding load voltage and current are displayed. By increasing the supply frequency, the   load current magnitude has decreased due to the increasing load impedance. The load frequency has been changed from 50Hz to 250Hz, which resembles that the proposed topology is suitable for high-frequency applications.
In Figure.16 load voltage and current are analysed for amplitude modulation index changes for M a = 0.8, M a = 0.9 and M a = 1. For these M a variations, the voltage levels are retained, but the width of the +4V dc and −4V dc levels is changed, which resembles the fundamental component variations as 319.4V, 360.7V, 389.9V for M a = 0.8, 0.9, 1 respectively, and their corresponding voltage THD are 20.02%, 17.85%, and 16.49%. In Figure.17 load voltage and current are shown for the modulation index variations for M a = 0.4, M a = 0.7, and M a = 1. With these M a variations, the output voltage levels are changed to five, seven, and nine for M a = 0.4, 0.7, 1 respectively, and the corresponding load current magnitude is changed. This happens because in LSPWM when M a = 0.4 the modulating signal is compared with only four carriers (C r3 -C r6 ). During M a = 0.7 it was compared with only six carrier signals (C r2 -C r7 ) and for M a = 1 it was compared with the eight carriers (C r1 -C r8 ). In Figure. In Figure.19 the load voltage and current are observed for the changes in the switching frequency (carrier frequency) of f sw = 1 kHz and f sw = 5 kHz. With the increase in carrier frequency, the number of switching in each voltage level increases; which leads to increase in switching losses. But by increasing the carrier frequency the harmonics are shifted to higher order which reduces the size of the filter in grid connecting applications. In Figure.20 efficiency of the proposed topology is plotted for load variations of 0 to 1.5 kW. For the efficiency calculations switching losses and conduction losses of MOSFET and its antiparallel diode are considered.

V. EXPERIMENTAL RESULTS
Experimental studies are done on the prototype shown in Figure.21. The components and ratings used in the experimental setup are listed in Table 4. The control scheme  for PWM signals shown in Figure.7 is designed in the Dspace1104 controller.
In Figure.22 (a) load voltage and current of the proposed 9-level topology are shown for R = 100 load and for RL = 100 + 150mH is shown in Figure.22 (b). In Figure.23 (a), the load change has been made from R load to RL load, and the transition is observed. The current is changed from in-phase to lagging. In Figure.23 (b) the load has been changed from RL = 100 +150mH to RL = 100 +300mH, with the increase in inductive load value the 25186 VOLUME 10, 2022  current has decreased and became more lagging. In Figure.24 the modulating frequency is changed from 125Hz to 50Hz and the change in output frequency is observed and it is noted that proposed topology is suitable for high frequency applications. In Figure.25 (a) the amplitude modulation index is changed from Ma = 1 to 0.8 the voltage levels are retained but the width of the +4V dc & −4V dc level has been reduced as the number of comparisons between M and C r1 has reduced.
In Figure.25 (b) the modulation index is changed from 1 to 0.7 the output voltage levels are reduced from nine to seven as the modulating signal is not got in comparison with C r1 & C r8 . In Figure.25 (c) the modulation index is changed from 1 to 0.4 as a result, the voltage levels change from nine to five. In this case the modulating signal has been compared with C r3 , C r4 , C r5 and C r6 . In Figure.25 (d) the modulating index is changed from 1 to 0.2 then the voltage levels are reduced from nine to three, as in this case the modulating signal is compared with only two carriers C r4 & C r5 . In Figure.26 (a) load voltage and current are shown for RL load at a switching frequency (carrier frequency) of 5 kHz, in Figure.26 (b) for a switching frequency of 2.5 kHz and in Figure.26 (c) for a switching frequency of 1 kHz. With reduced switching frequency, the number of transitions in each voltage level has been reduced. In Figure.27 the voltage of the capacitors C 1 , C 2 and C 3 are shown and it shows that the three capacitor voltages are balanced to V dc . In Figure 20 the efficiency of 9-level prototype is calculated for load variations and compared with simulation efficiency. The prototype has maximum efficiency of 96.2%. Overall, with the results and analysis shown above, the properties mentioned of the proposed topology are validated.

VI. CONCLUSION
This paper proposes a high gain generalized MLI and quadruple boost nine-level inverter for small scale solar PV applications. It has the advantages of low switch stress and self-voltage balancing of capacitors. A comparative study is conducted with recent literature. The proposed topology is tested for different load variations, supply voltage variations and load frequency variations and it is suitable for all type of loads. And with different load variations, the voltage ripples of the capacitor are within the allowable limits. The topology is analyzed with LSPWM technique for changes in amplitude modulation, frequency modulation, and corresponding THD and fundamental component variations are observed. The efficiency is analyzed for the variations in load. The effectiveness of the proposed topology is verified by various simulation and experimental results. SWAMY JAKKULA received the B.Tech. degree in electrical and electronics engineering from Jawaharlal Nehru Technological University Hyderabad, Hyderabad, India, in 2019. He is currently pursuing the M.Tech. degree in power electronics and drives with the National Institute of Technology Andhra Pradesh, India. His research interests include power electronics, switched capacitor multilevel inverter topologies, fault tolerant MLI, pulse width modulation techniques, grid integration of renewable energy systems, and AC motor drives and control.
NAKKA JAYARAM received the B.Tech. degree in electrical and electronics engineering from Jawaharlal Nehru Technological University Hyderabad, Hyderabad, India, in 2007, the M.Tech. degree from the Vellore Institute of Technology, Vellore, India, in 2009, and the Ph.D. degree in electrical engineering from the Indian Institute of Technology Roorkee, Roorkee, India, in 2014. Currently, he is with the Department of Electrical Engineering, National Institute of Technology Andhra Pradesh, India. He has published many international and national journals and conferences. His research interests include multilevel inverters, high power converters, and renewable energy systems. He is the reviewer of many international journals. He is currently pursuing the Ph.D. degree with the National Institute of Technology (NIT) Andhra Pradesh, Andhra Pradesh, India. His research interests include multi-level inverters, high power factor converters, and power electronics. VOLUME 10, 2022