Input Current Ripple Reduction in a Step-Up DC–DC Switched-Capacitor Switched-Inductor Converter

This paper presents research results related to the concept of a high-voltage-gain DC-DC converter with a low input current ripple. In the proposed topology, a low-volume DC-DC switch-mode boost converter operates in parallel with a switched-capacitor voltage multiplier (SCVM). The overall converter achieves a four-fold voltage gain, but the voltage stress of the transistor and the diode of the boost converter is only half of the output voltage. This is achieved by applying the specific topology of the proposed converter. Furthermore, the boost part uses a low-volume choke as it operates in the discontinuous conduction mode (DCM). The parallel operation of the boost converter and the SCVM decreases the current stress in some components of the multiplier. This paper presents a concept of the hybrid converter, an analytical model for the selection of components and switching parameters, an efficiency model, and the verification of the converter operation through simulation tests and experiments.


I. INTRODUCTION
DC-DC conversion based on switched-capacitor (SC) circuits allows a high-voltage-gain converter [1] to be achieved that can be optimized for low volume or high efficiency. One of the major problems of the switched-capacitor (SC) DC-DC converters is their pulsating input current. The input current ripple is associated with the method of operation of the SC circuits that is based on the charging and discharging of the switched capacitors in various configurations. This is clearly seen in SC voltage multipliers [2]- [4], such as a classic multiplier discussed in [2], or the converter presented in [3], where the input current can be approximated by a rectified sinusoidal shape. In other types of SC series-parallel converters, like those presented in [4], the input current is even deteriorated by zero-current periods that occur between the sequences of pulses, or an inequality of pulses occurs [5].
A low-ripple input current is especially important in some applications. In photovoltaic systems (PV), the input current ripple may affect the Maximum Power Point (MPP) operation quality. In [6]- [11], high-voltage-gain converters with SC circuits are proposed for renewable energy systems, where the problem of input current ripple is overcome by the topology The associate editor coordinating the review of this manuscript and approving it for publication was N. Prabaharan . and control concept. In [6], high voltage gain is generated by voltage multipliers which extend the boost converters, and low voltage ripple level is ensured by the interleaved operation of the units. The single unit is composed of a boost converter and a multiplier in series connection. Publication [7] presents a solution of a high-voltage-gain converter, where the topology of the converter allows to achieve continuous input current and utilizes two inductors of 1.96 mH and 1.35 mH. The interleaved technique used in the DC-DC converter concept for renewable energy systems is presented in [8]- [10]. The mentioned topologies combine SC circuits and switch-mode operation with the use of inductors and can be optimized toward a low number of switches. In [11], a charge pump and coupled inductors are used for high stepup DC-DC conversion in a photovoltaic AC module with voltage gain in the range of 2.9 to 10. The converter has low volume and is built using a transformer with magnetizing inductance of about 24 µH, one transistor, and three diodes. However, the input current ripple is not reduced as much as in the converter proposed in this paper. The application of high-voltage-gain converters with SC and switched-inductor (SI) circuits is also proposed for fuel cell applications in vehicles [12], [13].
The concept of interleaved technique is a common method that allows for a decrease in the input current ripple of a converter. It is demonstrated in [8]- [10] for renewable energy applications, but also in articles [14]- [20], which present high-voltage-gain converters with SC circuits. The converters proposed in [14]- [17] are built as a hybrid switchedcapacitor/switched-inductor (SC/SI) structure with inductors on the input side. This allows for a decrease in the input current ripple by the utilization of the proposed topology and control concept, as well as the use of the SC structure for adequate voltage gain achievement. In [14], cancelation of the input current ripple is demonstrated, and the experiments were carried out with inductors of 140 µH and 330 µH. In references [18]- [23], an interleaved operation of pure SC converters is presented. In [18] and [19] the charging and discharging states of the switched capacitors in parallel connected units, as well as the connection to the load, are phase shifted. From the input current quality viewpoint, this gives a substantial reduction in the ripples. The high-gain converter with improved efficiency presented in [20] uses distributed stray inductances and operates in an interleaved SC structure with a common input and output capacitor, resulting in a reduction in current ripple. In [21], a step-up converter based on the interleaved operation of the SC and the boost parts is presented. It ensures a reduction in the ripple of the input current. Furthermore, on the output side each part charges one of two series capacitors which gives the output voltage control by the boost converter. The resonant SC converter presented in [22] can also operate in an interleaved mode. The benefit of the input current ripple reduction was explained in the case of the voltage multiplier, which uses very small resonant inductors. In [23], a converter with series output capacitors charged in an interleaved mode by SC circuits is demonstrated. The application of very small inductances allows one to operate with oscillatory currents in front of each SC unit. An adequate phase shift of the currents gives a significant ripple reduction in the input current of the converter. The hybrid converter proposed in this paper exhibits a lower number of switches compared to concepts presented in [20]- [23], which is presented in more detail further in this article. In [24], some topologies of automatic interleaved Dickson switchedcapacitor converters are presented. The converter uses two transistors and circuits composed of diodes and capacitors, as well as a low-volume inductor in the resonant topology. In the demonstrated case of the converter with triple voltage gain, the input current ripple achieved is below 10%.
Another concept for input current ripple cancelation in a high-gain DC-DC converter with an SC structure is presented in [25]. The converter uses an input choke and auxiliary L and C components in a circuit that absorbs the AC component of the current. The application of DC-DC switch-mode circuits integrated with the SC structure allows design of a highvoltage-gain converter with regulation possibility, as shown in [26], where various types of converters with an inductive storage cell are presented. In a converter with an input DC-DC boost part, the input current ripple can be decreased compared to those of a classic boost converter or a pure SC converter. The conduction losses and voltage stress across the components of the boost converter are also reduced. Various examples of hybrid converters that integrate SC and switchmode circuits are presented in [26]- [32]. Further positive qualities such as low component count, high voltage gain, and output voltage regulation ability can be found in these concepts. In some cases, the input current ripple is significantly reduced, which is demonstrated in a converter equipped with an inductor of 220 µH [26], and in that with inductors of 1.1 mH and 0.55 mH [30].
The hybrid converter presented in this paper allows a significant reduction in the input current ripple by an active switch-inductor (SI) part operating in parallel to a specific SC converter. It utilizes an additional switched-inductor circuit with a very low inductance compared to those used in the majority of hybrid SC/SI converters presented in the literature. This is one of the very positive characteristics of the converter presented. Furthermore, the operation of the SI converter decreases current stress in some SC circuits, allowing for a decrease in its losses and volume. The next advantage is seen in the size of the components for the SI converter. It operates in the boost topology and converts the energy from the input capacitor to an internal capacitor in the SC converter where the voltage is equal to half of the output voltage. This is possible thanks to the application of the innovative SC topology [3], which finally allows the design of an SI converter for low voltage stresses of their devices. The SI part used in the proposed hybrid converter requires a very low choke inductance, as the boost converter operates in the DCM mode with a voltage gain of less than two. This is an advantage compared to the majority of switch-mode or hybrid converters that use chokes of substantial volume.
In the proposed parallel configuration, the output capacitor of the switch-mode converter is charged by the SC circuit as well. Since the switch-mode converter operates with a low duty cycle, it does not regulate the output voltage, and the whole converter operates as a voltage multiplier with a constant four-fold voltage gain.
The major contribution of the paper lies in the analytical determination of the parameter components, switching strategy, power sharing between the SC and boost (SI) parts of the converter, and an analytical model of efficiency, as well as in computer simulations and experimental verification of the converter operation and its efficiency. Together with the previously published conference paper [34], this work introduces a novel topology of the high-gain DC-DC stepup converter with reduced input current ripple achieved by a parallel operation of an SCVM converter and a switchinductor circuit equipped with a low-volume inductor.
The proposed hybrid converter maintains the favorable qualities of SC converters [1]- [5], such as high voltage gain, simple control, high efficiency, high power density, and minimization of the values of the magnetic components, which can lead to the elimination of ferrite cores from the design.
The input current ripple can be filtered by passive input circuits. This typical approach requires the use of LC components of adequate volume. However, these circuits can affect the transient response of the converter and should be designed with consideration of the dynamic behavior of the closedloop control system. This paper is organized as follows. Section 2 introduces the concept of the proposed converter, and its subsections contain analytical models useful for the selection of the converter components. Section 3 presents the results of the computer simulation and the determination of the current stresses of the SC converter components that are useful for the efficiency model demonstrated in Section 4. The operation of the converter and the efficiency model have been confirmed by experiments, whose results are presented in Section 5. All results obtained here lead to the positive conclusions described in the last section of this paper.

II. CONCEPT OF THE HYBRID CONVERTER
The concept of the proposed hybrid converter is presented in Fig. 1 in [34]. The converter is composed of a specific switched-capacitor voltage multiplier (SCVM) [3] and a switch-mode boost converter that directs its inductor current to an internal capacitor of the SCVM. The input current of the SCVM converter is composed of pulses, as in the classic converter presented in [33]. Therefore, the current of the parallel switch-mode boost converter should fill the gaps between the pulses. The appropriate mode of operation is the DCM, where the current of the boost converter is composed of triangle pulses with a phase shift in relation to the SCVM current. The shift time is adjusted to ensure that the boost converter pulse is exactly in place of the gap in the SCVM current.

A. VOLTAGE GAIN
The concept of the proposed converter assumes that the operation of the SC multiplier determines the total voltage gain, and the switch-mode converter allows for cancelation of input current ripple and reduction in current stress of the components of the SCVM.
The SCVM operates in a two-stage mode presented in Fig. 2. In the first stage, the capacitor C 1 is being charged from the source, and the capacitor C 3 is being charged from C 2 . The voltage across capacitor C 2 is determined by the configuration in the second stage of operation where capacitor C 2 is being charged from C 1 and the source connected in series. The average voltage on capacitor C 1 is equal to U in and that on capacitors C 2 and C 3 is 2U in . Such an operation ensures that the output voltage is maintained at a constant level equal to about 4U in and the voltage on the internal capacitor C 2 at a level equal to about 2U in . Therefore, the boost circuit, composed of elements S b , D b , and L b , operating in the DCM mode with the duty ratio D < 0.5, charges the capacitor C 2 , but does not significantly affect the converter voltage gain, which is equal to G U ≈ 4.

B. THE INPUT CURRENT RIPPLE REDUCTION
The SC and SI subcircuits can be controlled independently. The main positive characteristic of the proposed hybrid converter is the ability to reduce the input current ripple. To achieve the appropriate phase shift between both components of the input current, the control of both subcircuits should be adequately synchronized. From Fig. 4, it is seen that the pure SC converter [3] operates with pulses of its input current. It can be filtered by passive circuits on the input, but in connection with the SI circuit, the problem of the input current ripple is significantly decreased (current i in ). Figure 4 presents the operation concept of this converter, which is based on adequate switching of the SI circuits with respect to the SC part. The input current of the boost converter (i inb ) reaches its maximum at the time when the SCVM current (i ins ) reaches zero. It is not required to add any current to the SCVM current (i ins ) at the time when it reaches its maximum; therefore, the boost converter operates in the deep DCM mode using a low-volume choke.
It is also important that the operation of the SI part allows a decrease in the energy converted by the SCVM and the current stresses of components S 1 , S 2 , D 1 , D 2 , L 1 , and C 1 .

C. SELECTION OF PARAMETERS OF THE SCVM PART
The LC parameters of the SCVM converter are determined by the output power, the switching frequency, and the requirements for the resonant choke design. The energy is transferred by the switched capacitors, but the resonant inductor is required to avoid inrush currents in the SC circuits. It is justified to use a stray inductance or an air-based choke for this purpose. The aforementioned energy can determine the resonant inductance L i (i = 1 − 3). The design of the LC circuits in the SCVM can be achieved in the steps presented in Table 1. The issues of selecting LC components in SCVM converters are analyzed in [2] and [33].
After selecting L i and f S , the capacitance C i (i = 1 − 3) is adjusted to achieve the resonant frequency close to the switching frequency. The presence of dead time increases conduction losses in the SCVM converters and should be minimized. The selected capacitance C i can be oversized from a converter power viewpoint. Under such conditions, the capacitor C i is not fully discharged in a switching cycle, but operates with a voltage ripple. The power limit of the SCVM depends on the parameter C i f S , which is presented in [33].

D. SELECTION OF PARAMETERS OF THE BOOST PART
The model of the desired waveforms in the hybrid SCVM/boost converter with reduced ripples of the input current is presented in Fig. 5.
The combination of the final waveforms should comply with the following assumptions: -Both input currents reach the same maximum value I m -time points t 2 and t 6 , -The crossing of the waveforms occurs when both currents reach the value I m /2 -the time point t 4 . This means that the sum of the waveforms (i in ) reaches the value I m at the time point t 4 .
-The input current of the boost converter reaches its maximum value just in the middle of the dead time (time point t 6 = t 5 + T dt /2. In the particular case: T dt = 0 and then t 6 = t 5 = t 7 ). VOLUME 10, 2022 -The current of the boost converter has an ideal linear waveform and the SCVM current is purely sinusoidal.
Starting from the time point t 2 (Fig. 5), the SCVM current is described by the function: where ω 0 is the resonant pulsation in the SCVM circuits, ω 0 = 2πf 0 = 2π/T 0 , and T 0 + 2T dt = T S . Starting from the time point t 4 , the boost current has the following derivative: At time t 4 , i inS = I m /2 and during the time interval (t 5t 4 ), equal to 1/6 of the half-period T 0 /2, the SCVM current falls to zero. Therefore: The relationship which connects the inductance of the boost converter and the parameters of the SCVM as well as the input voltage, load, and the used dead time is the following: To achieve the filtering effect, the SCVM and boost converter switching signals should have an adequate phase shift. Assuming that the phase shift of a pulse of the SCVM current is zero, the phase shift of the boost converter is determined by the time point t 3 (Fig. 5). Using the symmetry of the i Lb waveform around the time point t 4 , the following relationship is true: The point t 4 has position 5/6·T 0 /2 (5/6π ) and the boost converter control time shift is the following: The duty cycle of the boost converter is as follows: Assuming that the dead time is negligible (T dt ≈ 0), the boost duty cycle approaches the value: Relationship (8) confirms that the boost converter can operate with the proposed SCVM. The boost should charge the internal capacitor C 2 where the voltage is maintained by the SCVM converter at the level of 2U in . Therefore, the boost converter, as a current-source-type converter, can charge the capacitor C 2 operated with duty cycle D = 0.33.
In the next step of the design of the hybrid converter parameters, the maximum current I m (Fig. 5) should be calculated. In a single SCVM converter, it depends directly on the load (under the fixed parameters of the resonant circuits). In a hybrid converter, the switch-mode boost converter transfers some of the energy, causing the SCVM input current to decrease. In the DCM mode, the average input current of the boost converter can be calculated from a triangle function in the time period T S /2 The power of the boost part of the converter is then the following: Similarly, the power of the SCVM part can be expressed as Assuming a very short value of the dead time T dt ≈ 0, T S tends to T 0 and the power of the boost converter is expressed by the simplified formula: For T dt ≈ 0, the input current of the SCVM converter is composed of the pulses described as: The average value of this current is the following: The power of the SCVM part of the converter can be expressed by The ratio of power converted by the SCVM to that of the switch-mode part of the converter is equal to From (16), it is seen that the boost converter transfers approximately 34% of the power of the hybrid system (Fig. 1). Thus, it reduces the power of the SCVM converter and the current stresses of its components. The power of the SCVM and the switch-mode part of the converter is   (4), it is seen that the boost inductance (L b ) is a function of the input voltage, the resonant frequency of the SCVM circuits and the dead-time. The inductance L b can be minimized by a decrease in the deadtime and an increase in the resonant frequency f 0 . This allows to minimize the LC parameters in the SCVM part as well. Fig. 6 presents graphs that show in figures the example relationships between the required boost inductance L b (4) and the dead time, the resonant inductance of the SCVM converter, power, and the SCVM resonant frequency. From these results, it is seen that both inductances (in the boost and SCVM converter) can be minimized simultaneously. The limit of the minimization of the inductances is determined by the maximum value of the currents and switching losses (as the switching frequency increases when smaller inductances are applied in the converters). Another very important conclusion concerns the relationship between the inductance L b and the output power. It is very interesting that for higher power, a lower value of inductance is required in the boost part of the hybrid converter.

III. SIMULATION RESULTS
Some simulations were performed to verify the operation of the converter and the analytical findings, as well as to measure the current and voltage values. The parameters of the VOLUME 10, 2022  simulation model are presented in Table 3. During the tests, the inductance of the boost converter remained constant. Figure 7 presents steady-state waveforms of the input currents in the converter. According to the assumed operating model, the total input current (i in ) is significantly improved by cancelation of its pulses.
In Figure 8, the waveforms of currents in particular branches of the converter are demonstrated. The current load is important for the selection of components and the estimation of conduction losses. The current stress of switches and diodes is limited as they conduct current only in every second pulse of operation.
The voltages across capacitors of the converter can be seen in Fig. 9. The four-fold total voltage gain is confirmed, as well as the voltage levels on the capacitors C 2 and C 3 , which are twice the input voltage.
In the proposed converter, the voltage stress of the switches (Fig. 10) is limited to the input voltage level U in (transistors S 1 and S 2 ) and to the doubled input voltage 2U in (transistors S 3 and S 4 ). This is very favourable, as the output voltage is 4U in . The voltage stress of the diodes is limited to U in and 2U in as well, as seen in the simulation results presented in Fig. 11.
When the output power varies, the reasonable operation method for the converter is to maintain both maximum currents at the same level: Under condition (18) and fixed L b , the proportion of powers is a function of the output power: P = P SCVM P b = f (P out ).     input currents and power. Based on the simulation results (Fig. 12), the proportion of power P can be expressed as the following function of the output power: For the sake of further analysis, the SCVM part of the hybrid converter has been divided into two parts: SCVM A and SCVM B . The first part, SCVM A , consists of components S 1 , S 2 , L 1 , C 1 , D 1 , and D 2 . The second part, SCVM B , contains the following elements of the SCVM (S 3 , S 4 , L 3 , C 3 , D 3 , and D out ).
The output voltage regulation in a conventional way is not applicable when the control duty cycle of the SI boost converter is below 50%. The boost converter operates in parallel with the SCVM A that has a constant two-fold voltage gain. Operating with D < 50%, the SI circuit charges the capacitor C 2 . This decreases the power of the SCVM A , but does not affect the overall voltage gain.
For D > 50%, the SI boost converter allows controlling the voltage across capacitor C 2 in the range u C2 > 2U in . In such a case, the SCVM A part of the converter cannot charge the capacitor C 2 (SCVM A has a twofold voltage gain and stops operating when u C2 > 2U in ). Therefore, the boost converter converts 100% of the power and the input current ripple reduction is deteriorated. Such an operation can be useful in some special cases of fault-tolerant operation. However, these are not rated conditions for the proposed converter and can require a different design approach than in the case of interleaved operation of the SC and SI input parts of the converter. Fig. 13 shows a comparison of the converter operation in cases where the boost converter operates below and above the duty cycle D = 50%. The inductance of the boost choke is selected to meet the conditions i inb = i inS at D = 50%. Using this stage of operation, the voltage gain characteristic becomes the following:

IV. MODEL OF EFFICIENCY
The parallel operation of the SC network and the boost converter in the proposed hybrid system allows for a decrease in the conduction and switching losses in the SC circuits. Conduction losses decrease in SCVMs due to the decrease of energy transferred by SC circuits. Additional power losses arise in the boost converter. However, the boost converter operates under favorable conditions from a switching loss point of view: -The boost converter charges the internal capacitor C 2 whose voltage is two times lower than the output voltage of the proposed hybrid converter. This allows one to decrease the turn-off losses of the transistor S b ; -Q rr losses are eliminated as the boost operates in the DCM mode.
The conduction loss can also be limited by selecting transistor S b with a low R DS(on) value. A decrease in the voltage stress of the switch S b is a very positive characteristic of the proposed converter for the transistor with a low R DS(on) .
For calculating the conduction losses, the average and rms values of currents in the particular branches of the converter can be determined on the basis of the input current. A similar method was proposed in [4]. The maximum value of the input current pulses depends on the input voltage and power and can be easily determined by assuming a sinusoidal shape of the current. Fig. 8 presents simulation results of the currents in the converter with estimated values of the average and rms values of the currents in branches.
The proportion of the power of the SCVM A to that of the boost converter is fixed for an operating point determined by the design of the boost inductance and the phase shift of the converter control given in the analysis above. This proportion varies when the converter operates with a dead time and when the output power is changed (19), (Fig. 12). Therefore, in the efficiency model, the proportion p of the powers of both parts of the converter will be determined using the function (19) that corresponds to the demonstrated case of the design.
It is assumed that the currents of both the SCVM and the boost parts reach the same maximum value I m (Figs. 5 and 12). This current can be determined as a function of the input voltage, converter power, switching frequency, and dead time. In this section, the current I m is computed for a zero dead time.
The converter power P in is the sum of powers of both converter parts P in = P b + P SCVM (22) where P b and P SCVM are given by (10) and (11), respectively. From the topology of the hybrid converter, it is seen that the first part of the SCVM (SCVM A ) operates in parallel to the boost converter with the power (23) From (23), we obtain the following: The currents of the SCVM A are (Fig. 8) The second part of the SCVM (SCVM B ) operates with full power, and its input voltage U in_SCVMB is equal to 2U in : From (23), we obtain the following: (27) The currents of the SCVM B are (Fig. 8) (28) Both SCVM A and SCVM B parts are voltage doublers [2]. The efficiency of the MOSFET-based voltage doubler is determined by the resistances of its components, the voltage drops on the diodes, the input voltage, and the power of the doubler. The conduction losses P SIk in the circuit of charging of the cell capacitor and the losses P SIIk in the circuit of charging of the output capacitor are the following: in the SCVM A , and in the SCVM B , where I S1 -I S4 are the rms values of the transistor currents, r S1 -r S4 denote the total resistance, including that of the MOSFET, in the circuit of charging and discharging the switched capacitor, respectively. I D1av -I D3av and I Doutav are the average values of the diode currents, U D1 -U D3 and U Dout are the voltage drops across the diodes. It is assumed that the voltage drops across the diodes remain constant in their conducting state.
The conduction losses P C1 in both SCVM A and SCVM B converters are the sum of the aforementioned losses U Dk I Dk + U Dout I Dout (31) There are also conduction losses P C2 in inductance L 2 , which is not included in any of the aforementioned doublers. The current i L2 , shown in Fig. 8, is equal to -i S3 in stage I and to i S2i S4 in stage II. Therefore, its minimum in stage I is -I m2 (27), its maximum in stage II is I m -I m2 (24), (27), and its rms value is equal to The conduction losses P C2 are where r L2 is the resistance of the circuit with L 2 . There are also conduction losses P C3 in the boost part of the converter P C3 = r Sb I 2 Sb + U Db I Dbav (34) where I Sb is the rms value of the transistor S b current, and r Sb denotes the total resistance, including that of transistor S b , in the circuit with inductance L b . I Dbav is the average value of the diode D b current and U Db is the voltage drop across this diode. Both i Sb and i Db currents are linear (Fig. 5); thus, The turn-off switching loss of transistors S 1 -S 4 is zero, due to the ZCS switching. However, there is a turn-on switching loss, associated with charging and discharging the output capacitances of the MOSFETs. The latter also refers to the transistor S b . The total turn-on switching power loss P sw_on is where W sw_on is the energy lost at turn-ons in all MOSFETs' resistances in a single switching cycle. A way to calculate these losses is presented in [36]. The transistor S b is turned off at maximum current I m , which involves a turn-off switching loss P sw_off where W sw_off' is the energy lost at the turn-off of transistor S b in a single switching cycle. This loss can be calculated based on [36] and the results of the measurements. The overall loss is the sum of all the aforementioned losses P = P C1 + P C2 + P C3 + P sw_on + P sw_off (38) and the efficiency of the converter is given by The results of this analysis are used in Fig. 21 to compare the measured efficiency of the converter with the theoretical one. The tolerance of passive components or their parameter variation may lead to an operation with unequal time durations of current pulses. To maintain the ZCS conditions, the time between pulses (the dead-time determined by the time interval t 5 -t 7 in Fig. 5) should be designed to be long enough. However, a dead time that is too long is not favorable due to the deterioration of efficiency in the SCVM converter that was proven in [33]. On the other hand, the SC converter operation above the resonant frequency is not dangerous, but may lead to a decrease in the output voltage. Such cases of operation were analyzed in [2] for a voltage doubler. In the converter presented in this paper, the operation above the resonant frequency is also allowed because the current of any inductor can flow through the diodes when the transistors are turned off.

V. EXPERIMENTAL VERIFICATION
This chapter presents the results of the hybrid converter measurements performed on the experimental setup. During the experiment, the operation of the converter and the higher harmonic content in its input current were verified. Moreover, the efficiency characteristic of the proposed converter was compared with that of the pure SCVM converter and with a theoretical one.

A. EXPERIMENTAL SETUP
All the parameters of the components used in the experimental setup, as well as other relevant experimental conditions, are collected in Table 4. The laboratory setup is presented in Fig. 14 where the SCVM part is visible on the top of the stack and the switch-mode section is placed on the bottom. The test results were obtained with the use of discrete chokes in the SCVM, but the setup allows for an operation at higher frequencies with air-based resonant chokes. Figure 14 presents the oscillogram of the input currents and the output voltage in the proposed converter. These are the essential results that confirm the operation of the proposed concept and the cancelation of the input current ripple. In the waveforms presented, the pulsating SCVM input current (i inS ) and the phase-shifted input current of the boost converter (i inb ) are seen. The combination of these two DC-DC  converters, as shown in Fig. 1, allows reducing the overall pulsation of the input current (i in ) of the SCVM converter.

B. EXPERIMENTAL RESULTS
The proposed modification does not have any negative impact on the voltage gain of the converter, which is proven by the converter output voltage recording (u out ). During the experiment, the proposed converter was operating at the output power of 585 W while powered up from a 100 V DC source. Under such conditions, the converter achieves a four-fold voltage gain, which is in line with the theoretical considerations and the results of the simulation research.
The waveforms visible in Fig. 15 were also recorded as a text file. This was done in order to perform the fast Fourier transform (FFT) analysis on it and investigate the exact amount of higher harmonic content in the currents i inS and i inb . The spectral analysis calculations have been carried out with the usage of MATLAB software and the results are shown in Fig. 16. From the obtained graphs, it follows that the input current of the hybrid converter contains much fewer higher harmonics than the input current of the pure SCVM converter. Figure 17 presents the waveforms of the basic converter currents and voltages across the resonant capacitors C 1 and C 2 . To obtain a full view of the recharging processes that take place in the proposed converter, an analysis of the voltage across capacitor C 3 (Fig. 18) is needed. All voltage waveforms shown in Figs. 17 and 18 present voltages recorded in the AC mode to expose the charging and discharging processes that take place in resonant capacitors and are crucial for the analysis of the operating principle.
The waveforms presented in Figs. 17 and 18 show that the resonant capacitors C 1 and C 3 are being charged and discharged at the same time. Furthermore, the charging of capacitor C 2 starts when capacitors C 1 and C 3 start to discharge, which is exactly in line with the previously assumed operating principle of the converter.
The proposed converter allows for reducing the drawbacks of the classic SCVM converter and maintaining all its positive characteristics. This is visible in Fig. 19, where the voltage stresses of the transistors operating in the converter output stage are shown. In this part of the proposed circuit, the expected voltage stresses are the highest, like in a classic SCVM converter. From the properties of the SCVM topology, it follows that the voltage stresses across the switches in this part of the converter are equal to only half of the classic SCVM converter output voltage. This benefit is very valuable from the perspective of the selection of semiconductor elements and is also present in the proposed hybrid converter.
Other experimental tests were associated with the efficiency of the hybrid and pure SC converters. The results presented in Fig. 20 show that the peak efficiency of the hybrid converter is about one percentage point above that of   the pure SCVM. Additionally, the efficiency characteristic of the hybrid converter seems to be stable, while that of the classic SCVM starts to decrease for higher loads. This proves that the proposed converter might be a better solution for use in higher power applications.   (19). Figure 21 shows a comparison between the measured efficiency of the hybrid converter (Fig. 20) and the theoretical efficiency given by (39). There is a good convergence between both characteristics.

VI. CONCLUSION
In this paper, a novel concept and results of investigations of a parallel converter composed of switched-capacitor (SC) circuits and a switch-mode converter are presented. The proposed hybrid converter demonstrates the following several advantages compared to a pure SC converter: -The input current ripple is reduced significantly; -The application of the switch-mode part connected in parallel to the SC converter reduces the current burden of the SC converter, and the total cost of the converter may not rise when the hybrid concept is introduced; -The efficiency of the hybrid converter is higher than that of the classical SCVM for higher values of power; thus, the proposed converter might be a better solution for use in higher power applications; -The switch-mode converter, built in the boost topology, operates in the deep DCM mode with a low duty cycle. Therefore, its choke has a small inductance and volume; -The boost converter operates with a low output voltage (two times lower than the output voltage), which allows the use of high-quality semiconductor switches of low cost; -Very favorable design relationships show that the inductance of the boost converter should be decreased as the power of the converter increases. Similarly, when the resonant inductance of the SCVM part is designed smaller, the boost inductance is also decreased. This makes it possible to minimize the volume of the entire hybrid converter; -As the input current ripple is significantly reduced, the proposed converter could be attractive for application in photovoltaic systems. In a DC-AC PV system, the proposed DC-DC converter allows to increase the voltage of the PV arrays to a range of the rated DC-link voltage of the inverter. Since the DC-DC multiplier does not regulate power, the MPPT algorithm should be implemented for inverter control. A similar approach is used in PV systems that operate without DC-DC converters. Reference [35] shows a concept of the MPPT method for a single-stage grid-connected PV system with a single-phase inverter. The presence of a multiplier in the conversion system may, of course, affect its dynamic behavior; -The major qualities of the proposed converter are compared with the state-of-the-art and are demonstrated in Table 5. The selected cases for comparison contain SC converters operating in the interleaved configuration [18]- [24]. As the proposed converter uses low-volume chokes in both SC and switch-mode parts, a detailed comparison with interleaved SC converters is valuable; -When optimization towards the number of components utilization is critical, the proposed converter can be selected among the concepts compared in Table 5. Pure SC converters, such as the solution presented in [20], use a large number of switches, but allow the ripple of the input current to be reduced without the use of discrete inductors and with lower voltage stress of the switches. The converter presented in [24] uses a very low number of transistors, but the converter proposed in this paper exhibits a favorable low number of diodes and capacitors; -The other class of hybrid converters utilizes switch-mode converters with larger inductors, which allows for lowripple input current and regulation capability. Reference converters from that area of concepts are described in Introduction with example values of the used inductances.