Dual-Band Direct Conversion Receiver With Additive Mixing Architecture

A dual-band direct conversion receiver based on additive mixing architecture for low-cost and multi-mode wireless communication systems is proposed. The proposed receiver consists of two active four-port junctions for additive mixing and one-stage dual-band polyphase filter for quadrature LO signal generation. Each four-port junction is fabricated with $0.18~\mu \text{m}$ CMOS technology and configured by an active balun, two buffer amplifiers, two active combiners and two power detectors. The proposed polyphase filter is implemented using type-I architecture adopting one-stage and R-LC resonance type for low power and dual-band operation. The phase and amplitude calibration schemes are also integrated to effectively correct I/Q mismatch within the proposed architecture. The calibration ranges for the phase and amplitude mismatches show 8° and 14 dB, respectively. The validity of the proposed receiver based on additive mixing method is successfully demonstrated by demodulating 16-QAM signals with 40 Mbps at the dual band of 900 MHz and 2.4 GHz.


I. INTRODUCTION
Modern wireless communication systems typically use direct conversion receivers (DCR) for high-speed multi-band or multi-mode applications to effectively demodulate various modulated signals like M-ary quadrature amplitude modulation (M-QAM). Among various approaches to design DCRs, the multi-port technology generally known as six-port or fiveport networks is considered as one of the efficient solutions for reconfigurable RF transceiver [1]. Since the six-port networks were first proposed as a low-cost alternative to vector network analyzers [2], [3], active researches have been also conducted to extend the use of six-port based circuits. Some DCRs based on the six-port techniques were also proposed for software defined radio (SDR) front-ends [4]- [6]. Other six-port applications can be also found in calibration circuitry and discriminator [7], [8]. This broad scope of applications is possible because the advantages of additive mixing by The associate editor coordinating the review of this manuscript and approving it for publication was John Xun Yang . the six-port over conventional multiplicative topologies are compactness and low power consumption. Fig. 1 (a) shows the conventional block diagram of six-port DCR. The sixport junction in DCR adds a RF signal with LO signals shifted by 0 • , 90 • , 180 • and 270 • . The six-port network has been typically implemented by microwave passive circuits such as hybrid coupler or Wilkinson power divider as shown in Fig. 1 (b). The hybrid coupler with standard varactor diodes has been also conventionally used to implement dualband or multi-band operations [9]. Another typically used technique in the six-port is to utilize the wideband power dividers or combiners and the polyphase LO network [10] as shown in Fig. 1 (c). However, the integrated circuit (IC) fabrication for the passive circuit based six-port is limited due to the required size for quarter wavelength transmission lines. To overcome the drawback of the passive six-port architecture, a CMOS four-port DCR with BPSK demodulation has been proposed as shown in Fig. 2 (a) [11]. Here, the conventional passive couplers and dividers were replaced by a wideband active divider, combiner and an FIGURE 1. Simplified diagrams of six-port based receiver with (a) overall DCR architecture (b) six-port junction implemented by hybrid couplers and Wilkinson power divider, and (c) six-port junction implemented by power dividers, combiners and polyphase network. active balun. The BPSK demodulator based on the fourport junction first divides the RF signal and then adds the divided RF signals with the coherent I/Q LO signals. Next, the mixed signals go through the envelope detectors to determine a received phase during a symbol period. Fig. 2(b) shows the example waveforms at each node denoted in Fig. 2(a) to describe the signal chain. Although the previously reported active four-port junction has shown the compactness compared to the conventional passive network, the operation flexibility like multi-band operation has not been demonstrated yet. Thus, in this paper, a new six-port DCR architecture with a dual-band operation is proposed to further extend the effective use of the active six-port technique. To achieve the dual-band performance with low circuit complexity, low power and compact size, a dual-band polyphase filter (PPF) and I/Q mismatch calibration scheme are adopted in the proposed architecture.

II. DESIGN AND ANAYSIS OF THE PROPOSED DUAL-BAND SIX-PORT DCR
The fundamental operation of the active six-port receiver is based on the additive mixing among RF signals and quadrature LO signals through active RF dividers and combiners. Although there are several methods to generate the quadrature signals, PPF can be effectively integrated due to its compact size and ease of design. Also, baluns can be used with a single-stage PPF to generate 0 • , 90 • , 180 • and 270 • phases instead of multi-stage PPF. Baluns are often realized in off-chip because on-chip balun at microwave frequencies occupies a large area. Thus, to effectively integrate the balun with small area occupancy in IC, the balun in the proposed architecture is designed by active CMOS transistors. Further, since the single-stage PPF cannot generate the dual-band operation, a dual-band PPF based on the combination of band-pass and band-stop configurations is also proposed in this paper.

A. DUAL-BAND POLYPHASE FILTER
Among various methods to generate the quadrature signals, the RC-CR network is considered as the simplest structure. The phase shifts of ±45 • by high-pass network and low-pass network generate the quadrature signals at a single frequency. A cascade multi-stage architecture can be generally used to extend the operation bandwidth of the PPF. However, the increase in both circuit size and chip area, and power loss of the LO signal become the main drawbacks of the multi-stage PPF [12]. To generate dual-band or multi-band quadrature signals, tunable LC network [13], dual-band bandpass filter (BPF) or tunable varactor [14] have been reported as well. Also, the combination of PPF and quarterwavelength coupled line coupler (CLC) has been recently suggested for wideband quadrature signal generation [15]. However, these structures require additional control voltages or increase the circuit size making it unsuitable for sub-6GHz IC fabrication. Instead of adopting tunable configuration to achieve dual or multi band operations, a fixed dual-band structure with a low-complexity is focused in this paper.
To solve the problems of the conventional RC-CR network, the modified PPF circuit for the dual-band operation is proposed as shown in Fig. 3 (a). Here, the series resonance by LC is adopted in both paths instead of a single C in the conventional PPF network. The relative phases in two paths are conceptually presented Fig. 3 (b). The phases generated by the band-pass CL-R filter in one path and the band-stop R-CL filter in the other path result in ±90 • phase difference between the two paths: +90 • in the low-band and −90 • in the high-band. The transfer functions in band-pass and band-stop paths are given by equations (1) and (2), respectively.
where ω 0 = 1 √ LC and Q = ω 0 L R . From the above equations, the half power frequencies corresponding to the desired dual-band frequencies can be found by Based on the equations (1)-(4), the required inductor and capacitor values can be easily determined. It is noted that the proposed PPF has the phase reversal characteristic between the low and high bands. Then, to convert the unbalanced dual-band PPF outputs to balanced signals, active baluns are used as shown in Fig. 4. The proposed dual-band quadrature LO generation circuitry is configured by the dual-band PPF and two active baluns. Further, the proposed technique is compared with the other quadrature signal generation methods as shown in Table 1.   by active balun, buffer amplifier, active combiner and power detectors. The active balun is based on a common-source and a common-gate amplifiers with M1 and M2 transistors. The simulated output gain and phase imbalances at the target frequencies are less than 2.1 dB and 5 • , respectively. Next, the active combiner that additively mixes RF and LO signals is designed with a differential pair of M3 and M4. The simulated output flatness within the target bands is less than 1.6 dB. Further, the potential LO leakages denoted as L due to the mismatch of power detectors or imbalance in LO signals are cancelled at the RF junction because of the differential structure. Thus, high isolation between LO and RF can be structurally obtained. Then, the power detector is designed by rectifying the output of the single-ended class-AB amplifier with M5. The transistor M6 is used for biasing the power detector and calibrating the amplitude mismatch between the I and Q networks. Also, the buffer amplifier is added in between the active balun and combiner to reject a common-mode signal from the active balun and also to calibrate the phase mismatch between the I and Q networks.
The calibration scheme will be specifically discussed later in this section. Then, the power detector outputs are connected with the low pass filters externally as well as the analog decoders to retrieve I and Q signals. The operation principles can be easily explained with a QPSK-modulated RF carrier and a LO signal. Let the RF and LO signals be defined as For simplicity, the LO signal is assumed to be synchronized with the RF carrier to make ω RF = ω LO , and ϕ LO = 0. Here, the quadrature LO signals through the PPF and the active baluns can be found by where θ and ε denote phase and amplitude errors with respect to the PPF. Also, i equals to 1, 2, 3 and 4 corresponding to the LO phases of 0, 90 • , 180 • and 270 • , respectively. DC output voltage of an ideal power detector is proportional to the square of the magnitude of the RF input signal. Assuming four identical detectors and LPF, the DC output voltages can be expressed as follows.
Here, LPF[·] represents the low-pass filtering of the parameters in square braces. Subtracting the outputs of the power detectors, P 1 -P 2 and P 3 -P 4 , gives I and Q signals as follows.
It is noted that the above equations include phase and amplitude errors due to the parasitic effect of the PPF. Thus, to reduce the resulted I/Q mismatch, additional calibration scheme in the LO signal path before the active combiner and power detectors is applied in the proposed receiver. Referring to Fig. 5, the phase tuning can be performed by adjusting two DC control voltages, Vcont-I-phase and Vcont-Q-phase. The bias current change of the buffer amplifier by tuning these DC VOLUME 10, 2022 voltages yields the variation in the gate-source capacitance of the amplifier. Consequently, phase delay in the buffer amplifier is achieved with respect to the control voltage. Fig. 6 (a) shows the simulated phase variation according to the phase tuning voltage in I-signal. The simulated phase calibration range is 8 • for the phase tuning voltage between 1.2 V and 1.4 V. For the maximum phase tuning of 8 • , the maximum amplitude error up to 6.5 dB is observed. This unintended amplitude variation caused by the phase tuning can be also calibrated by the gain control voltages denoted as Vcont-I-amp and Vcont-Q-amp in Fig. 5. The proposed receiver has the amplitude calibration range of 14 dB with respect to the amplitude tuning voltage of 0.35 V to 0.4 V as shown in Fig. 6 (b). Thus, the amplitude calibration range is sufficient to compensate the amplitude error generated during the phase calibration process.

III. FABRICATION AND MEASUREMENT
As described in Fig. 5, the proposed six-port architecture is configured by two active four-port ICs and a single dual-band PPF network. The designed four-port receiver was fabricated with 0.18 um CMOS process as shown in Fig. 7 (a). The fabricated chip size was 0.7 mm × 0.72 mm, including the active combiner, active balun, buffer amplifiers, two power detectors, and bonding pads. Further, the proposed dual-band PPF network was fabricated with a Teflon substrate having  a thickness of 0.5 mm and a relative permittivity of 2.6 as shown in Fig. 7 (b). The measured insertion loss and phase mismatch of the dual-band PPF network at the low-band frequency of 0.9 GHz were 8.4 dB and 2.1 • , respectively as shown in Fig. 7 (c). Also, the high-band performance at 2.4 GHz showed the measured insertion loss and phase mismatch of 7.2 dB and 1.2 • , respectively. Here, the slopes of the band-pass and band-stop magnitude responses at the upper and lower corner frequencies determine the bandwidths at the low-band and high-band. That is, higher Q factor generates steeper slopes at the corner frequencies, resulting in greater magnitude imbalances around the center frequencies.
Consequently, the usable bandwidths of the low-band and the high-band will decrease. On the contrary, lower Q factor results in a larger bandwidth at the sacrifice of insertion loss. Next, Fig. 8 (a) shows the measurement setup of the complete dual-band six-port DCR. The fabricated chip was implemented on a PCB with a supply voltage of 1.8 V. Then, two chips were connected with the dual-band PPF network to form the complete six-port architecture. The outputs of the six-port were connected to low-pass filters and baseband analog decoders. These analog decoders were implemented with AD8138 and AD8003 to take the difference between each I/Q output of the four-ports corresponding to LPF[V RF + V LO ] and LPF[V RF -V LO ]. Further, to verify the calibration scheme in the proposed six-port DCR, a bit error ratio (BER) measurement was also conducted as shown in Fig. 8 (a). The measured isolation between RF and LO ports were more than 50 dB from 1 GHz to 2.5 GHz as shown in Fig. 8 (b). Then, the modulated RF and the LO signals were generated by the E4438C vector signal generator and the synthesized sweeper HP-8341B, respectively. The QPSK modulator and LO generator shared the same reference clock by connecting both reference ports to synchronize the RF carrier and LO signals. The LO signal phase was fine-tuned using a manually tunable phase shifter for coherent demodulation. Further, a pseudo-random bit sequence with 2 21 -1 bits was generated by using the Anritsu MP1763C pattern generator to test BER. Fig. 9 (a) shows the measured BER with respect to the phase tuning voltage from 1.2 V to 1.6 V to verify the integrated calibration. The measurement was conducted with the input power to the RF and LO ports of -50 dBm and -20 dBm, respectively. According to Fig. 9 (a), the optimized BER value can be found at the tuning voltage of 1.4 V, implying the optimally calibrated phase between the RF and LO signals. The measured BER shows the improvement from 7 × 10 −5 to 2 × 10 −7 after the calibration. Further, the noise generator configured by a reverse-biased Zener diode and a two-stage wide-band amplifier was used to verify the BER performance under the noisy environment. The variation in E b /N o was realized by attenuating noise power from -89 dBm/Hz to -98 dBm/Hz. Fig. 9 (b) shows the theoretical and measured BER as a function of E b /N o . The measured BER less than 10 −6 was achieved with the E b /N o of 11 dB. Further, the power consumption of the proposed six-port DCR was about 28 mW with the supply voltage of 1.8 V. Table 2 shows the summarized measurement performance of the proposed sixport DCR with other architectures at similar operation band.
Here, the proposed DCR shows the low power consumption, low LO power and high RF-to-LO isolation performances compared with the other structures. Lastly,   Fig. 10 (a) and (b), respectively. Further, Fig. 10 (c) and (d) show the demodulated constellation and the demodulated output waveforms of the I and Q signals with 16-QAM, respectively. With the help of the integrated calibration, the constellation pattern was observed clearly as well as the I/Q waveforms.

IV. CONCLUSION
In this paper, a new dual-band six-port DCR with 0.9 GHz and 2.4 GHz operation bands has been proposed and verified. The proposed architecture was configured by a single-stage dual-band PPF, two CMOS four-port junctions and analog decoders. A manual I/Q phase and amplitude calibration scheme has been also adopted to balance the phase and amplitude mismatches generated in the demodulation process. The validity of the designed dual-band six-port receiver was successfully demonstrated by demodulating 16-QAM signals with 40 Mbps data rate. Therefore, the proposed six-port DCR has shown the advantages such as compactness, low complexity and relatively low power consumption.