A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

In this paper, a simple while effective methodology to calculate the symbolic transfer function of a multistage amplifier with frequency compensation is proposed. Three general amplifier models are introduced and analyzed, which represent basic topologies found in the literature. For these amplifier models, the symbolic transfer function is derived and specific strategies for the zero and non-dominant pole expressions are presented. The methodology is suited for hand calculations and yields accurate results while offering more intuition into the operation of the widely adopted frequency compensation solutions discussed in the literature. The effectiveness of the proposed approach is validated through various typical cases of study.


I. INTRODUCTION
A preliminary and fundamental task to the design of a multistage amplifier is the derivation of its symbolic transfer function. Indeed, knowledge of the voltage transfer function is required to gain more insight into the operation of a multistage amplifier and to set and design the amplifier compensation network, which is a fundamental design step where interactions between the power consumption, noise, area, bandwidth, and stability are involved. Moreover, starting from a generalized symbolic transfer function expression, a designer can readily study and compare the several design features of an amplifier compensated with different frequency compensation solutions.
Since the early years of MOS analog integrated circuits, the compensation of two or more stage amplifiers was a key research area [1]- [28]. In this field several novel solutions were continuously proposed, especially for three-and fourstage amplifiers, and, despite several decades have been devoted to this subject, even in the last ten years the interest on this topic appears active [29]- [40]. Indeed, due to the continuous degradation of transistors' intrinsic gain and the low supply voltage of modern scaled technologies, more gain The associate editor coordinating the review of this manuscript and approving it for publication was Teerachot Siriburanon . stages are required [35] and in any case the development of novel compensation networks remains an important research area in advanced CMOS technologies.
Despite from one side several multistage amplifier compensation networks were proposed and analyzed [1]- [40], and, hence, we know their voltage transfer functions which are typically reported in the original or successive papers, the continuous research on this domain maintains unchanged the need to evaluate the voltage transfer function especially in a novel more complex topology that could be adopted. Hence, methodologies to calculate the symbolic voltage transfer function simply and efficiently are still important.
Traditionally, the calculation of a symbolic transfer function is a very lengthy and complex task if only Kirchhoff laws at nodes and meshes are used. To help the designer, computer-aided design (CAD) tools are developed to carry out the small-signal analysis such that the transfer function can be extracted in factorized or non-factorized form [41]- [48]. Simplifying circuit-level methods are used for pole/zero extraction, some of which are relied on dividing the frequency spectrum into small pieces [43], approximation of the time constants [44], developing new circuit micromodel [49], [50], or analysis of signal flowgraph [41]. Despite these approaches could be ideally suited also for pencil and paper evaluation, the final expressions are, however, complicated and cannot be analyzed simply, thus these strategies are more suited for CAD tools rather than for hand calculations.
Among the several papers and books where compensation techniques for multistage amplifiers are treated and their voltage transfer function is calculated, some circuit-level techniques suitable for a pencil and paper approach can be found in the literature [51]- [54]. For instance, one may calculate the location of the poles of a three-stage nested Miller compensated (NMC) amplifier by assuming that the second compensation capacitor is short-circuited, and the inner gain stage is in unity-feedback configuration [51]. Alternatively, the compensation network of an amplifier may be analyzed directly based on the concepts of control-centric Local Feedback Loop (LFL) [52], [32] or equivalent output impedance of the compensation loop [55], [56]. Similar methodologies facilitate the designer's ability to calculate the transfer function given that the type of the amplifier was specified a priori. A control-centric design-oriented analysis methodology based on a simplified feedback theory is presented in [54], helping to quickly evaluate the pole frequencies. Nevertheless, no clear symbolic expression can be extracted in general form, hindering a general understanding of the contributing and the limiting factors of the amplifier's performance.
In this paper, we develop a simple methodology that allows to efficiently calculate the symbolic transfer function of a multistage amplifier with its specific compensation networks. The methodology is suited to be also applied with pencil and paper and gives very accurate results. In particular, three general amplifier models are introduced and analyzed, which represent basic topologies found in the literature. For these amplifier models, the symbolic transfer function is derived and specific strategies for the zero and non-dominant pole expressions are presented. Thus, the final symbolic transfer function can be written in the required standard form.
The application and accuracy of the approach are reported for a set of six amplifiers, which includes classical and advanced topologies that can be considered as typical cases of study, even if the approach was positively used and tested for other several topologies. In particular, the amplifiers considered to validate the methodology are: -a two-stage Miller compensation with nulling resistor (MCNR) [1]; -a three-stage with NMC [5], [6]; -a three-stage with reversed Nested-Miller compensation (RNMC) [6]; -a three-stage with the nested Miller compensation and a current buffer in the external loop, named active-feedback frequency compensation (AFFC) [16]; -a three-stage with single Miller compensation named impedance adapting compensation named (IAC) [29]; -a three-stage with single Miller compensation and current buffer, named cross feedforward cascode compensation (CFCC) [31]. Moreover, the results show that the entire procedure can be summarized to find the variables used in a symbolic transfer function expression.
The manuscript is organized as follows. In Section II, after some preliminary considerations, the methodology is presented and developed, showing the evaluation of zero and poles and of the whole transfer function, as well as approximated calculation of the dominant pole. Section III reports the application, in order of complexity, on the six amplifier topologies selected as typical cases. Design considerations and remarks arising from the proposed methodology are included in Section IV. Finally, the conclusions are given in Section V.

II. THE PROPOSED METHODOLOGY A. ABBREVIATIONS AND ACRONYMS
After inspecting the circuit topology of a huge number of multistage amplifiers presented in the literature, which includes both the conventional and the novel solutions, it was found that a generic topology can be modeled by using, in a recursive way if needed, the generalized three circuit configurations shown in Fig. 1 and named type I, type II, and type III.
In particular, as it will be better detailed and explained in the next Section, considering the well-known topology reported in references, the type I model can be used for the amplifier that adopts the Miller compensation [1], NMC [5], RNMC [6], single Miller compensation (SMC) [22], together with the IAC single Miller topology [29], (i.e., compensation topologies without current or buffer or amplifier in the external loop). The type II model can be considered for two-stage amplifiers with Miller compensation and current buffer [8], [53], [66] and AFFC amplifier [16], while single miller topologies with a current buffer, like CFCC [31] and the cascode Miller-compensation with local impedance attenuation (CLIA) [34] (not included in this manuscript for space reason) can be reported and analyzed with the type III model.
It is worth noting that the main difference between the models in Fig. 1 is the way the input is connected to the feedback pathway of the frequency compensation network. In any case, the input transconductance, G mi , converts the input voltage into an equivalent ac current, and the current is applied to the compensation loop. The transconductance G mi is considered unchanged at the frequencies of interest and can be positive or negative depending on circuit implementation. The compensation loop is comprised of the frequency-dependent transconductance G m (s), in negative feedback configuration, and supplies the load impedance z L (s).
Considering the feedback network of the three model types, for the type I model the feedback elements in Fig. 1(a) connect the output of G m (s) to its input directly, whereas for type II in Fig. 1(b) the one-way current buffer with constant G mC (and an input impedance of 1/G mC ) buffers the feedback current, and prevents the feedforward current flowing to the output through z A (s). Finally, the type III model in Fig. 1(c), where the input transconductance is broken into identical G mi /2 stages, can be seen as a combination of the two other models in Fig. 1

(a) and (b).
Note that also a type IV model could be considered, which uses a voltage buffer inside the feedback loop instead of the current buffer [7], [64], but presently, especially for the low voltage power supply of the typical application, it is not a practical solution. Moreover, by inspection of Fig. 1, it is apparent that type III model can be seen as a more general topology of type II model and hence could be, in principle, merged. However, since the zeros of the type II model, unlike to type III model, may depend on G m (s) (as it will be shown in the next sub-section), we decided to maintain two different models which appear to be more effective from a practical point of view.
In all the cases considered, the symbolic voltage-gain transfer function from v i to v o can be generally expressed as where A 0 and p −3dB p −3dB denote the DC voltage gain and the dominant pole, respectively, and N Z (s) and D NP (s) are the zeros and nondominant poles polynomials, respectively, being The polynomial D NP (s) contains the most important bandwidth-and stability-limiting pole frequencies, whereas N Z (s) contains the zero frequencies which generally may also affect the overall stability, depending of course on their frequency.
A symbolic transfer function in the form of relationship (1) is very helpful for writing all the design expressions in symbolic form. For instance, a symbolic phase margin (PM) expression can then be expressed as where GBW is the gain-bandwidth product and is given by Moreover, to take advantage of the model treated, it is conventionally assumed that the amplifier contains linear elements only. Hence, the transfer function would be fractional, and contains unchanged coefficients for N(s) and D NP (s) expressions: Analysis of the transfer function provides insightful knowledge on the behavior of the frequency compensation applied. To this end, N (s) and D NP (s) in their most general form must be evaluated. Thus, instead of using a direct transfer function evaluation, or the adoption or other approaches such as Rosenstark method [57] or Signal Flow Analysis [58], the analysis in the rest of this section is devoted to directly derive N(s) and D NP (s) through a depth circuit observation and practical considerations. In particular, it will be shown that the zeros originate from the feedforward pathways and the shunt elements within the input-output pathway, whereas the location of nondominant poles is mainly governed by the compensation loop.

B. ANALYSIS OF ZEROS
It is possible to formulate the transfer function zero expressions by revisiting the conditions leading to a 'zero'. A zero is a complex frequency, s zi , where v o evaluated at its value is equal to zero (i.e., v o (s zi ) = 0), and it can be regarded as the input frequency s zi that yields a virtual grounded output. Different scenarios end up with such result for the models under consideration. In particular, considering the type I model in Fig. 1(a), we found the zeros under the following conditions: a) an input frequency that generates a load impedance equal to zero (i.e., z L (s) = 0), which in turn means c) a current through the load impedance equal to zero; this case corresponds to a complex frequency where the current supplied by the G m (s) becomes equal to the current of the feedback element Thus, any zero of the type I model transfer function is obtained from one of the three above cases and combining them in a general and compact form we get The two zero expressions in (8) and (9) are valid for the amplifier model type II illustrated in Fig. 1 The series combination of z A (s) and 1/G mC is connected to the output and generates additional zeros. The output will be grounded when the series impedance of the two elements becomes zero (i.e., z A (s) + 1/G mC = 0) and we can write Thus, the generalized zero expression of model type II is given by Equation (8) still holds for the model type III illustrated in Fig. 1(c). Other zero expressions can be, however, found by setting the output voltage to zero. In particular, if v o = 0, the voltage v C can be expressed in terms of the input voltage, v i , as Hence, taking into account the above relation, the feedback Thus, applying the current law to the output node yields and the zero equation is expressed by where the approximation holds since the first 1 in relationship (19) can be safely neglected with respect to the other terms which are normally much higher (remember that G m (s). z A (s) and G mC (s). z B (s) represent two gains). The symbolic zero expression of the model type III can be written as By inspection of the N i (s) expressions derived above for different amplifier models, it is worth noting that the feedforward pathways and the shunt elements are responsible for generating a zero.

C. ANALYSIS OF POLES
Remembering that in a network the natural frequencies, i.e. the poles, only depend on the network topology and component values, but not on the input [59], to evaluate the poles of the transfer function we can calculate the input or the output impedance and take their poles.
Consider the model type I illustrated in Fig. 1(a). The output impedance is that of a typical simple feedback circuit and, consequently, it can be simply evaluated by applying any usual method for impedance evaluation in feedback amplifiers, such as Blackman [60] or modified Rosenstark [57], or even directly. In particular, we get Thus, by using (4)-(7), after routine manipulations, the final z eq (s) can be expressed by and hence the pole expression of the transfer function, being the same of the relationship (23), is given by Concerning the type II and type III models, their output impedance is equal 1 and by inspection of Fig. 1(b) or 1(c), observing that to evaluate the output impedance type II and type III models are equivalent to type I if (26) are used in the compensation loop instead of G m and z B , respectively. Thus, from (22) we get 2 Therefore, from (24) the denominator of type II and type III models is given by Moreover, being and equation (28) becomes

D. GENERAL TRANSFER FUNCTION
Noticing that the feedback element z A (s), contains generally a series compensation capacitor, which means for any of the proposed models, the symbolic DC gain formula can thus be expressed by 1 We are implicitly assuming for type III model, as it happens for real cases, that the output impedance of the upper G mi /2 transcoductance can be neglected (i.e., much higher than 1/G mC ). 2 Using (25) and (26), eq. (27) reduces to 1+G m( s)·z B (s) //z L (s) but this form is less practical at this moment.
To ensure that condition (2) is met for the type of the transfer function in (1), the standard N Z (s) should be implied in the form of (1 + αs + βs 2 + . . .), while inspecting the N(s) expressions derived in subsection II.B we find a constant term. Hence, we can write that where i is equal to 1, 2 or 3. Concerning eqs. (24) and (33), to represent the transfer function as in (1), despite D Pi (s), with i from 1 to 3, contains all the amplifier poles, we have to identify the dominant pole and factorize it. At this purpose we can consider that the dominant pole, p −3dB , can be evaluated by applying the open-circuit time constant method [62] and, since it is typically imposed by exploiting the Miller effect on the C C , of z A (s) [49], we can write (37), as shown at the bottom of the next page, where C B and C L are the capacitive contribute of z B (s) and z L (s).
The function D Pi (s) in a general form can be written as D Pi (s) = a 0 + a 1 s + a 2 s 2 + . . . + a n s n (38) where, of course, Thus, remembering that a compensated amplifier has a dominant pole approximated by the transfer function related to the non-dominant poles only with the unitary constant term can be expressed by In conclusion, expression (42) summarizes the analysis of this section, providing a symbolic voltage-gain transfer function expression for most multistage amplifiers used in the literature where i is from 1 to 3 and N i (s) and D Pi (s) are summarized in Table 1.

E. APPROXIMATED POLE EXPRESSIONS
A useful approximation can be obtained by noting that in a compensated amplifier the non-dominant poles are at frequencies higher than the transition frequency. They are, consequently, much higher than the dominant pole that is usually entirely set by the Miller compensation capacitor.
Then, at the frequency of the non-dominant poles we can assume the compensation capacitor is short-circuited. The compensation capacitor is inside z A (s), thus the assumption of short-circuited compensation capacitor means to evaluate and substitute it to z A (s) in (24) and (32) to achieve the equation for the non-dominant poles. In particular, rewriting (24) and (33) by introducing z Alim we respectively get where D NGNPi (s) are equations with only the non-dominant poles, but not in the required form. Indeed, note that the dominant pole of the transfer function can be approximated by Then, the expression for the non-dominant poles with one as constant term is given by Despite being useful, especially when a Miller capacitance or a nulling resistance in the compensation path is adopted (i.e., for amplifiers that are represented with type I model), this approximation may lead to errors when current buffers are introduced in the compensation path. As such, the small input resistance of the current buffer in series makes quite important the size of the Miller capacitance and its ac current on the location of non-dominant poles. Approximated D NGNPi (s) are summarized in Table 1.

III. APPLICATIONS OF THE PROPOSED METHODOLOGY
The achieved symbolic transfer function expression can significantly reduce the calculations of OTA transfer function. Fig. 2 presents several well-known circuit diagrams used to realize two-stage and three-stage amplifiers, where resistors, capacitors, and transconductors of different blocks are explicitly represented using conventional notations. In this section, we shall analyze these amplifiers as a typical case of study by using the methodology developed in the previous section based on the models introduced in Fig. 1 and summarized by equation (42) and Table 1.

A. MILLER COMPENSATION WITH NULLING RESISTOR
As the classical method to stabilize a two-stage amplifier [51], Miller compensation places a compensation capacitor among the input and output of the second stage to dominate the pole of the first stage output. The original Miller compensation is mostly avoided since it suffers from stability problems due to a right-half plane (RHP) zero and improvements that avoid the RHP are usually adopted [51], [63].
The most known and used solution that allows to avoid the RHP is based on a nulling resistor (R C ) which is therefore  placed in series with the compensation capacitor (C C ) to create a negative zero according to the circuit diagram shown in Fig. 2(a). In addition to the input g mi stage with the output capacitor (C 1 ) and resistor (R 1 ), the block diagram of Fig. 2(a) is composed of an inverting g mL stage with the feedback R C and C C , driving C L and R L of the amplifier. This structure is analogous to the model type I discussed in Section 2, when taking into consideration G mi = g mi , and the following relations for remaining components: The DC gain and dominant pole are obtained from (35) and (37), respectively. Moreover, usually (37) can be simplified into The zeros expressions are easily derived as Concerning the non-dominant poles, we can use the approximated expression (44). Thus, approximating the first term of D P1 (s) as dG m dz B nz L = R L + R 1 g mL R L + R C + R 1 ≈ R 1 g mL R L (54) and being we get which from (47) gives the non-dominant pole function in the required form It is worth noting that application of the accurate relationship (41) only adds the negligible term, C L C 1 /C C g mL , thus yielding the same result.

B. NESTED MILLER COMPENSATION
Nested Miller compensation is an advanced variant of the Miller compensation presented formerly for three-stage amplifiers [3], [5], [6]. Fig. 2(b) illustrates the circuit schematic of a three-stage NMC amplifier, comprising from an inverting first stage, a non-inverting second stage, and an inverting third stage modeled by their equivalent transconductor (g mi , g m2 and g mL ), output stage resistor (R 1 , R 2 and R L ) and output stage capacitor (C 1 , C 2 and C L ). The two compensation capacitors of NMC, i.e. C C 1 and C C 2 , connect the third stage output to the first and the second stage outputs, respectively. The capacitor C C 1 creates the main pole of the amplifier, while C C 2 controls the quality factor of the non-dominant poles. This structure is analogous to the model type I in Fig. 1(a), when considering where the rightmost approximation in (59) holds if The DC gain and the dominant pole can be evaluated from (35) and (37) noting that z B (0) = R 1 , G m (0) = g m2 g mL R 2 and z L (0) = R L . Nonetheless, it is essential to evaluate the G m (s) and z L (s) expressions before the proposed method can be applied to evaluate N zi (s) and D NPi (s). To this end, the elements inside the rectangular dash line in Fig. 3(a) can be represented by an equivalent transconductor G m (s), with input voltage v i , output voltage v o , and an output impedance of z o .
By applying the current law at the output of the second stage, the output current, i o is related to v i and v o by Thus, since typically C C 2 >>C 2 , R 2 C C 2 s>>1 and g mL >>C C 2 s we get Due to the impedance z o at the output of G m (s) the load impedance is modified according to the equivalent high-frequency model of NMC amplifier shown in Fig. 3(b).
By using (58) to (62), being N 1 (0) = −g m2 g mL , relationship N z1 (s) is expressed by which is exactly the expression that is found in papers [12]- [14] and textbooks [49], and applying the approximated pole expression, being z Alim = 0 and D NGNP1 (0) = g m2 g mL , we get D NP1 (s) as In this case application of the accurate relationship (41) only adds the terms (C C 2 C 1 /g m2 C C 1 )s and (C C 2 C 1 /g m2 g mL ) (C C 2 /C C 1 )s 2 which are negligible. Moreover, neglecting C 1 in the s 2 term, which is typically much lower than C L , (64) gives exactly the approximated denominator reported in papers [12]- [14] and textbooks [51].

C. REVERSE NESTED MILLER COMPENSATION
When a three-stage amplifier is realized with an inverting first and second stage and a non-inverting last stage, the NMC cannot be applied and the RNMC is adopted (Fig. 2(c)), formerly presented in [6] and analyzed with details in [15]. As compared to NMC, RNMC also shows inherent benefits in terms of speed performance as demonstrated in [64]. An RNMC amplifier diagram is fitted to the generalized model type I, where and considering the generalized G m (s) and z B (s) found according to Fig. 4. In particular, the elements inside the rectangular dashed box of Fig. 4(a) can be integrated to an equivalent transconductor with input voltage v i , output voltage v o , and an input impedance z o . The voltage v x of the second stage output is related to v i by The output current i o , can be expressed in terms of v x and v i as Thus, by using the usual approximations (g mL R 1 , g mL R 2 >>1, The ratio between v i and i i should be measured to additionally evaluate z i of the new transconductor. Applying the current law at the second stage output, z i is calculated as Fig. 4(b) illustrates the equivalent high-frequency circuit schematic of the RNMC amplifier. The equivalent z i modifies z B (s) of the first stage to From ( Note that in this case a 0 = 0 in (41), but this happens for the approximation adopted in (65), (66), (69) and (71). Neglecting the second-order addends in the s 2 term of (72), as suggested in [15], we find exactly the transfer function reported in [15]. It is worth noting that if we apply the approximated pole expression, where z Alim = 0, we lack the two terms (C C 2 C 1 /g m2 C C 1 )s and (C 1 C C 2 /g m2 g mL C C 1 )s 2 , where the former of the two cannot be considered negligible as compared to the others in (72). Fig. 2(d) illustrates the architecture of the named three-stage AFFC amplifier [16]. It implements an active feedback network from the third stage output through the transconductor g mC , and the capacitor C C 1 to the second stage input (i.e., a NMC with a current buffer in the external loop). Again capacitor C C 2 adjusts the quality of the complex poles similar to NMC and RNMC amplifiers. Moreover, it also includes an additional feedforward g mf stage, which shunts to the main signal pathway comprised from g m2 and g mL , extending the bandwidth for g mf >> g m2 [39]. The AFFC block diagram is similar to that of model type II for G mC = g mC and G mi = g mi , and the combination of the second and the third stages can be analyzed similarly to the approach used for the NMC amplifier in sub section 3.2. The result is, hence, an equivalent G m (s) between the first and third stage outputs reported in (61), but including g mf :

D. ACTIVE-FEEDBACK FREQUENCY COMPENSATION
and the load impedance given by (62). Fig. 5 reports the block scheme of the high-frequency AFFC amplifier as a model type II. In addition to G m (s) and z L (s), it includes the z A (s) and z B (s) given by (58) and (59), respectively. Of course, the DC gain and dominant pole are evaluated from (35) and (37), and again the dominant pole can be simplified with (52).
Beginning from (15), and since N 2 (0) = g m2 g mL g mC , the zero expressions N z2 (s) is given by From (41) and (33) (noting that in (41) a 0 = 0) we get If the approximated expression (44) is used, where z Alim = 0 and D NGNP1 (0) = g m2 g mL g mC , we lose in the s term the negligible addend with C 1 /C C 2 , but also the term with the ratio C L /C C 1 in the s 2 term. It is worth noting that neglecting in the s term of the denominator the contribute with C 1 /C C 2 we find that the first non-dominant pole is almost perfectly cancelled by the first zero in (74). Thus (74) and (75) reduce to the relationship reported in the original paper [16].

E. SINGLE MILLER CAPACITOR COMPENSATION
A more recent compensation techniques with respect to NMC and RNMC is based on the use of only a single Miller capacitor [26], [27], [29]- [32], [34]- [36], [39]. Since the first paper dates back twenty years ago [11] and another one five years later [22], investigation and application of this kind of strategy is increasing, especially for multistage amplifiers having high capacitive loads, such as [32], [34]- [36] and [39]. Among the various single Miller topologies with only passive components on the compensation loop, one of the most popular topologies named Impedance Adapting Compensation (IAC) [29] is considered in the following. The topology reported in Fig. 2(e) adopts a series R-C network (R D and C D ) added to the second stage output, to further split the non-dominant real poles.
In order to evaluate the voltage-gain transfer function, the following model parameters have to be used For C D >> C 2 , R 2 >> R D , and R 2 C D s >> 1, the equivalent G m (s) is expressed as The expressions z B (0) = R 1 and z L (0) = R L should be used when evaluating the dominant pole and the DC gain from (35) and (37). The zeros are given by the polynomial and from the approximated pole expression, being z Alim = 0 and D NGNP1 (0) = g m2 g mL , we get Note that the precise relationship (41) has one more negligible term (C D C L C 1 /g m2 g mL C C )s 2 . The resulting transfer function is the same of that reported in [29], even if the order of the numerator and denominator is reduced due to the approximation adopted on G m (s) according to (79).

F. CROSS FEEDFORWARD CASCODE COMPENSATION
Among the amplifier with single Miller compensation the first specifically devoted to high capacitive load was the topology named cross feedforward cascode compensation (CFCC) [31]. A single compensation capacitor with a current buffer realizes an active feedback network to enable driving the ultra-large load capacitors, according to the CFCC diagram in Fig. 2(f). The amplifier also contains two feedforward stages g mf 1 and g mf 2 , which improve the largeand small-signal operation [36]. As shown in Fig. 6, we simplify the analysis by transferring the input of g mf 1 from the first stage to the second stage input. Thus, the equivalent transconductor, denoting A v1 (s) = g mi (R 1 //(1/C 1 s)) as the gain of the first stage, is g mf 1 /A v1 .
The CFCC architecture matches with the type III model (G mC = g mC and G mi = g mi ), with the corresponding z A (s), z B (s) and z L (s) are again given by (76), (77) and (78), respectively.
The new transconductor g mf 1 /A v1 , is now shunted to g m2 resulting to an effective transconductance of g m2 + g mf 1 /A v1 . Hence, G m (s) is Being N 3 (0) = 2g mC , N z3 (s) yields and from (41) with (33) we get Relationship (83) and (84) gives zeros and non-dominant poles also reported in [31], even if the results are more accurate since in the original manuscript additional approximations are done from the assumption that C L is much higher than C C . It is worth noting that, in this case in VOLUME 10, 2022 which the compensation loop has an active component, the approximated pole expression may be not sufficiently accurate since it lacks the two terms (C L C 1 /g m2 g mL R 2 C C )s and (C L C 1 C 2 /g m2 g mL C C )s 2 . Table 2 summarizes the model parameters of the compensation schemes analyzed in Section III. By inspection of Table 2, it is apparent that, regardless of the amplifier model, the main difference between different schemes is from the perspective of G m (s). It affects the entire features of the amplifier with frequency compensation and results in many advantages and disadvantages in terms of power and area. Of course, the type of the model is another factor that impacts considerably the operation of an amplifier. Moreover, from Table 2, it is evident that NMC and AFFC, and IAC and CFCC have similar model parameters. The differences of the amplifier models, however, enhance the operation of the AFFC and CFCC topologies over their counterparts. Indeed, for identical model parameters, both models type II and III employ a series G mC with z A (s), a property that leads to superior operation as compared to model type I, for identical parameters. This can be demonstrated by investigating the pole expressions of the three models.

IV. COMPARISON AND REMARK ON THE ANALYZED MODELS
In particular, looking into (24), among the four terms appearing in D P1 (s) the factor nG m dz A nz B nz L is typically the term with the lowest order, as it contains three nominators that are mostly constant (see Table 2). And considering this condition, we can factorize the terms in (24) that can be rearranged as For the same reason, the order of G mC nG m dz A nz B nz L term is mostly the lowest in the D P2,3 (s) of models type II and III. Thus, factorizing this term in (33), yields Since typically z B (s)>>1/G mC , the models type II and III generate larger nondominant poles for identical C L (i.e., z L (s)) and C C (i.e., z A (s)), z B (s) and G m (s) of the model type I. The pole expressions in (85) and (86) also suggest the following design rules for improving the performance when the load and compensation capacitors are known a priori (unchanged z L (s) and z A (s), respectively): 1. The impedance z B (s), of the first stage should be increased to reduce the second term of the standard pole expressions, thereby pushing the nondominant poles to higher frequencies (this can be accomplished by trying to further reduce the parasitic output capacitor C 1 of the first stage). 2. The second term inside the brackets in (83) and (84) can be suppressed by further enlarging G m (s). This can be made possible by increasing G m (0), and by pushing further the nondominant poles of G m (s) to higher frequencies. For all the models proposed in Fig. 1, the zeros of z L (s) will be also the same zeros of the transfer function. Such zeros are, indeed, very common in low-dropout regulators (LDOs) [64]- [66]. The zeros of the models type I and II may depend on G m (s), contrary to model type III which does not contain a zero related to G m (s). An advantage of model type II is its potential to generate a LHP zero at frequencies lower than that of model type III, which can be concluded by comparing the zero expressions appeared for these models in (15) and (21). More LHP zeros might be generated by model type II via G m (s) and z B (s).

V. CONCLUSION
A simple methodology to quickly carry out a closed-form expression for the symbolic transfer function of multistage amplifiers with frequency compensation is proposed.
The method can be applied to any amplifier that can be modelled through the general models reported in Fig.1, which, to the best of the authors' knowledge, unless for the old and not used case where a voltage buffer is used [7], allows to represent all the different solution reported in the literature so far. Anyway, it can also be simply extended to other novel and original topologies that cannot be represented by the model in Fig. 1, by simply following the procedure described in Section II for the three type models.
While simplifying the fundamental task of symbolic analysis of an amplifier, the methodology gives an insightful view into the operation of the applied frequency compensation network, offering design rules for improving the performance when the load and compensation capacitors are known a priori. The proposed method is validated through the analysis of a number of the widely adopted amplifiers found in the literature and it is shown that, in all cases, the same transfer function reported in the original paper is obtained.
To sum up, the main advantages of the proposed methodology are as follows: 1. It happens frequently that, after writing several pages of the small-signal equations for a multistage amplifier, the designer gets confused by the theoretical complications and is forced to get back and check the results again. The same problem led to different forms of transfer functions with inaccurate results in the literature, some of which happen to be even incorrect. With the proposed systematic solution, the designer will not deal with the lengthy and complex small-signal equations of the amplifier. They should only specify the amplifier's model and find the elements before using the proposed symbolic transfer function. This is equivalent to breaking a difficult problem into several simple and easy steps. With the aim of providing the reader with a guideline to apply the proposed methodology, Fig. 7 show a flowchart that summarizes the steps to follow in order to carry out the transfer function.
Modeling the transfer function of several amplifiers in the form of a single symbolic equation paves the way to compare their properties easily. Some results can be found in Section IV where the terms inside the symbolic transfer functions are compared.