0.5 V Current-Mode Low-Pass Filter Based on Voltage Second Generation Current Conveyor for Bio-Sensor Applications

This paper presents a low-voltage low-power current-mode third-order low-pass filter (LPF) based on voltage second generation current conveyor (VCII). The VCII utilizes the bulk-driven MOS transistor technique to achieve a wide input voltage range at low supply voltage of 0.5 V. Also, the VCII operates in the subthreshold region to achieve nano-power consumption of 390 nW. A third-order low-pass filter that is presented as an application of the VCII can operate as both current- and transimpedance-mode filters. The filter consumes 2.73 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> and the total harmonic distortion (THD) is below 1 % for sine-wave input signal below 350 nA<sub>pp</sub> @ 10 Hz. The post-layout simulation results based on TSMC 0.18 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process are presented and confirms the futures of the filter.


I. INTRODUCTION
Recently, there is a gaining research interest for current-mode technique of the filter design. Compared with the voltagemode counterparts the current-mode filters have been presented in the literature exhibiting improved performance [1]. There are several current-mode building blocks for realization high-order current-mode filters such as current differencing buffered amplifier (CDBA) [2], current-mirror [3] and current differencing transconductance amplifier (CDTA) [4], [5] available in literature. The developed filter topologies provide a higher maximum frequency of operation and a more accuracy of transfer function due to smaller parasitic parameters compared with the filters realized using voltage-mode op-amp configurations [6].
The associate editor coordinating the review of this manuscript and approving it for publication was S. M. Hasan .
Since these signals attributes small amplitude and low frequency, high-order filters for applications to these systems should be designed to meet high dynamic range and lowpower consumption. The analog low-pass filter is usually required to select the frequency range and eliminate out-ofband noise in the front-end of biomedical systems. The highorder filter based on the RLC prototype is usually required due to lower pass-band sensitivity compared with the cascade approach using biquads.
Voltage second generation current conveyor (VCII) was introduced in [8]- [10]. Conventional VCII has three terminals (y, x, and z), the first stage between y and x terminals is a current follower and cascaded by a voltage follower between x and z terminals as the second stage. This device is designed to obtain a low impedance voltage output node for avoiding an extra voltage buffer for application requiring a voltage output signal [11]. The required additional voltage buffer can lead to higher power consumption and a large chip area. A number of VCII structures have been reported recently in literature [11]- [18]. Unfortunately, these structures are designed by rather high supply voltage and high-power consumption such as ±1.65 V/330 µW in [11], ±0.9 V/120 µW in [12], ±1.65 V/320 µW in [13], ±0.9 V/664 µW in [16], VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ ±0.45 V/79.3 µW in [18]. Therefore, these VCIIs are not suitable for applications to ultra-low power analog signal processing. There are interesting applications of VCII available literature such as simulated inductor [15], universal filter [19]- [21], first-order all-pass filter [22], capacitance sensors [23], and full wave rectifier [24]. In this work, a current-mode third-order low-pass filter based on voltage second generation current conveyor for bio-sensor applications is proposed. The proposed VCII is designed using bulk-driven (BD) MOS technique to provide wide input voltage range while the MOS operates in subthreshold region to obtain low-voltage low-power operation. The VCII is designed to work with voltage supply V DD = 0.5 V and power consumption is 390 nW. The proposed third-order filter was designed and simulated in the Cadence environment using a 0.18 µm CMOS process from TSMC. Post-layout Simulation results show that the filter offers a bandwidth (BW) of 250 Hz, and a power consumption of 2.73 µW.

II. PROPOSED CIRCUIT
A. 0.5 V VCII Fig. 1(a) shows the symbol of VCII and its equivalent circuit is shown in Fig. 1(b). The relation between the terminal voltages and current can be described by where β is the current gain and α is the voltage gain of VCII (unity for the ideal case). It should be noted from (1) that the relation between x and y terminals is the current follower and the relation between z and x is the voltage follower, where r y , r x , and r z are respectively the parasitic resistance at y, x, and z terminals. Fig. 2 shows the proposed VCII that is consists of two op-amps operating in unity gain feedback, firstly presented in [25], [26]. The first op-amp has two outputs and is created by transistors M 1 -M 4 and M 9 -M 12 that ensure the unity gain current transfer I x = I y . The second op-amp is created by M 5 -M 7 and M 13 -M 15 that ensure the unity gain voltage transfer V z = V x . The bias current I B and transistor M 8 set the currents of the VCII. For the first op-amp, transistor M 1 , M 2 create non-tailed differential amplifier loaded by current mirrors M 9 , M 10 , the second stage is created by transistor M 3 loaded by the current source M 11 . The bulk-drain terminals of M 3 and the bulk terminal of M 2 are connected together that creates a negative unity feedback connection. Transistors M 4 , M 12 create a copy of the current M 3 , M 11 . The minimum voltage supply of this structure is: where V SG and V DSsat are the source-gate voltage and saturation voltage of the MOS transistor, respectively.  The output resistances of the y, x and z terminals can be calculates as: 12 (4) r z ∼ = g oM 5 + g oM 13 g mM 7 g mbM 6 (5) where g m , g mb , g o are the transconductance, bulk transconductance and output conductance of the MOS transistor, respectively. The input referred thermal noise is determined by the input noise of the input differential stage: (g mM 1,M 2 + g mM 9,M 10 ) where n is the subthreshold slope factor, k is the Boltzmann constant and T is the temperature. Fig. 3 shows the doubly terminated RLC ladder third-order low-pass filter by R s and R L are connecting at the input and output ports respectively. Using KCL routine analysis the voltage and current relationship in several nodes can be written as: (11) where I RL = I out and V 3 = V out . Using (7)-(9), signal flow graph of RLC low-pass filter can be shown in Fig. 4. It should be noted that three lossless integrators are required for realizing third-order low-pass filter.     5 shows the proposed current-mode third-order lowpass filter using VCIIs. The VCII 1 , VCII 2 , C 1 are worked as a first integrator while VCII 3 , VCII 4 , C L1 are worked as a second integrator and VCII 5 , VCII 6 , C 2 are worked as a third integrator. The inductor L 2 in the RLC prototype can be converted to the capacitor C L1 through the VCII and R by L 2 = C L1 R 2 . The VCII 7 is used to provide high-output impedance for current-mode circuit. Thus, the proposed current-mode filter offers low-input impedance and high-output impedance which is meet for current-mode circuit. From the property of VCII such as V z = V x , node V 3 can also be used as output voltage terminal (V out ). In this case, the filter works as a transimpedance-mode filter which is meet a low-input impedance and a low-output impedance. The VCII 7 can be vanished and the resistor R L must be connected to ground if it works as a transimpedance-mode filter.   The DC current characteristic of I X versus I Y and current error are shown in Fig. 7. The circuit has good linearity in the range of ±190 nA. Note, that even though the input current range is relatively low, it is sufficient for the proposed application. Fig. 8 shows the DC voltage characteristic of V Z versus V X and voltage error. The low voltage error is evident for ±200 mV voltage range.

The VCII was designed and verified in Cadence Analog
The impedance frequency characteristics of Z X , Z Y and Z Z are shown in Fig. 9. At low frequencies the X terminal  enjoys high output resistance R X = 16.1 M while the resistances R Y = R Z = 5.63 k . The value of these parasitic resistances of Y and Z terminals should be taken into account during the design of the applications. The voltage and current input-referred noises (IRN) of the VCII at Z and X node, respectively, are shown in Fig. 10. The voltage IRN is 500nV, while the current IRN is 0.481pA @ 1 kHz.
The performances of the VCII are presented in the Table 1 and compared to most recent VCIIs presented in the literature [12], [13], [18], [22]. It is evident that the proposed structure has the lowest supply voltage, lowest power consumption with extended input voltage range ±200 mV that make it suitable for bio-sensor applications. Also the efficient of the design and the low voltage operation capability are confirmed by the figure of merits (V TH /V DD ) × 100 (%) and (V in-max /V DD ) × 100 (%).    11 shows the frequency characteristics of the proposed and the RLC filter. The gain at low frequencies is −6.7 dB and −6.02 dB for the proposed and RLC filter, respectively, while the −3 dB is 248.2 Hz for both filters. The tuning capability with R varied from 440 k to 1440 k is shown in Fig. 12 the −3 dB is varied form 360.6 Hz to 96.17 Hz, respectively.
The histograms of Monte-Carlo (MC) 200 runs for gain and −3 dB bandwidth are shown in Fig. 13. The mean value of the gain is around −6.713 dB with standard deviation around 113.6 mdB. For the −3 dB BW the mean  value is around 248.3 Hz with standard deviation around 1.93 Hz.
The process, voltage and temperature (PVT) corners analysis were carried out with transistor corners: ss, sf, fs, ff, voltage supply corners ±10% of V DD , and temperature corners −20 • C to 70 • C. The results of the frequency characteristics of the proposed filter with PVT corner analysis are shown in Fig. 14. The minimum −3dB BW = 238.2 Hz and the maximum = 250 Hz. The minimums and maximum gain were around −6.67dB and −6.98 dB, respectively.
The transient analysis of the filter is shown in Fig. 15. The input sine wave signal applied to the filter In = 50 nA pp @10 Hz. The THD of the output signal is 0.09 %. The filter was tested for different peak-to-peak signal and with 100 Hz, the results of THD is shown in Fig. 16. The THD is below 1 % for input signal below 350 nA pp .

IV. CONCLUSION
This paper presents a third order low pass filter based on lowvoltage low-power VCII. The VCII is capable to work with supply voltage of 0.5V while offering a wide input voltage range thanks to using the bulk-driven MOST technique operating in the subthreshold region. The filter can be operated as both current-mode and transimpedance-mode filters. The filter consumes 2.73 µW and the THD is below 1 % for input signal below 350 nA pp @ 10Hz. Intensive postlayout simulation including MC and corner analysis confirm the performance of the filter. TOMASZ KULEJ received the M.Sc. and Ph.D. degrees from the Gdańsk University of Technology, Gdańsk, Poland, in 1990 and 1996, respectively. He was a Senior Design Analysis Engineer with the Polish Branch, Chipworks Inc., Ottawa, Canada. He is currently an Associate Professor with the Department of Electrical Engineering, Częstochowa University of Technology, Poland, where he conducts lectures on electronics fundamentals, analog circuits, and computer aided design. He has authored or coauthored over 80 publications in peer-reviewed journals and conferences. He holds three patents. His recent research interests include analog integrated circuits in CMOS technology, with emphasis to low-voltage and low-power solutions. He also serves as an Associate Editor of the Circuits, Systems, and Signal Processing and IET Circuits, Devices and Systems. He was also a Guest Editor for the Special Issues on Low Voltage Integrated Circuits on Circuits, Systems, and Signal Processing in 2017, IET Circuits, Devices and Systems in 2018, and Microelectronics Journal in 2019. VOLUME 10, 2022