Simulation-Assisted Design of a Power Stack for Improving Static Current Sharing Among Three IGBT Modules Connected in Parallel

In this study, Q3D and Simplorer software were adopted to design a single-phase power stack with equal output current on three paralleled IGBT modules in high power application, therefore, the derating of total current will be reduced, which can improve the current utilization and power density of power stack. The performance of the designed stack was verified using a double-pulse test (DPT). The circuit used in the DPT regarded the power stack output current as static current, which is a critical index to evaluate current sharing. The static current sharing among the IGBT modules was mainly dependent on the stray inductance of the DC busbar, IGBT modules, and phase output bar (POB), which is used to connect the IGBT modules to load, in the power stack. Cosimulation was performed with Simplorer and Q3D to determine the stray inductance of the IGBT modules, DC busbar and POB, and a constant-current-slope method was used to verify the inductance. Subsequently, design the shapes of the DC busbar and POB for attaining maximum ratio of imbalanced current (MRIC) of the three IGBT modules is within 3% under 200% (2400A) rated current. The cosimulation results indicated that the MRIC of the current paths in power stack were 0.8%. Finally, three IGBT modules and a gate driver were used to construct power stack with 1000V DC link. The experimental results obtained by DPT indicated that the MRIC was 0.9% under 200% rated current, demonstrating the effectiveness of the proposed stray inductance design method.


I. INTRODUCTION
Insulated-gate bipolar transistors (IGBTs) are widely used in medium-voltage, high-voltage, and high-power systems because of their high current rating, high withstand voltage, and low loss. A half-bridge module with two IGBTs connected in series is typically used as a basic unit in converter or motor drive applications for the convenience of these applications [1], [2]. Therefore, a converter or an inverter is composed of low-or medium-voltage IGBT modules connected in series [3], [4] or parallel to increase the output power [5], which reduces the cost of wind turbine [6], traction driver [7], and ventilation [8] applications. Although IGBTs connected in parallel can effectively increase the output current, the power circuit should be designed such that it provides equal current to each IGBT [9]. The authors of [10] demonstrated that the derating of total current must be conducted by considering the current imbalance of IGBTs connected in parallel. They derived a formula that indicates that the derating of total current is 17.4% under an imbalance current ratio of 15% for three IGBTs connected in parallel.
To reduce cost and stock, the inverter used in wind generation applications usually contains multiple IGBT modules connected in parallel for constructing a single-phase power stack. A three-phase inverter is formed using three power stacks [11], [12]. According to the current change rate, the current of a power stack with IGBTs connected in parallel can be divided into static current and dynamic current, which have low and high change rates, respectively. Fig. 1(a) displays the dynamic and static current flow paths of a power stack with IGBT modules connected in parallel in a doublepulse test (DPT) method. The relationship between the IGBT module current and the DPT pattern is shown in Fig. 1(b). 2 VOLUME XX, 2020 The static current provides the required load current when the low-side IGBT is turned on, and dynamic current occurs at the turn-on and turn-off transients of the low-side IGBT. The main difference between the static and dynamic current flow paths is that static current flows through the load inductor to the POB, whereas dynamic current flows through the parasitic diode of the high-side IGBT and the Coss of the lowside IGBTs. Because of the low switching frequency of IGBTs in high-power applications, the power stack loss is dominated by static current [13] when compared with short turn-on and turn-off transient times.   Table 1. summarizes recent studies on current balancing for IGBTs connected in parallel. The factors affecting current distribution are as follows [14], [15]: characteristics of IGBTs, the gate driver circuit, the DC busbar, and the POB. Turn-on saturation voltage, stray resistance, and inductance of IGBTs, and the temperature difference among IGBT mod ules connected in parallel may affect the current sharing [14]- [18]; therefore, the same die production batch should be preselected and the parallel modules should be connected to the same heatsink to achieve superior current balancing [19].

Characteristic of power module
Investigate the influence of VCE(sat.), stray impedance and temperature on current sharing. [14]- [18] New module package provides + and -in the same side to reduce the DC-link stray inductance.
[20], [21] Gate driver Active gate voltage control for current balancing by FPGA and DSP.
[19], [22] Use common choke in the gate circuit to drive paralleled IGBTs by single gate-driver to improve current sharing.
[24], [26] DC Busbar Demonstrate placement of the DC link capacitors with slotted busbar which can provide good transient and static current sharing by experiment. [14] Phase output bar (POB) Add additional chokes in the phase connection to reduce the imbalanced current.
[24], [25] Demonstrate the influence of load connected position on the imbalanced current.
[26]- [28] Moreover, the DC+ and DC− terminals of IGBT modules connected in parallel should be adjacent to each other on the same side [20], [21] for reducing the stray inductance difference between the DC busbar and each IGBT module. In addition to IGBT modules, the gate driver circuit can effectively improve current sharing. In [19] and [22], active gate voltage control with online IGBT current detection was implemented to achieve superior static current sharing. Because of the requirement of real-time control during the IGBT turn-on period, most circuits are constructed using complex FPGAs, DSPs, and high-bandwidth current sensors [23]. However, such circuits cannot drive parallel IGBT modules by using a single-gate driver. In [24], [25] chokes were added to the phase outputs of IGBT modules connected in parallel to achieve balanced current distribution Studies [24], [26] have indicated that a gate driver with a common mode choke can achieve balanced static current distribution. A study [14] used a slotted DC busbar to improve dynamic current sharing; however, the optimal method for balancing static current remains unclear because the DC busbar incorporates a small percentage of stray inductance into the static current path. Moreover, the POB of the power stack is used to not only connect the IGBT modules [26]-[28] but also achieve static current balancing for IGBT modules. To ensure static current balancing, some studies [27], [28] have employed the same individual stray inductance from each IGBT module to load terminal in the POB. However, the studies cited in the aforementioned text have not described the POB design method and have not mentioned why the stray inductance of each IGBT path in the POB must be similar for achieving static current balancing. IGBT modules are included in the static current flow path depicted in Fig. 1(a); however, limited research has been conducted on the influence of the stray inductance of these modules on static current balancing. Furthermore, the DPT [22], [29] is generally used to test the current balancing of IGBT modules connected in parallel. Studies [9], [14], [17], 3 VOLUME XX, 2020 [30] have indicated that the wiring from the load inductor to the POB in the DPT setup affects output current balancing.
The aforementioned discussion indicates that appropriately designing the DC busbar and POB is important. The traditional design method for DC busbars is based on Maxwell's equations for calculating the trend of stray inductance [31], [32]. For complex-shaped POBs and DC busbars, Ansys Q3D or Maxwell 3D has been used for the quantitative analysis of the stray inductance [33]- [36]. The measurement of stray inductance inside the IGBT module is crucial. Studies [18] have only described the measurement of the internal resistance of IGBT modules but have not described the measurement of the stray inductance.
In this study, a single-phase power stack containing three half-bridge IGBT modules connected in parallel was constructed for achieving static current balancing. To design a laminated DC busbar and POB, the Q3D simulation software was adopted for analyzing the stray inductance of the IGBT modules. Moreover, the Simplorer software was used with Q3D to ensure that the stray inductances in the three static current paths of the IGBT modules were nearly the same for achieving static current balancing. The current balancing of the three IGBT modules was analyzed through cosimulations, and the suitability of the design was verified through careful measurements. Finally, a single-phase power stack with a DC link voltage of 1000V was constructed according to the specifications presented in Table 2. to verify the effectiveness of the design. The designed power stack contains a DC link capacitor tank with nine film capacitors (50.R19-764NT1, ELECTRONICON); three half-bridge IGBT modules (Mitsubishi Electric CM1200DW-34T) with 1200A rated current connected in parallel; a single-gate driver (Tamura, 2DUC51008CML1), which is used to drive the IGBT modules; a carefully designed DC busbar; and a carefully designed POB. The results by the DPT method indicated that the maximal current difference among the three IGBT modules was 38A at 200% rated current per IGBT module. Moreover, the maximum ratio of imbalanced current (MRIC) was 0.9% under a 200% (2400A) rated current of an IGBT module. The aforementioned results indicate the effectiveness of the proposed stray inductance design method.

II. DESIGN OF THE POWER STACK
The proposed power stack comprises a DC busbar, DC link capacitors, IGBTs, a gate driver, a heat sink, a POB, and a ferromagnetic-metal housing. The exploded view of this stack is presented in Fig. 2. Because limited energy is required by the designed power stack in the DPT method, the DC link capacitors are regarded as ideal voltage sources, with each capacitor providing the same current for testing in the DPT. Therefore, the stray inductances from the DC busbar, IGBTs, and POB ( Fig. 3) are major factors influencing the static current balancing of IGBT modules connected in parallel. Design results indicated that the POB is the main part to be modified for ensuring that the stray inductances are the same.  The design procedure for the proposed power stack is displayed in Fig. 4. First, IGBT module, gate driver and DC link capacitors are selected according to requirements. Subsequently, Q3D is employed to analyze the stray inductance of the IGBT modules as a design basis for the laminated DC busbar and POB. Moreover, the DC busbar and POB are designed and analyzed through cosimulation with Simplorer and Q3D to obtain nearly the same stray inductance for the three current paths from the DC link capacitors to the phase output terminal. If the MRICs for the three IGBT modules is within 3% under 200% rated current, then the designed power stack is constructed for performance verification; otherwise, the POB is redesigned.

A. SELECTION OF THE DC LINK CAPACITORS
Front-end AC-DC rectifier with a capacitor tank is widely used in high-power applications to provide the DC voltage required by multiple power stacks. This study analyzed the current sharing among IGBT modules connected in parallel.
The selection of DC link capacitors was based only on the specifications presented in Table 2. and the power requirement of the load [37], [38]. Moreover, the designed power stack was constructed to test its current balancing by the DPT method. Through the use of the aforementioned selection procedure, the capacitance of the DC link capacitors should be sufficient for the DPT method. The DC link voltage of an inverter is usually 1000-1100V in applications with a grid voltage of 690Vrms [39]- [41]. Therefore, the required capacitance of DC link capacitors for an inverter with three power stacks can be expressed as follows: : minimal DC link voltage Q : rated reactive power f : line frequency of the grid P : rated active power The capacitance of the DC link capacitors was calculated to be 20869μF by substituting the parameters presented in Table 2 in (1). The DC link capacitor for a single stack Cstack is one-third that for the inverter (i.e., Cstack is 6956μF). Film capacitors have been widely adopted in power stacks used in wind power generation because of their favorable performance at low temperatures, safety and robustness [34]. Therefore, the ELECTRONICON E50.R19-764NT1 film capacitor was adopted in this study. The total capacitance of a single stack Cstack comprising nine film capacitors with a rated voltage of 1300V each and a capacitance of 760μF each that are connected in parallel is 6840μF under an operating temperature range of 40~85 CC   .

B. GATE DRIVER
The adopted gate driver (Tamura 2DUC51008CML1), which contains an in-built isolated DC-DC converter and performs soft turn-off and desaturation, is used to drive the three IGBT modules (Fig. 5). The gate driver serves as a master and connects two expansion slave boards with similar matching impedances to drive the three IGBT modules simultaneously, the gate resistance Rg is 0.6Ω, turn on and off gate to emitter voltage are 15V (Vge_on) and -9.6V (Vge_off), respectively.

Slave control board
Slave control board FIGURE 5. Connection of the adopted gate driver to the three IGBT modules connected in parallel.

C. DETERMINATION OF THE STRAY INDUCTANCE FROM THE IGBT MODULES
The stray inductances of the IGBT modules were extracted using Q3D, which adopts the simplified flat copper bonding model of the IGBT module of Mitsubishi Electric that is displayed in Fig. 6. Moreover, the stray inductances belong to the dynamic and static current paths, which are shown in Fig. 7(a) and 7(b), respectively. The stray inductances in an IGBT module can be expressed as follows: Where Lσ_S and Lσ_D: total stray inductances of the static and dynamic current paths in the IGBT module, respectively. Lo: stray inductance between the phase terminal and the IGBT die. L1 and L2: stray inductances from DC+ to the die and from the die to the Lo of the high-side IGBT die, respectively. L3 and L4: stray inductances from Lo to the die and from the die to the DC− of the low-side IGBT die, respectively. M : mutual inductance between (L1, L2) and (L3, L4) under the assumption that the bonding wire is symmetrical in the highand low-side IGBTs in the IGBT module.

Connect to phase output
Connect to DC-Connect to DC+ Fig. 8 displays the simulated results obtained using Q3D for the stray inductance. A dynamic path enables magnetic flux canceling because of the wire-bonding structure; therefore, Lσ_D is smaller than Lσ_S. The simulated values of Lσ_D and Lσ_S were 12.5nH and 30.3nH, respectively, under a frequency of 1.25 kHz. The frequency of 1.25kHz represents the fundamental operating frequency of the first test pulse in the DPT Fig. 1(b). Moreover, the simulated parasitic resistance Rσ_S of static current path was 0.14mΩ. Because the Spice model could not be applied to the adopted IGBT modules, the simplified IGBT circuit [ Fig.  9(a)] was used to simulate the static current sharing among the IGBT modules for improving the design of the POB. The approximate turn-on saturation voltage of the low-side IGBT VCE(sat.) [18] is expressed as follows: Where VCE(0) and RX are the turn-on initial voltage and equivalent resistance of the low-side IGBT die used in the IGBT module, respectively. As shown in the die level output curve depicted in Fig. 9   6 VOLUME XX, 2020

D. DC BUSBAR DESIGN
Because of the usage of a high-voltage film capacitor and the need for cost reduction, a double-layer laminated busbar was selected for the designed power stack. To reduce the stray inductance of the DC busbar, the overlap area of the two layers should be as high as possible and the gap between the two layers [42] should be as low as possible under the consideration of safety regulations. The symmetrical connection of capacitors to the DC busbar can reduce the current imbalance [34], [43] among them. Moreover, the connections between capacitors and the DC busbar should have rounded edges for reducing the eddy current loss [34]. Fig. 10(a) depicts the shape and dimension of the designed DC busbar. The current flow starts from the positive terminals of the capacitors, passes through the positive layer to the load inductor, and moves from the POB to the negative layer through the negative terminal of the IGBT modules; finally, it returns to the negative terminals of the capacitors. Therefore, the magnetic field coupling effect occurs. This effect is induced by the current that flows between capacitors and IGBT modules. Consequently, the following assumptions were made in the adopted stray inductance simulation method [ Fig. 10(b)]: 1) The DC link capacitors are ideal.
2) The DC busbar can provide balanced current to the three IGBT modules.
3) The connection between the capacitor and the DC busbar can be regarded as a short circuit. On the basis of the aforementioned assumptions, the DC link capacitors can be regarded as ideal voltage sources, with each capacitor providing the same current. Therefore, the terminals of these capacitors can be set as short circuits during the simulation. In the cosimulation conducted with Simplorer and Q3D, the ideal current with a fixed slope increased from 0 to 2400A in 80μs for each current path. These currents were used for determining the stray inductances. The stray inductances of the three parallel paths in the DC busbar are expressed as follows:  . In this case, (5) can be simplified as follows: Where is the equivalent stray inductance in the DC busbar and is expressed as bx bx bx bx L L L L      The simulated values of Lb1, Lb2 and Lb3 were 22nH, 19nH, and 22nH, respectively. The parameter Lb2 is smaller than Lb1 and Lb3 because of the DC busbar structure and location of load inductor. The maximum difference among the stray inductances was only 3nH, which indicates that the DC busbar design and proposed stray inductance simulation method were effective for achieving near-equal stray inductances among the three current flow paths.

E. POB DESIGN
A T-type POB, which is an improvement over the traditional POB, was designed using Q3D to connect and enable satisfactory current sharing among the three IGBT modules. Fig. 12 presents the structures of the traditional and proposed POB. According to the current flow, the aforementioned POBs can be divided into two parts: the convergence and common parts. The convergence part is used to merge the three IGBT module currents. In Fig. 12, the red, blue, and green paths correspond to the current paths of IGBT 1, IGBT 2, and IGBT 3, respectively. Because the blue path (IGBT 2) of the traditional POB is the shortest path to the load inductance in Fig. 12(a), this path has the lowest stray inductance. This finding is in line with the results of the DC busbar simulation. The proposed POB [ Fig. 12(b)] contains a polygonal hollow part for adjusting its stray inductances. Moreover, it compensates for the stray inductance of path 2 (blue path) of the DC busbar. The common part of the aforementioned two POBs is used for conducting current with the same stray inductance; therefore, this part has no influence on the current balancing and can be regarded as part of the load inductor. Consequently, the polygonal hollow part is the only part that affects the current balancing.  The design procedure for the proposed POB (Fig. 13) is described as follows:

1) STEP1: DESIGN THE SIZE OF THE POB
Because the stray inductances are varied by changing the hollow area, the convergence part of the proposed POB is larger than that of the traditional POB.

2) STEP2: DETERMINE THE LENGTH (L) AND WIDTH (W)
The maximum ratio of inductance difference (MRID) and average inductance LPOBC(Avg.) of the convergence part can be defined as follows:  (8) where LPOBC,1, LPOBC,2 and LPOBC,3 are the equivalent stray inductances of the proposed convergence part along three paths.
Step 1 Step 2 Step 3 Common part Fig. 14 displays the simulated results for the relationship among the length (L), width (W), and MRID of the convergence part. The MRID can be minimized by adjusting the hollow dimensions under the assumption that the inductances of paths 1 and 3 in the convergence part are nearly the same because of the symmetrical structure of this part. The simulation results indicated that the smallest MRID is less than 2% in the area where L is greater than 140mm and W is approximately 10-15mm. Because the shape of the POB can be easily adjusted for obtaining the required stray inductances which compared with 20nH average value of the DC busbar, the stray inductance of the convergence part dominates the adjustment of all the stray inductances.

3) STEP3: FINE-TURN THE PROPOSED POB
To compensate for the low stray inductance along current path 2 of the DC busbar, the rectangular area A in Fig. 13 is removed. In addition, the triangular area B is removed to reduce the weight of the POB without affecting the required stray inductance. The stray inductances simulated method of the POB and DC busbar was similar (Fig. 16). The current sources exhibited a constant-current-slope of 2400A/80μs for testing the convergence part and entire POB. The simulation results of the traditional and proposed POBs are presented in Table 3, which indicates that the stray inductances of the proposed convergence part are closer and larger than those of the traditional POB. The simulated stray inductances of the common parts of the proposed and traditional POBs were near 106nH and 102nH, respectively. Moreover, the stray inductance of the proposed convergence part along path 2 was marginally higher than those along paths 1 and 3 for compensating for the stray inductance in the DC busbar.

III. COSIMULATION OF THE STATIC IMBALANCED CURRENT OF THE DESIGNED POWER STACK
For further analyzing the current balancing, cosimulation was conducted using Simplorer and Q3D to predict the current distribution among the IGBT modules and examine the validity of the aforementioned stray inductance and current balancing estimations. Fig. 17 shows the cosimulation setup of the power stack in the DPT. The parameters and settings of the cosimulation environment are listed as follows: 1) The DC source voltage VDC was 1000V.
2) The nine film capacitors had the same electric parameters, and these capacitors, including their ESR and ESL, were connected one-by-one to the nine connectors of the DC busbar that was constructed using Q3D. 3) Because the Spice model of the IGBT modules was not available, the high-side IGBT was assumed to be always off and the low-side IGBT was assumed to be driven by an ideal gate driver in the DPT. Moreover, the relationship between the turn-on voltage VCE(sat.) of the low-side IGBT and the current was determined using (4) to simulate the behavior of this IGBT. 4) The simulated results of two types of POBs, namely the traditional and proposed POBs, were compared. 5) The output signal of the gate driver was ideal, and the signal sequence comprised two on-off cycles with on and off periods of 40μs each. 6) The maximal current of the IGBT modules in the DPT was 200% rated current; thus, the total output current was 7200A for the three IGBT modules, with each IGBT having a rated current of 1200A. The required load inductance was calculated to be 9.5μH by considering a VDC of 1000V, which was also assumed to be the voltage drop of the resistance; a maximal current of 7200A; and the signal sequence of gate driver. Moreover, the inductive load was replaced by a RL series circuit in the cosimulation to neglect the magnetic coupling effect induced by the load inductor. 7) Cosimulation was conducted using Simplorer and Q3D to consider the proximity effect caused by various currents along each path of the POB. Fig. 18 displays the simulated current sharing results for the designed power stack in the traditional and proposed POBs. The inferences drawn from the simulation results are as follows: 1) Because path 2 of the traditional POB exhibited the lowest stray inductance (Table. 3), the peak current of this path (ipeak,2) was larger than those of the other two paths (ipeak,1 and ipeak,3), which were equal. 2) Similarly, ipeak,2 was smaller than the other two peak currents because path 2 had highest stray inductance, with ipeak,1 being equal to ipeak,3 for the proposed POB.   The MRIC can be defined as follows: . (%) . 100 where ipeak,k is the peak current of the IGBT module along path k and ipeak(Avg.) is average peak current of the three IGBTs. The MRIC of the traditional and proposed POBs were 5.9% and 0.8%, respectively, and the and maximal current difference (MCD) of these POBs were 216 and 30A, respectively. These results indicate that the proposed POB enabled better current sharing among the IGBT modules than did the traditional POB. Fig. 19 shows the cosimulation results of current sharing in the power stack in the proposed POB when only considering the convergence part. The three path currents displayed in Fig. 19 are close to those depicted in Fig. 18(b), which indicates that the common part of the POBs had no influence on current sharing. Fig. 20 depicts the stray inductance distribution presented in Table 4. Table 4 summarizes the stray inductances of the DC busbar, IGBT modules, and convergence part of the POB along the three static current flow paths in the designed power stack. The following phenomena can be observed from

A. VERIFICATION OF IGBT MODULE INDUCTANCE
The test circuit was based on the DPT, and the measurements were based on the equivalent circuits of the IGBT modules depicted in Fig. 9. Therefore, the lower-arm voltage of the IGBT modules in the DPT is expressed as follows: To increase the measurement accuracy and considered voltage drop, a DC link voltage of 30V and load inductance of 0.68μH were selected for achieving a constant-currentslope (i.e., dic(t)/dt=35.1A/μs) during calculation period 5.7μs as shown in Fig. 22. The achieved current slope was equivalent to that of a 1000V DC link voltage with a 9.5μH inductor. Therefore, a voltage probe with a 10:1 attenuation was adopted to measure the IGBT voltage VCE(module). This probe provides a higher accuracy than does that with an attenuation of 100:1. The measured waveforms of the lowside IGBT voltage VCE(module) and current ic are illustrated in Fig. 22

B. VERIFICATION OF POB INDUCTANCE
The verification method for the stray inductances in the POB is similar to the inductance extraction in (6). However, in contrast to the simulation, the manufactured POB is an integrated structure and cannot be separated into the convergence and common parts in practice. Therefore, the measured waveforms of the entire POB (Fig. 23) and the measurement setup are the same as those depicted in Fig.  16(b). To reduce the influence of resistances in the POB and measured error caused by high current, the DC voltage is set as 300V to let the peak current be less than 400A in each current path. The measured and simulated stray inductances are listed in Table 5. The maximal error between the simulation and experimental results is less than 3.1%, which indicates a satisfactory match between the cosimulation and measurement results.  .

 
The parameters LPOBE,1, LPOBE,2 and LPOBE,3 denote the entire stray inductances of the proposed POB along paths 1, 2, and 3, respectively. Table 6 and Fig. 24 present the experimental results for the three IGBT modules and a comparison between the simulation and experimental results of these modules, respectively. The following inferences can be drawn from the results presented in Table 6: 1) The simulated and experimental MRIC and MCD of the proposed POB were smaller than those of the traditional POB. Moreover, the proposed POB met the design criterion of the MRIC being less than 3%. The simulated and experimental MRIC values of the proposed POB were 0.8% and 0.9%, respectively. In the experiment, the MCD decreased from 161 to 38A when the traditional POB was replaced with the proposed POB. Such a decrease in the MCD can reduce the derating current of the three IGBT modules. 2) The proposed design method of POB can improve current sharing from simulation results as shown in Fig.  18, which are also good match with experimental results. Possibly because the proximity effect on the three IGBT modules was considered in the experiment, which resulted in an increase in the impedance of IGBT 2 for reducing the current along path 2.  Notably, the method of wiring the load inductor in the DPT affects the test results. Fig. 25(a) indicates that the imbalance currents of the IGBTs increased when the wiring of the load inductor was parallel to the POB. Therefore, the wiring of the load inductor must be perpendicular to the POB and DC busbar during the DPT, as depicted in Fig.  25(b), to reduce the effect of electromagnetic coupling on current sharing. In order to keep the maximum current less than 2400A in each IGBT module under serious EM coupling condition, VDC is adjusted to 800V.

V. CONCLUSION
In this study, a power stack with equal stray inductances along the static current flow paths in three IGBT modules connected in parallel was developed. Moreover, a cosimulation was conducted with Simplorer and Q3D to guide the design of a DC busbar and POB for achieving current balancing among the three IGBT modules. A power stack with a DC link voltage of 1000V and a maximal output current of 7200A was constructed and tested using the DPT to verify the effectiveness of the design. The main contributions and conclusions of this study are as follows: 1) The current in the IGBT modules was defined as static or dynamic in the DPT. The results of the DPT confirmed that the static current balancing among IGBT modules is mainly affected by the DC busbar, IGBT modules, and POB in the power stack. 2) A method is proposed for measuring the stray inductance along static current flow paths in the IGBT modules to verify the results simulated using a simplified model. The measured and simulated stray inductances were 36.5nH and 30.3nH, respectively. Although the measured value was larger than the simulated value, the simulation results were reasonable because the simulation was conducted using a simplified flat copper wiring model rather than a multiple wire-bonding model for the IGBT modules. 3) A design procedure is proposed for achieving suitable current sharing among IGBT modules connected in parallel. The DC busbar and POB were designed through cosimulation with Simplorer and Q3D to enable each stray inductance along the three static current paths to be nearly equal for achieving static current balancing. The stray inductances could be varied effectively by changing the shape of the hollow part in the proposed POB. The proposed POB exhibited almost identical stray inductance along the three current paths in the simulation. 4) The simulated and experimental MRIC and MCD of the power stack with proposed POB were smaller than those of traditional POB. Moreover, the proposed POB met the design criterion of the MRIC being less than 3%. The simulated and experimental MRIC values of the proposed POB were 0.8% and 0.9%, respectively. In the experiment, the MCD decreased from 161A to 38A when the traditional POB was replaced with the proposed POB. The almost-equal stray inductances along the three static current flow paths in the proposed POB enabled satisfactory current balancing to be achieved among the three IGBT modules.