Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF

This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for C<sub>L</sub> = 0 and under 60 mV for <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\mathrm {L}} =1\,\,\mu \text{F}$ </tex-math></inline-formula>, when the load current varies between 1 <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> and 100 mA in 1 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>. The LDO requires only 6.2 <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> of quiescent current and occupies 0.018 mm<sup>2</sup> of die area.


I. INTRODUCTION
A standard LDO consists of an error amplifier (EA) that drives a PMOS or PNP pass transistor, and a passive feedback network, as shown in Fig.1(a). Its frequency characteristics are largely determined by two poles: the first is associated with the gate of the pass transistor, while the second is associated with the LDO output node. The latter depends on the load current, I L , and load capacitor, C L . Therefore, the wider the ranges of C L and I L values that need to be accommodated, the more difficult it is to ensure the LDO stability. A typical solution is to employ a Miller-type polesplitting frequency compensation. However, this approach The associate editor coordinating the review of this manuscript and approving it for publication was Mostafa Rahimi Azghadi . reduces the gain-bandwidth product (GBW) of the LDO, impairing its dynamic performance. Fig.1(b). shows the typical LDO response to steep variations of the load current: as I L increases, the output voltage decreases sharply; it takes the time t 1 for the feedback loop to arrest the decrease and start bringing V OUT back to its steady-state value. A similar scenario is shown when I L decreases sharply, only this time V OUT increases for the period t 2 , before the loop starts correcting the V OUT variation. The maximum variation of the output voltage, V undershoot/overshoot , and the periods t 1 , t 2 can be approximated as follows [1]: GATE_sr2 (2) C GATE ∼ = G GS + A v,pass * C GD (3) where BW cl is the closed loop bandwidth of the system, t sr is the slew-rate time -the time needed to charge/discharge the parasitic gate capacitance of the pass element, V GATE is the voltage variation at the gate of the pass transistor and I GATE_sr is the maximum current available to discharge and charge the capacitance C GATE at that node GATE, A v,pass is the voltage gain of the Mpass and C GS , C GD are the gate-source and gate-drain capacitances of the pass transistor. Equations (1) and (2) show that by increasing the I GATE_sr current, the overshoot/undershoot of the regulated voltage can be reduced. However, this usually comes at a cost in quiescent current.
Most solutions proposed in the literature for speeding up the LDO response to load transients employ an additional feedback loop, connected directly between the LDO output and the gate of the pass transistor, as illustrated in Fig.1(a) by the dotted line rectangle. This second feedback path improves the transient response of the LDO, otherwise limited by the GBW of the main loop [2].
In [2], a capacitor is connected between the LDO output and the source of a cascode, so that the output voltage variations are sensed and converted into a current signal, which is then amplified and conveyed to the gate of the pass transistor. This fast path increases momentarily the I GATE_sr current available to discharge the parasitic gate capacitance. However, the output voltage overshoot remains relatively large and the maximum C L value the LDO proposed in [2] is stable for, is only 100 pF. The solutions proposed in [3] and [4] use operational transconductor amplifiers with enhanced slew rate and adaptive biasing; they require less quiescent current and are more effective in reducing the output voltage overshoot than the LDO proposed in [2], but they, too, cannot handle load capacitors larger than 100 pF.
LDOs designed to operate with external capacitors usually have a narrow closed-loop bandwidth, and rely on the charge accumulated by the C L , usually with values in the µF -tens of µF range, to reduce the output voltage variations caused by steep load transients. The C L Equivalent Series Resistance (ESR) diminishes the effectiveness of this approach, but it may help improve the stability of LDO. Moreover, the impact a large decoupling capacitor can have on reducing the variation in the voltage delivered to a load located inside the IC is further diminished by the parasitic series inductance and resistance of the track between the internal load and the external C L .
The need for LDOs able to handle a wide range of load currents and capacitors, while providing a fast response to load transients, has been increasing steadily. Analog Devices registered the term anyCAP as a trademark and provides LDOs that ensure stability for all types of external capacitors and over a wide range of C L values [5]. The LDO proposed in [6] uses an EA based on the flippedvoltage-follower structure, with a slew rate enhancement technique for fast transient response, and a feed-forward frequency compensation network that ensures stability for C L values up to 2 nF. However, it requires a large quiescent current, between 50 µA and 190 µA. The LDOs proposed in [1] and [7] rely on pole-zero cancellation realized by a parallel amplifier structure, or by a modified pass element with several transistors connected in parallel. However, the quiescent currents required by these rather complex structures are also large.
The topology of the LDO proposed in this paper is similar to the ones described above, but the local feedback is implemented by a novel circuit, which ensures both a fast response to load transients and the LDO stability for practically any load capacitance. This circuit is combined with an EA with enhanced slew-rate to obtain a compact LDO, suitable for low quiescent current operation and a small die footprint. These are presented in Section II, along with an intuitive small-signal analysis of the resulting LDO, which yields the key sizing equations.
Section III presents a design example: the proposed LDO was integrated in a 130 nm standard CMOS technology; simulation and measurement results prove that the design can handle capacitive loads up to tens of µF, exhibits small output voltage overshoots and undershoots when I L varies between 1 µA and 100 mA in 1 µs, while its quiescent current is just over 6 µA. This section also comprises a comprehensive comparison with state-of-the-art. Conclusions are drawn in the last Section.  Fig. 1(a) but highlights the fact that the additional local feedback created between the LDO output and its pass transistor is used to ensure both a fast response to load transients and an effective frequency compensation. A circuit that achieves these goals is presented in Fig. 2(b).: capacitors C1 and C2 are connected between the LDO output and the sources of transistors MyN and MyP, respectively. In steady-state operation, the potentials at these sources are set by the voltage drops across resistors Rn and Rp, caused by a current derived from the bias current Idc by the cascoded current mirrors M5-M6, MxN-MyN-Rn and M7-M8, MxN-MyN-Rp. Let us assume that, starting from a stable operating point, the output voltage decreases fast due to a sudden increase in the load current. The main feedback loop, that includes the EA, needs time to react but the output voltage variation is conveyed immediately by capacitor C1 to the source of MyN. Thus, the potential of node N is pushed down fast, and it can go below the GND rail. Therefore, the gate-source voltage of  MyN increases quickly, causing a dramatic increase of its drain current. Similarly, as the output voltage decreases, the node P is pulled down, but this results in the source-gate voltage of transistor MyP being shrunk. Therefore, the current injected into the node GATE by MyP decreases, while the current sunk from that node by transistor MyN increases. The combined effect is to pull down the gate of the PMOS pass transistor, so that it sources more current into the load, which in turn arrests the decrease of the output voltage. Conversely, when the output voltage increases due to a sudden decrease of the load current, the circuit shown in Fig. 2(b). injects more current into the GATE. As the gate voltage of Mpass increases its source-gate voltage shrinks, resulting in a drastic decrease of the current it sources into the load. This prevents the output voltage from increasing any further.
The cascodes M6 and M8 help increase the output impedance of the fast transient and frequency compensation circuit so that it does not significantly impact the equivalent small-signal resistance between nodes GATE and GND, hence neither the gain of the main voltage-control feedback loop.
The voltages at nodes P and N can go outside the supply rails, but the circuit can be sized so that this does not result in SOA violations. This is demonstrated in Fig. 3, where the voltages at nodes P and N go above, respectively below the corresponding supply line but only by 81mV and 168mV. Fig. 3 provides a direct comparison of the transient response to a load current step between an ordinary LDO before and after inserting the fast transient circuit shown in Fig. 2(b). When using the additional circuit, a larger current is injected and sunk into and from the gate of the pass transistor, which leads to a faster reaction of the LDO to variations of the output voltage. This behaviour can be seen in Fig. 3, and is consistent with (1) and (2): as t is reduced by adding in the fast transient circuit, the output voltage overshoot and undershoot are also reduced. The faster settling time is also worth noticing.
To conclude, the circuit presented in Fig. 2(b) reacts very fast to variations of the LDO output voltage, driving the gate of Mpass so that the Vout variations are arrested quickly, well before the main feedback loop can react. This way, both the output voltage undershoot and overshoot are diminished.
In steady-state operation, the circuit shown in Fig. 2(b) implements a parallel-parallel inner feedback loop that helps reduce the impedance at the LDO output. In turn, this reduces the impact the pole associated with the output node, which also depends on the load capacitance, C L , has on the LDO stability. Section II.C explains in detail the impact of this circuit on the loop frequency characteristics.

B. AN EFFICIENT CIRCUIT IMPLEMENTATION 1) ERROR AMPLIFIER WITH HIGH SLEW RATE
The operational transconductance amplifier (OTA) shown in Fig. 4 employs a recycled folded cascode topology [8] and adaptive biasing to achieve large values for the low-frequency gain and slew rate (SR) [4].
The input stage is formed by two pairs of matched crosscoupled transistors, M1a-M1b and M2a-M2b, and two levelshifters, M13a and M13b, and operates in class AB [9]. Assuming that transistors M1a, M1b, M2a, M2b, M13a, M13b work in the saturation region, the output current is a 4 th order function of the differential input voltage, Vid = V InP -V InM [4]: where β = µC ox W L is the transconductance factor and I cm = (I 2a + I 2b )/2.
Thus, this OTA is well suited to implement the error amplifier depicted in Fig. 2(a).: the current that charges or discharges the gate capacitance of the pass transistor can easily reach values well above the quiescent current -effectively boosting the equivalent slew-rate of this circuit.
However, a complicated and somewhat unwieldy LDO, that requires considerable quiescent current and die area, results if one simply inserts the schematics presented in Fig. 2(b). and Fig. 4 into the LDO block diagram shown in Fig. 2(a).  By analysing the three schematics mentioned above, one notices that in Fig. 5 the Ft&Fc circuit is implemented by adding only passive elements -C1, C2, Rp and Rn1, Rn2, drawn in blue in Fig. 5 -to the OTA shown in Fig. 4. All MOS transistors within the Ft&Fc circuit shown in Fig. 2 -drawn in red in Fig. 5 -are obtained by assigning dual function to several transistors within the initial OTA. This way, the Ft&Fc circuit does not require additional quiescent current, and the die area increase is minimized C. SMALL SIGNAL ANALYSIS Fig. 6(a) presents a simplified small-signal representation of the circuit shown in Fig. 5, in unity-gain configuration (FB node connected directly to OUT node). Here is a brief description: -G mEA is the transconductance of the EA OTA, with the noninverting input connected directly to the LDO output. Its internal pole, due to the pair of nodes denoted A and B in Fig. 5, has to be considered; let its angular frequency be ω pEA ; VOLUME 10, 2022  -G mPASS is the transconductance of the pass transistor, Mpass; -G mFB1 is the transconductance of the section of the local feedback implemented by the Ft&Fc circuit that is connected to the LDO output through C1. It consists of M4yNb-M6 and Rn2. Its input impedance is represented by (1/G mFB1 ) || R n .
-G mFB2 is the transconductance of the local feedback implemented by the Ft&Fc circuit that is connected to the LDO output through C2. It consists of M10yP-M8 and Rp. Its input impedance is represented by (1/G mFB2 ) || R p .
-R G || C G represents the small-signal impedance between the nodes denoted GATE and GND in Fig. 5, while R L || C L is the small-signal impedance between nodes OUT and GND.
Brute-force analysis of the small-signal equivalent of the circuit shown in Fig. 6(a) yields the loop gain expression detailed in (5), as shown at the bottom of the page. Such a complex, high-order expression is awkward to use by the circuit designer. To reduce it to a two-real-poles-and-onezero expression similar to Ahuja's [10] (also simplified) loop gain expression requires a lot of creative algebra and a series of approximations, which in turn are valid only if several sizing conditions are imposed. This algebra-driven approach is not conducive to an intuitive understanding of the design constraints and sizing equation required by a circuit designer.
Instead, we developed a version of the approximate graphical analysis method introduced in [11] and [12], and developed in [13]. Its main points are: -a circuit with multiple feedback loops can be simplified iteratively, starting from the inner loop and moving outwards. At each step, the section enclosed by the inner-most feedback loop is replaced by its closed loop equivalent, yielded by the classical feedback theory. In this way, one eventually obtains an equivalent circuit with only one feedback loop, whose stability is easier to analyse.
-if the final equivalent circuit, as well as the sections obtained at each step of topological transformation, meet the usual stability criteria, the entire circuit is stable.
-focus the analysis on the narrow frequency range around the unity-gain frequency of each loop-gain, rather than the loop-gain expressions over the entire frequency range.
By making the two sections of the local feedback implemented by the Ft&Fc circuit symmetrical, that is: the small-signal representation of the circuit shown in Fig. 5 can be reduced to the schematic presented in Fig. 6(b). This highlights the two distinct feedback loops within the LDO: the main one, that comprises the EA, and the inner one, formed by the Ft&Fc circuit. The latter closes parallel-parallel feedback around the pass transistor; thus, the ensemble can be represented by a single block, as shown in Fig. 6(c). Its transfer function, corresponding to the parallelparallel feedback topology, is the transimpedance Z t INNER , whose expression results simply from the classical feedback theory: where LG INNER is the loop gain of the inner loop and a INNER and f INNER are the open loop gain and the feedback transmittance of the inner loop, respectively: As LG INNER = a INNER f INNER , one obtains: The loop gain of the entire LDO results by analysing Fig. 6(c): LG LDO (13) For the LDO to be stable, the inner feedback circuit shown in Fig. 6(c) must be stable, as well. Therefore, one needs to analyse both LG INNER and LG LDO . For this, we will use an intuitive method based on approximate representations of the module frequency characteristics of the two loop gains, considering all relevant combinations of load current (which determines G mPASS and R L ) and load capacitance values.
To ensure a proper phase margin for both feedback loops, let us set two general requirements: i). the magnitude characteristic of LG INNER should cross the 0 dB horizontal with a −20 dB/dec slope; ii). The unity-gain angular frequency, ω u , of the |LG LDO | frequency characteristic should occur more than a decade below ω pEA . In other words, this internal pole of the EA ought to be sized so that it is always beyond ω u . Fig. 7(a) presents the magnitude frequency characteristics of the two loop gains derived by using , when I L is close to the maximum value, I L_MAX , while C L is relatively small, so that R L C L < R G C G .

1) ANALYSIS OF THE INNER LOOP GAIN, LG INNER
The frequency characteristics of LG INNER are determined by a zero placed in the origin, two main poles associated with the GATE and OUT nodes, ω G = 1 R G C G < ω L = 1 R L C L in this case, and a third pole introduced by the Ft&Fc circuit -as described by (10). It crosses the 0 dB horizontal with a −20 dB/dec slope if its unity gain angular frequency, ω u2 , is no larger than the angular frequency of the third pole: This can be ensured by setting the following constraint on the maximum value of the inner loop gain: As the load current decreases, the equivalent small-signal resistance at the OUT node, R L , increases, while G mPASS decreases. Also, at very light load, the gate of the pass transistor rises, which pushes the Pmos cascoded mirror of the EA into the linear region. As a result, the total gain of the LDO decreases. This scenario is illustrated in Fig. 7(b): the pole associated with the OUT node moves to a lower angular frequency, ω * L ; concurrently, the level of the LG INNER plateau decreases, pulling the unity-gain frequency lower, down to ω * u2 , while the first zero-crossing occurs at a higher angular frequency, ω * u1 . As long as |LG INNER | max > 0 dB and ω G remains the dominant pole, (15) yields: For R 1 G mFB one can approximate R|| 1 G mFB ∼ = R. Therefore, (16) can be rewritten as follows: Let us now analyse the LDO loop gain for the case shown in Fig. 7(a). Equations (12) and (13) indicate that: -for ω < ω u1 and ω > ω u2 the LDO loop gain is approximated by the product G mEA a INNER -for ω u1 < ω < ω u2 the LG LDO follows G mEA 1 f INNER Therefore, the LG LDO dominant and secondary poles are set by the zero-crossing points of the |LG INNER | characteristic: In this case, we can provide for the LG LDO magnitude frequency characteristic to cross the 0 dB horizontal with a slope of −20 dB/dec by setting the following condition: Furthermore, the unity gain frequency of the LDO loop gain, ω u , can be found at the intersection of the G mEA 1 f INNER frequency characteristic with the 0 dB horizontal: The ω u value is close to ω pEA but in this case the LDO stability is ensured by condition (19). For the scenario depicted in Fig. 7(b), the dominant pole of |LG LDO | moves up in frequency, while its secondary pole moves down, to ω * dp = ω * u1 and ω * sp = ω * u2 , respectively. Although the low-frequency gain decreases, the 0 dB-crossing occurs after the secondary pole, ω * sp < ω * u . However, the LDO remains stable because the unity-gain frequency is far lower than in the previous case, shown in Fig. 7(a), while the parasitic pole of the G mEA , ω pEA , does not move. The LDO phase margin depends mainly on the distance between ω * u and ω * sp , which becomes an important design constraint. Fig. 8 illustrates four real-life cases for the LG INNER and LG LDO : the load current is kept constant at a normal operating level, I L_MIN < I L < I L_MAX , while the load capacitance takes four values C La < C Lb < C Lc < C Ld , from near-zero to very large values, in the µF to tens of µF range. Fig. 8(a) shows the case of a load capacitance value, C La , relatively small, such that R L C La < R G C G . This is similar to the case shown in Fig. 7(b), except for the higher level of the |LG INNER | plateau. As the value of C L increases, the secondary pole of the |LG INNER | characteristic, ω L = 1 R L C L , moves towards lower frequencies, dragging with it the second zero-crossing point of that characteristic, ω u2 a ; this ensures the stability of the inner loop. According to (18), this forces the secondary pole of |LG LDO | to move to a lower 9130 VOLUME 10, 2022 frequency, while its main pole does not change position. Therefore, the |LG LDO | characteristic crosses the 0dB axis after the secondary pole, ω sp a < ω u a . As the distance between the main |LG LDO | poles decreases, so does the LDO phase margin. This situation is similar to, but slightly better than, the one shown in Fig. 7(b), because here the dominant pole does not move. Therefore, the LDO stability is ensured by the same factors: the unity-gain angular frequency decreases, while the G mEA parasitic pole does not move, thus ω u a ω pEA . The value of the LDO phase margin is set by the distance between these poles, i.e. the ratios ω ua ω sp a and ω ua ω pEA . As the load capacitance increases further, the LG INNER pole associated with the OUT node moves to even lower frequencies; for the load value C Lb , it reaches the position of the pole associated with the GATE node, ω G = ω L b . The frequency characteristics for this case are shown in Fig. 8(b). With respect to LDO stability, the situation is worse than the one presented in Fig. 8(a): as the second pole of |LG LDO | moves down in frequency, the distance between it and the dominant pole, which remains fixed, decreases. In turn, this results in a larger distance between the second pole and the zero-crossing point, , thus resulting in a smaller phase margin.
However, the phase margin remains positive as long as and its actual value can be adjusted through appropriate sizing.
By further increasing the load capacitance to C Lc , one obtains the frequency characteristics depicted in Fig. 8(c): for the |LG INNER | characteristic, the pole associated with the OUT node becomes the dominant pole, exceeding the pole associated with the GATE node, while its second zero-crossing frequency decreases further, ω u2 c < ω u2 b , albeit at a slower pace than in the previous case. Therefore, the secondary pole of the |LG LDO | characteristic moves to lower frequencies, while the other two poles maintain their positions. In this case, by reiterating (14), the constraint set on the maximum value of the inner loop gain becomes: which leads to: The situation is similar to the case illustrated in Fig. 8(b), with two differences: the plateau of the |LG INNER | characteristic is a function of C L now and gets smaller than in the previous cases, and the distances between the |LG LDO | zerocrossing point and the second and third poles are slighlty larger. It follows that the LDO phase margin may be a bit smaller but remains positive.
The level of the |LG INNER | plateau decreases as the load capacitance increases further, eventually reaching values below 0 dB, as shown in Fig. 8(d). In this case, the main poles of the |LG LDO | characteristic are mainly determined by the first two poles of the |LG INNER | characteristic, Therefore, as C L increases, the dominant pole moves to lower frequencies, while the second pole maintains its position. The zero-crossing frequency of |LG LDO | decreases, but it gets closer to the second pole, ω sp d .
Therefore, the LDO phase margin increases.
To conclude, for all cases analysed here the LDO phase margin remains positive; the circuit can be sized in order to ensure that the LDO phase margin remains above a minimum allowed value. The circuit sizing should be optimized for the case illustrated in Fig. 8(c), by taking into account (17) and (23), equations that can be rewritten as follows: This makes the approach to the analysis of multiple-loop LDOs more effective and useful to the circuit designer than [10] and [14].

III. DESIGN EXAMPLE A. LDO DESIGN REQUIREMENTS AND SIZING STARTEGY
The LDO introduced in the previous Section, with the schematic shown in Fig. 5, was used to implement a regulator for an SoC integrated in a standard 130 nm CMOS process. Multiple instances of this LDO are used for various digital sections within the SoC, so it has to cater for a wide range of loads. This led to the following set of design requirements: -Vout = 1 V, when supply voltage varies between 1.2 V to 1.5 V and I L varies between 1 µA and 100 mA; -maximum Vdrop = 100 mV; max quiescent current = 7 µA; -the LDO stability should be ensured for I L varying from 1 µA to 100mA and C L ranging from 0 to at least 1 µF, and irrespective of the ESR of C L .
-output voltage undershoot/overshoot when I L steps up from 1 µA to 100 mA in 1 µs, then back: no more than +/− 20% of nominal value, so that the difference Vout_max -Vout_min remains smaller than 400mVpkpk.
-PSR of at least 50 dB at 10 kHz for mid-range load currents, and better than 30 dB at full load, over the entire C L range.
-design and integrate in a standard 130 nm CMOS process.
-due to the die size limitations, the total value of on-chip capacitors (C 1 , C 2 ) should be maintained to less than 100 pF. As such, we propose the following sizing strategy for the frequency compensation circuit to meet these demands for the LDO stability.  Step 1: Size the pass transistor according to the dropout requirement and estimate the total gate parasitic capacitance, C G , at node GATE of the pass transistor.
Step 2: Size the remaining transistors in order to obtain the desired open loop DC gain given by (12), considering precision and PSR. This should follow the common design strategy (distribute the quiescent current for each circuit branch, bias the transistors in saturation etc.). Therefore, this step is not expanded in further details.
Step 3: By running parametric sims, find the I L and C L values for which the LDO without the frequency compensation circuit has a phase margin smaller than required. In our case, this resulted in the values shown with dark red in Fig. 9. Notice that no C L value can ensure the LDO stability over the entire range of load currents.
Step 4: From (24) find the RC value for which the frequency compensation covers the values of I L & C L found at Step 3 -the area delimited by the upper ( C G C L G mFB G mPASS ) and lower (max 3D representation of (24) is shown in Fig. 10, followed by a top-view of the same, Fig. 11.
Step 5: For the RC value obtained at the previous step, choose the values for R & C for which the dynamic response  of the Ft&Fc circuit is optimal (exhibits the highest output current). Testing the fast transient circuit part connected to the NMOS transistor resulted in a non-intuitive optimal value for R & C around 500 k & 100 pF, as shown in Fig. 12. For higher values for R the circuit exhibits less current. Given the RC value obtained at the previous step, aria constraints and voltage drop on R, a good tradeoff was to choose R = 10 k and C = 80 pF. The capacitance value will be split between C 1 and C 2 .
Step 6: Check the LDO Phase Margin for the values of R & C obtained at Step 5 and ensure that, for all combinations of I L & C L , the Phase Margin is greater than the minimum allowed value.

B. SIMULATION RESULTS
All results shown in this section were obtained by running simulations on netlists that included post-layout-extracted parasitics. Fig. 13 shows the frequency characteristics of the LDO loop gain for C L = 1 pF and two load currents:  I L = 1 µA, then 100 mA. For I L = 100 mA the simulated magnitude characteristics are similar to those approximated by Fig. 7(a): the first pole, ω dp , is placed around the first zero crossing of the |LG INNER |, while the second pole, ω sp , is placed at the second zero crossing of |LG INNER |, which occurs after the unity-gain frequency of the |LG LDO | -in this case 1.54 MHz. This results in a comfortable phase margin value, 89.71 • .
As indicated by Fig. 7(b)., for I L = 1 µA the |LG LDO | low-frequency value is significantly smaller than for I L = 100 mA; also, the first pole of |LG LDO | has moved up in frequency, while the second pole has moved to a lower frequency. Therefore, the LG LDO magnitude characteristic started decreasing with a −40 dB/dec slope before reaching its unity-gain frequency, of 594.1 kHz. This resulted in a substantially smaller phase margin value than the previous case, 23.28 • , but large enough to ensure the LDO stability.   Fig. 15 presents a similar set of simulations, but for the maximum load current, I L = 100 mA, and a smaller range of C L values:1 pF to 100 nF. Fig. 16 depicts the frequency characteristic of the LDO for the same maximum load current, but in this case the output capacitor takes values between 1 µF and 300 µF. Fig. 17 present the variation with C L of the LDO phase margin and gain margin corresponding to the simulations shown in Fig. 14, Fig. 15 and Fig. 16.
The simulation setup used to obtain the results shown in Fig. 14 corresponds to the cases presented in Fig. 8. As long as the C L values are small enough to satisfy condition R L C L < R G C G , the dominant pole is given by the first zero-crossing of |LG INNER | and only the secondary pole moves down in frequency as C L increases -this corresponds to the cases shown in Fig. 8(a) and (b). Therefore, the LDO phase margin decreases.
For larger C L values, for which R L C L > R G C G , the level of the inner loop gain plateau, |LG INNER | max , starts decreasing; the secondary pole continues to move down in frequency as C L increases, but by smaller amounts -see Fig. 8(c). As a result, the LDO phase margin degradation continues at a smaller pace, eventually reaching a minimum value, just over 8 • , for C L = 281 pF. For even larger C L values, |LG INNER | max starts decreasing such as it reaches below 0 dB. In this case, the |LG LDO | dominant pole starts moving to lower frequencies, while the secondary pole remains practically at the same frequency. This situation corresponds to the one illustrated by Fig. 8(d).: as the value of |LG INNER | max gets smaller than unity, the |LG LDO | dominant pole is given by the OUT node with the angular frequency inversely proportional to C L , while the secondary pole is determined by the GATE node. Therefore, the LDO phase and gain margin start increasing, and continue to do so as the C L value increases further. Note that for C L values larger than 100 nF, the phase margin stays above 60 degrees. This proves that at light loads the LDO remains stable for practically any value of the load capacitor.
For small C L values, that is, as long as R L C L < R G C G , the simulation setup used to obtain the results shown in Fig. 15 corresponds to the case illustrated in Fig. 7(a): the |LG LDO | characteristic crosses the 0 dB axis with a −20 dB/dec slope. As the value of C L increases, the secondary pole of the |LG LDO | characteristic moves towards lower frequencies, so that it occurs around the zero-crossing point of that characteristic. As C L increases furthermore, case shown in Fig. 16, the secondary pole of |LG LDO | moves down even more in frequency, so that it occurs above the 0 dB; this corresponds to the case shown in Fig. 8(a). From there on, the situation evolves similarly to the light-load case shown in Fig. 14: as the distance between the two |LG LDO | main poles decreases, so does the LDO phase margin, reaching a value slightly above 10 • for C L = 3.7 µF. For larger C L values the phase margin starts increasing. The pole associated with the OUT node moves down in frequency and becomes the dominant pole of the |LG LDO | characteristic.   1 µF; b). and c). I L = 100 mA, C L takes values between 1 pF to 100 nF, then between 1 µF to 300 µF. by comparing these results with their counterparts depicted in Fig. 9, obtained for a similar core LDO but without the Ft&Fc circuit. One notices that the proposed frequency compensation ensures the LDO stability over the entire range of I L and C L values, with double digit Phase Margin values for most cases, except for the small area highlighted at the top of Fig. 18.
There, the Phase Margin reaches its minimum value of 7 degrees, but exhaustive transient simulations confirmed that the LDO remains stable. It should be noted that the simulation results presented in both Fig. 9 and Fig. 18 were obtained for a particularly tough case with respect to the LDO stability: no track resistance and capacitors with ESR = 0 and ESL = 0.    Looking closely at Fig. 17(a) and (b), one notices that there are three worst cases regarding stability, where phase margin and gain margin take values below 10 • and 10 dB,  respectively. In Fig. 17(a) the minimum PM value is 8.2 • for C L = 281 pF and the smallest GM is 8.7 dB for C L = 91 pF. In Fig. 17(b) the worst case is for GM. The smallest value is found at C L = 19.35 nF and is 6.45 dB. The following figures, Fig. 20 and Fig. 21, illustrate the transient response of the LDO to a load current step for the worst cases described above. At t = 2 ms the load current jumps from 1 µA to 100 mA in 1 µs and at 2.04 ms back to 1 µA. The small ringing at the output voltage confirms that the LDO is stable even for PM and GM values smaller than 10 • and 10 dB, respectively.
The LDO output noise of the LDO for I L = 1mA and C L = 0 pF is shown in Fig. 22. Fig. 23 shows the LDO Power Supply Rejection (PSR) for the same load current and C L values between 1pF and 1µF.  Fig. 24 shows the die photographs of the proposed LDO integrated in a 130 nm CMOS test chip, with a zoomin that details the LDO floorplan. Most of its 0.018 mm 2 active area is occupied by the two capacitors within the Ft&Fc circuit, C 1 and C 2 . Therefore, the LDO area can be reduced substantially if high-density metal capacitors are available.

C. MEASUREMENTS RESULTS
The error amplifier is located separately from the pass transistor, so that it is not affected by the thermal gradients caused by the power MOS transistor.
The LDO was configured in a unity feedback structure as shown in Fig. 5, that is the worst case with respect to stability. Figures 25 -27 show the measured LDO response to load current jumps between 1 µA and 100 mA in 1 µs for three C L values: the response depicted in Fig. 25 was obtained for C L = 0; the one shown in Fig. 26 was obtained for C L = 91 pF, the value for which the LDO Gain Margin reached its minimum in Fig. 17(a); Fig. 27 depicts the load transient response for the maximum C L value, 1 µF. The test setup used for these measurements was similar to the one described in [13].
The output voltage overshoot/undershoot is 170 mV/ 234 mV without external load capacitor but decreases to 28 mV/58 mV for C L = 1 µF. Note that the slow output voltage recovery after an overshoot shown in Fig. 27 is due to the small current available I L = 1 µA to discharge the large C L = 1 µF. Fig. 28 shows the PSR frequency characteristic of the proposed LDO for the maximum load current, I L = 100mA, and three die temperatures: −40 • C, 25 • C and 150 • C. These 9136 VOLUME 10, 2022 measurements indicate that the LDO meets the PSR design requirement set in Section III.A. Fig. 29 and Fig. 30 present the LDO response to a 300mV line jump with the rise/fall time of 1 µs, measured for the same load current, 100 µA, and the extreme values for the load capacitor, respectively C L = 0 and C L = 1 µF. The output voltage overshoot and undershoot are quite small (20mV and 21mV) even for C L = 0, and are further reduced when a large external capacitor is used. The measurement shown in Fig.30 proves that the LDO is stable for the loading conditions (C L = 1 µF, I L = 100 µA) for which simulation results yielded a small Phase Margin value of less than 10 degrees. The settling time is longer for C L = 1 µF than for C L = 0, as expected considering the different Phase Margin values obtained for the two load capacitor values.
The measurement results presented here validate the design and prove that the proposed LDO meets the requirements set out in Section III.A. The circuit is able to operate without a placed decoupling capacitor, as well as with large, external load capacitors. For practical reasons, the maximum load capacitor employed here was 1 µF but the LDO can handle even larger loads, as indicated by Fig. 17(c).  -FOM1 proposed in [15] is effective for comparing LDOs with widely different values for the quiescent current, I q , load capacitance C L and load current: where V out_pkpk is the maximum output voltage variation (undershoot + overshoot) caused by the largest current load step the LDO can handle, range, I L = I L_max − I L_min . In general, the C L values used to calculate FOM1 were the ones for which the largest V out_pkpk was obtained. If that value was zero, C L = 1pF was used instead.
-FOM2 introduced in [16] is suitable for comparing capacitorless LDOs. It takes into account the rise/fall time of the load current step, which has a particularly large impact on the step response of LDOs that operate with no or only a small decoupling capacitor at their output. Also, it includes a process-dependent factor -FO4 Delay , the propagation delay of a standard CMOS invertor with fan-out of four -to obtain a process normalized FOM: where K = t used in measurement the smallest t among designs for comparison and I L is the amplitude of the load current step.
Let us now define a new figure of merit that takes into consideration two more features: the range of load capacitance the LDO can handle, and the slope of the load step the undershoot/overshoot was measured for, I L / t: where C Lmin is set to 1 pF for capacitorless LDOs. Note that FoM3 is dimensionless. For all three FOMs defined above, the smaller the value, the better the LDO transient performance. Table 1 summarizes the main parameters of the proposed LDO and eight other LDOs which reported similar levels of output voltage and current, and load capacitance values. These LDOs are integrated in different processes -from 65 nm to 0.5 µm -and their quiescent currents are very different -from just over 0.7 µA to over 200 µA. However, all of them can handle wide ranges of load capacitance, although the corresponding output voltage undershoots/overshoots caused by load transients are very different, as well.
References [6], [18] and [19] reported smaller values for the output voltage undershoots and overshoots than this work, but they used smaller load steps -from 0 A to 50 mA -and they required up to ten times more quiescent current than the LDO presented here. The second smallest quiescent current was reported by [21], but it refers only to the no-load operation; as that LDO uses an adaptive biasing technique, its quiescent current increases as the load current increases, reaching values above 100µA at full load.
The smallest quiescent current is reported by [13] and it achieves better FOMs value than the LDO presented here. In fact, the circuit we introduced in [13] is a particular case of the topology shown in Fig. 2, with a circuit implementation optimized for ultra-low power consumption. The error amplifier in [13] employs a common-gate input stage, to maximize the speed. Thus, it consumes only 0.7µA and its transient response is slightly below 300mV for a load jump of 100mA. However, it is inferior to the LDO presented in this paper with respect to three other parameters: its PSR value at low-frequency is 20 dB smaller, the output noise at 100 kHz is five times larger and its output voltage overshoot caused by a 300 mV/2.5 µs line jump is 1.5 times worse.
The LDO presented here exhibits the largest V out_pkpk for C L = 0, but a value of 1pF was used to calculate FoM1. Even so, the FoM1 value for the proposed LDO is the second best, 14 times better than the nearest competitor, [20], and 30 times better than the next one, [6].
The LDO presented here also yielded the second-best FOM2 value, overtaken only by the LDO we reported in [13], which is based on the same topology.
To calculate the FOM3 for the LDO presented here the maximum C L value was considered 1 µF, as measurement results were presented only for this value. Under these conditions, our LDO occupies the third place, with an FoM3 value twice as large as the second-best. However, it should be noted that the LDO reported in [7] owns its second place to its large maximum C L value, 47 µF, a value the LDO presented here can handle, according to Fig. 17(c). Table 2 lists the main parameters of other seven LDOs, this time designed for load capacitors with maximum values in the hundreds of pF range. When compared against these LDOs, the LDO described in this work exhibits the best FoM1 value -21 times better than the second best, [4] -and the second-best FoM2 value. It should be noted that the best FoM2 is yielded by the LDO reported in [22], which occupies the third position with respect to FoM1.
The data presented in Table 1 and Table 2 indicates that the LDO proposed in this work performs very well against its competitors in terms of power consumption and ability to handle a wide range of load capacitors, while ensuring a good response to steep and large variations of the load current.

IV. CONCLUSION
This paper presents an LDO topology and a circuit implementation that provides fast responses to load transients and can handle any practical capacitive loads, from near-zero to tenhundreds of µF. Besides the main voltage control feedback loop, the LDO topology employs an additional feedback loop, connected directly between the LDO output and the gate of the pass transistor. This additional loop is implemented by a novel circuit, which not only ensures a fast response to load transients but also helps improve the LDO frequency compensation, especially at light loads. This circuit can be used in conjunction with most types of error amplifiers, for LDOs that exhibit a relatively large small-signal resistance between the gate of their pass transistor and the ground line.
A very compact transistor-level implementation of the proposed LDO was presented: the Fast transient & Frequency compensation circuit described above was embedded into the structure of an OTA with high slew rate, so that only passive elements had to be added, while all MOS transistors were obtained by dual-using transistors within the initial OTA. In this way, no additional quiescent current was required, and the die area required by the additional circuitry was minimized.
A simplified, intuitive, and effective small-signal analysis of the proposed LDO was performed; it yielded insight into the LDO operation under various conditions for the load current and capacitance, as well as key sizing equations.
An LDO based on the proposed topology and circuit implementation was integrated in a 130 nm CMOS process. Simulation results and measurements performed on a test chip confirmed the excellent performance of the proposed LDO.
A comprehensive comparative analysis was performed against fifteen LDOs reported previously, with similar levels of output voltage and current: eight of them designed for a wide ranges of external decoupling capacitors and seven LDOs designed for narrow ranges of on-chip load capacitors. Three Figure-of-Merit metrics were used, two of them introduced in previous works and one newly proposed. They considered the quiescent current, the maximum load current and load capacitance, the output voltage undershoot and overshoot -in absolute value or referred to the nominal value -and the slope of the current step. Two of them also include edge time and process scaling. The LDO reported by this work yielded the first and second-best values for two of these metrics and the third-best for the third. Therefore, one can conclude that it provides a very good overall performance, considering the power consumption and the ability to handle a wide range of load capacitors while ensuring a good response to steep and large variations of the load current. MARIUS NEAG (Member, IEEE) received the M.Eng. degree in applied electronics from the Technical University of Cluj-Napoca (TUCN), Romania, in 1991, and the Ph.D. degree from the University of Limerick, Ireland, in 1999. He joined TUCN as an Assistant Lecturer a year later. Then, he worked several years as a Senior Designer of RF, analog, and mixed-signal ICs in Ireland and USA, before returning to the academia. Since 2008, he has been an Associate Professor with TUCN, where he co-founded the Digitally Enhanced RF and Analog IC Research Group. He has coauthored over 100 scientific papers and three books on analog IC design, and three international patents. His research interests include design of PMICs, frequency synthesisers, analog front-ends, transceivers for wired and wireless communications, design methodologies for RF and analog ICs, circuit theory, and education tools and methods.
LAURENŢIU VĂRZARU received the bachelor's degree in microelectronics, optoelectronics and nanotechnologies and the M.S. degree in advanced microelectronics from the''Politehnica'' University of Bucharest, Faculty of Electronics, Telecommunications and Information Technology, in 2009 and 2011, respectively. He started his analog design engineering career in 2009 with the ON Semiconductor's Design Center, Bucharest, specializing in gate-driving circuits for power MOSFETs and precision current sensing amplifiers. Since 2016, he has been joining Infineon Technologies, Bucharest, working as an Analog and Mixed-Signal Designer in the field of automotive linear voltage regulators.
MARINA DANA ŢOPA (Member, IEEE) received the M.S. degree in electrical engineering and the Ph.D. degree from the Technical University of Cluj-Napoca (TUCN), Romania, in 1981 and 1998, respectively. Since 1983, she has been with the Department of Basis of Electronics, TUCN. She is currently a Professor and lectures on signals and systems theory. She has published over 190 articles in journals, conference proceedings and has contributed to 14 books. Her research interests include analysis and design of electronic circuits, digital signal processing, mainly audio signals, and room acoustics.