Design and Synchronization of Chaos-Based True Random Number Generators and Its FPGA Implementation

In this paper, a new chaos-based true random number generator (TRNG) and a sliding mode controller (SMC) to synchronize the proposed TRNGs are proposed. Firstly, the continuous chaotic system is transformed into a discrete system that preserves the original continuous system’s chaotic behavior and makes it easy to realize with the field-programmable gate array (FPGA) for synchronization control. Then, a discrete SMC is introduced to solve the synchronization problem of the master-slave discrete chaotic systems. Subsequently, a novel hybrid function integrated with the El-Gamal algorithm is proposed to complete the TRNG design. Finally, the FPGA-based realization of the synchronized master-slave TRNGs is implemented. The randomness quality of the proposed TRNGs has been ensured by using Shannon’s entropy and histogram analysis. Furthermore, the National Institute of Standards and Technology (NIST) test suite has also been introduced to evaluate the proposed TRNGs and compare with the existing results in the literature.


I. INTRODUCTION
In cryptographic applications, the design of random number generators is crucial. Random number generators can generally be divided into two categories, namely the true random number generator (TRNG) and the pseudo-random number generator. Generally, truly random numbers cannot be predicted and controlled in advance. The TRNG usually exists in the natural world, for example, electromagnetic noise, thermal noise signals, decay radiation of radioactive elements. However, additional high-cost hardware circuits are usually required to convert or extract the true random sequences. To obtain a low-cost random number, a method of manually generating random numbers is called a pseudorandom number generator. The advantages of pseudo-random number generators are simple and low cost.
Nevertheless, its randomness might not be satisfied and unsuitable for high-security requirements compared with The associate editor coordinating the review of this manuscript and approving it for publication was Nishant Unnikrishnan. true random numbers. Therefore, a new low-cost TRNG is worth studying. Since the state responses of chaotic systems are random dynamic behavior, sensitivity to initial values, broadband of white noise, these characteristics provide advantages for the design of TRNGs [1], [2]. However, when it is applied to communication security, simultaneously obtaining the same random numbers at both the transmitter and receiver is also a significant issue. Concerning the chaos-based TRNG design, the works [1], [2] successfully utilized chaotic systems' random property to propose a new high-speed FPGA-based chaotic TRNG. However, they had not considered the synchronization control of TRNGs. Therefore, in the communication encryption application, the same initial values must be given for the chaotic random number generators embedded in the transmitter (master) and receiver (slave), respectively. As well known, for chaotic systems, the butterfly effect is a sensitive dependence on initial conditions, wherein a small change in initial conditions can lead to vastly different outcomes [3]. Therefore, when the chaotic systems used in the TRNGs are disturbed, and  the states become slightly different, the synchronization of random numbers will be destroyed due to the butterfly effect.
We will apply the control technology to synchronize master and slave random number generators to solve this problem, which effectively solves the above-mentioned problems. With the pioneering research of Pecora and Carroll [4], many effective control methods have been proposed for chaos synchronization, such as adaptive control, fuzzy control, sliding mode control [5] and H∞ control [6], etc. Because the sliding mode control method is insensitive to system parameters and external disturbances and has good robustness, this control approach will be applied in this paper. In [7]- [9], the randomness quality of their proposed chaos-based random numbers does not meet tests of the NIST-800-22 statistical standard, so they cannot be called true random number generators. In this paper, a novel chaos-based hybrid function integrated with the El-Gamal algorithm [10] is proposed to design low-cost TRNGs. The El-Gamal algorithm is a popular asymmetric encryption algorithm. In our design architecture, the El-Gamal algorithm acts as a hybrid function for upgrading the randomness of chaotic signals to the level of true random numbers. On the other hand, with the advancement of digital signal processing with verylarge-scale integration (VLSI) technology, the computing ability and speed of the digital chips have significantly been promoted, and the price is reduced [11], [12]. FPGA is a kind of digital chip that can be programmed with the internal logic array to realize some specified functions. The advantages of FPGA are high flexibility, a short development cycle, and parallel computing function. The authors proposed novel design methods to successfully implement chaotic systems in the FPGA circuit implementation of [13], [14].
Nevertheless, there is no discussion about the design of real random numbers or the design of synchronization control for chaos-based random numbers in their research.
In [15], the authors used a new 5D hyperchaotic system and implemented it on FPGA. However, it does not consider the synchronization design. In [16], the authors proposed a new type of chaotic neurons, used adaptive control to achieve synchronization, and added a combination of XOR and shift registers for post-processing to improve randomness. In this paper, following the concept of post-processing [16], a new hybrid function algorithm designed based on the El-Gamal algorithm for post-processing possesses the advantages of the El-Gamal algorithm, which increases the quality of random numbers but also improves the security of the cipher-text.
The rest of this paper is organized as follows. Section 2 describes the discretization of continuous chaotic systems In Section 3, based on the SMC, a controller is proposed to guarantee the stability of the error dynamics. In Section 4, a hybrid function based on the El-Gamal algorithm is designed for TRNGs. In Section 5, the implementation of the FPGA circuit for TRNGs is considered. Sections 6 and 7, respectively, show the chaotic behavior after the FPGA implementation and randomness test of TRNGs. Conclusions are provided in Section 8.

II. DISCRETIZATION OF CONTINUOUS CHAOTIC SYSTEMS
This paper aims to implement the synchronized chaosbased TRNGs. First, we need to discretize the continuous chaotic system into a corresponding discrete chaotic system that still preserves the random behavior like the original continuous system. We choose the continuous unified chaotic system (UCS) for our discussion for simplicity. However, the approach proposed can also be easily extended to other chaotic systems. The continuous UCS [17] is described as follows: where x i (t), i = 1, 2, 3 denotes system states and w ∈ [0, 1] is the system parameter bridging the Lorentz attractor with the Chen attractor and the Lü attractor. For discretizing continuous chaotic systems, we consider a continuous system described byẊ where X (t) ∈ R n is the state vector, g(X (t)) ∈ R n×m is a nonlinear vector. A and B are known constant matrices with appropriate dimensions. Then the corresponding discretetime model of the system (2) can be obtained as: where T is the sampling time; Rearrange the system (1) into the form of equation (2), the system is described as follows: According to (3), the discrete-time dynamics of UCS with ω = 0.0012 and T = 0.0021 can be obtained as: To illustrate the consistency of the chaotic behavior of the discrete system (5) and the continuous system (4), we give the following simulation in Figures 1 and 2, respectively, for systems (4) and (5). The initial conditions are given as From Figures 1 and 2, it is observed that the discretized system (5) still preserves the chaotic behavior like the original continuous system (4).

III. SYNCHRONIZATION CONTROL OF DISCRETE CHAOTIC SYSTEMS
To discuss the synchronization of TRNGs, the following master and slave systems are described, respectively, as Master discrete UCS: Slave discrete UCS: where x i , i = 1, 2, 3 and y i , i = 1, 2, 3. are state variables of the master and slave systems, respectively. The control input u(k) ∈ R introduced into (7) will be designed later to guarantee the synchronization of both the master and slave UCSs. The definition of e i (k) = y i (k) − x i (k), i = 1, 2, 3, the dynamics of synchronization error between the master and slave systems given in (6) and (7) can be described by the following equation: To complete the SMC design for synchronization, we first select a switching function as follows: where c is a design parameter quickly decided later. Assume the system is in the sliding manifold, i.e., s(k) = 0. Then we have: Therefore, when the system enters the sliding mode, i.e., s(k) = e 2 (k) + ce 1 (k) = 0, from (8) and (10), we have: If c is selected satisfying |0.9798 − 0.0208 c| < 1, by (11), e 1 (k) will converge to zero, and because e 2 (k + 1) = −ce 1 (k) in (10), then e 2 (k) will also converge to zero. We can observe that the dynamics of e 3 (k) will degenerate to e 3 (k + 1) = 0.9944e 3 (k) and then converge to zero. So, the system can reach complete chaos synchronization in the sliding manifold. After guaranteeing the synchronization in the sliding manifold, we still need to design an appropriate SMC to ensure the fact of s(k) = 0. Theorem 1: If the controller u(k) in (7) is appropriately designed as then the sliding motion (i.e., lim k→∞ s(k) = 0 ) is guaranteed. where |α| < 1 and f (k) = −(0.058e 1 (k) + 0.9985e 2 (k) − 0.0021(y 1 (k)y 3 (k) +x 1 (k)x 3 (k)) + 0.9798ce 1 (k) + 0.0208ce 2 ) (13) Proof: From (8) and (9), we have (14) Substituting (12) into (14), we can obtain s(k + 1) = αs(k). Since α is selected satisfying |α| < 1, lim k→∞ s(k) = 0 can be ensured.
Consequently, numerical simulations are performed to verify the synchronization of SMC design. For simulation, the initial conditions of master and slave systems are selected as x 1 (0) = 0.2, x 2 (0) = −0.3, x 3 (0) = 0.1, and y 1 (0) = −0.8, y 2 (0) = 1.2, y 3 (0) = −1 and the parameters in (9) and (12) are given as α = 0.1, c = 47 satisfying, respectively, |α| < 1 and |0.9798 − 0.0208c| < 1. Figure 3 shows the dynamic error responses between the master andslave VOLUME 10, 2022   discrete UCSs, and Figure 4 shows the master (left) and the slave (right) strange attractors of discrete UCSs. From Figures 3 and 4, we can observe that the state response of the slave can be synchronized with the master, and the dynamic error will also converge to zero as expected.

IV. DESIGN OF TRUE RANDOM NUMBER GENERATORS
After solving the synchronization problem of master-slave chaotic systems, we introduce a novel TRNG design that integrates synchronized random-like chaos signals with the El-Gamal algorithm. The El-Gamal encryption algorithm has high security [10], which means that the El-Gamal encryption algorithm can convert plaintext into complex random ciphertext. So, to improve the randomness of the original discrete UCS, an El-Gamal-based hybrid function is firstly proposed, as shown in Figure 5.
The El-Gamal-based hybrid function F(r, x, Seed) in Figure 5 is described as follows: step.1 Randomly select a prime number p, p ∈ Z * P . step.2 Select a prime number g, g ∈ Z * P . step.3 Convert chaos state to the IEEE754 format (see Figure 6 below), and use bits 16-23 of state step.4 Calculation y = g x mod p. step.5 Use bits 16-23 of state x 2 in IEEE754 format as a random positive integer r, r ∈ Z * P−1 . step.6 Select the x 3 byte (bits 23-16) as the Seed. step.7 Obtain the random value, result1= (Seed ·y r ) mod p. After introducing the El-Gamal-based hybrid function, the algorithm is proposed in Figure 7 to obtain the TRN sequence.
In Figure 7, results i, i = 1, 2, 3 are obtained from the El-Gamal-based hybrid function in Figure 5 with the chaotic signals x i . Furthermore, the result i, i = 1, 2, 3 is then mapped again by the El-Gamal-based hybrid function, and the design of the TRN generator is completed.

A. SECURITY ANALYSIS OF TRN
The National Institute of Standards and Technology (NIST) test [18] suite evaluates the randomness of the numbers obtained from the FPGA output. First, we set the length of the sequence by 10 5 bits or 10 6 bits, the number of subsequences is selected by 10 or 100. When the outcome value ≥ 0.01 passes the test, it confirms that the proposed TRN sequence is a true random number.
From Table 1, we can observe that the original states of the UCS have not passed all test items and only passed the Non-Overlapping-Template test. However, after the modulation of the El-Gamal-based hybrid function, the randomness has been improved a lot, but it still has not reached the standard of the NIST test, and the modulated TRNG passed all the test items. Also, we compare our results with the published papers [19], [20]. We perform the NIST test according to the conditions set by each paper. In the paper [19], the tested random number is 7000bits, and the bitstream length is set to 2, and the comparison results are given in Table 2. For the paper [20], the tested random number is 10000bits, and the bitstream length is set to 100, and the comparison results are given in Table 3. According to the comparison results, under the individual test conditions, we can see that our results might not be the best in all test items. This is because each random number generator has its advantages.  However, judging from the sum of the outcomes in all test items, the TRN we proposed is better than others, and it can also show that our proposed TRN has better randomness characteristics.

V. FPGA CIRCUIT IMPLEMENTATION
In this part, the above-mentioned TRNGs design is then implemented on FPGA, and IP core (intellectual property   core) is designed through Vivado HLS (high-level synthesis). The production unit has used units such as subtractor, adder, and multiplier. PYNQ (Python Productivity for Zynq) is a development version based on the ZYNQ architecture and supporting Python. The development version used in this paper is PYNQ-Z2. The special feature of PYNQ is the built-in interactive logic that encapsulates the ARM processor and FPGA. Users can directly edit programs through Jupyter interactive notebook and Python API, and programmable logic circuits are introduced as hardware libraries or provide hardware acceleration functions for the system.
We utilize FPGA to implement the proposed TRNG and their synchronization design, as shown in Figure 8. The master-slave discrete UCSs are synchronized by the synchronization controller presented in Section 3. Hence, we can simultaneously obtain the master-slave synchronized TRNs. Figure 9 shows the wiring diagram, it contains two (master and slave) discrete UCS intellectual property (IP) cores, eight mixed functions IP cores, and GPIO IP core. FPGA chip statistics have been obtained and given in Table 4. Table 5 shows the latency and throughput of the proposed TRNG. VOLUME 10, 2022

VI. CHAOTIC BEHAVIOR WITH THE FPGA IMPLEMENTATION
Next, we use FPGA to implement the above-designed TRNGs. The initial conditions are set to x 1 (0) = 3, x 2 (0) = 6, x 3 (0) = 9, for realization. The responses of the state variables with FPGA implementation are recorded and shown in Figure 10. By observing Figure 10, it reveals that there are strange attractors peculiar to the chaotic system through the FPGA implementation, which shows that the chaotic behavior is still preserved after the FPGA implementation.
In Figure 11, with the initial conditions x 1 (0) = 0.2, x 2 (0) = −0.3, x 3 (0) = 0.1, we show two thousand TRNs states to show the randomness of obtained TRNs. In Figure 11, k is the sampling interval. Since the TRN data is 8bit, the state range will be between 0 and 255.
Next, to show the synchronization of the master and slave TRNGs in FPGA, we display 100 data of our master and slave TRNGs. The initial conditions are selected as   Figure 12, the synchronization controller is not enabled, and the output signals of the master-slave TRNs cannot be synchronized. After allowing the synchronization to a controller, the master-slave TRNs can be synchronized as expected, as shown in Figure 13.

VII. INFORMATION ENTROPY AND HISTOGRAM ANALYSIS
In the section, we give information entropy and histogram analysis. Shannon's entropy formula [21] is given as follows: where P(TRN ) is the probability of appearance of the data proposed TRNG, and it may either be 0 or 1. We generate 70,000 bits for the proposed TRNG, where the probability of P(0) is 0.498%, the probability of P(1) is 0.502%, and the deviation between the two is 0.004% Substituting equation (15), we get: H shannon = −0.498 · log 2 0.498 − 0.502 · log 2 0.502 = 0.99999 (16) The results given in Table 6 reveal that the information entropy H shannon obtained from the proposed TRNG is very close to the ideal value. It shows that the bit-level random numbers obtained from the proposed TRNG have a uniform distribution, making it difficult to predict. A. HISTOGRAM ANALYSIS [22] In this analysis, the initial value of UCS is set to x 1 (0) = 0.6, x 2 (0) = 0.8, x 3 (0) = 0.2, and a total of 100,000 data are generated. It can be seen from Figure 7 that the proposed TRNG can get 8 bits at one time, so here will be presented as integers from 0 to 255. The three states of the UCS chaotic system and the proposed TRNG histogram analysis are shown in Figure 14.
From the histogram analysis in Figure 14, the uniformity of the original chaos states has been improved very well by the proposed TRNG design.

VIII. CONCLUSION
In this paper, a novel chaos-based hybrid function integrated with the El-Gamal algorithm has been proposed to design TRNG. Moreover, a discrete sliding mode control (SMC) method has been designed to guarantee the synchronization of the master-slave discrete unified chaotic systems. Furthermore, the random bit sequences produced by TRNG have been evaluated by NIST-800-22 statistical standards and compared with the existing results in the literature to demonstrate their validity and correctness. Finally, the proposed chaos-based TRNGs and their synchronization has been implemented in FPGA. The randomness quality of the proposed TRNGs has been ensured by using Shannon's entropy and histogram analysis.