Analysis and Comparison of Series Resonant Converter With Embedded Filters for High Power Density DCX of Solid-State Transformer

A series resonant converter (SRC) operating as a DC transformer (DCX) is a candidate for the isolated bidirectional DC/DC converters of solid-state transformers (SSTs). However, the input/output current ripple of the SRC is relatively high, which requires bulky parallel capacitors and low-pass filters such as C/LC filters. These additional components reduce the power density. In addition, to operate an SRC as a DCX, a small resonant inductance is desired to reduce the voltage gain variation and achieve a faster transient response. To resolve these problems, a SRC with embedded filters is studied. Adding a clamping capacitor between split transformers not only significantly reduces current ripples and the harmonic components of the input/output currents but also connects resonant inductors in parallel to reduce the equivalent resonant inductance. In addition, dividing the resonant current into two split windings reduces the RMS current of the transformer. This paper presents a detailed analysis, a design methodology, and a comprehensive comparison with the conventional half-bridge CLLC converter with C/LC filters. 1-kW prototypes with a 600-V input voltage and 200-V output voltage demonstrate the superiority of the proposed converter; the second harmonic of the output current was significantly suppressed by 19.3 dB compared with that of the conventional converter with the same power density. The loss breakdown showed the proposed converter mitigated copper loss by 9.47% and eliminated the losses of the filter and DC-link capacitors. The prototype of the proposed converter had the highest efficiency of 95.4% at full-load among prototypes.


I. INTRODUCTION
Solid-state transformers (SSTs) have attracted much attention in the past few decades and are considered to be alternative power-electronics technologies that can replace the line frequency transformers (LFTs) of middle-voltage (MV) applications in distribution systems, traction systems, renewable energy systems, shipboard distribution systems, and possibly even future electric aircraft systems [1]- [6].
A typical cascaded configuration for a single-phase AC/DC SST is shown in Fig. 1. The isolated bidirectional DC/DC converter (IBDC) is a core component of such a The associate editor coordinating the review of this manuscript and approving it for publication was Vitor Monteiro . cascaded configuration. The basic concept of SST is reducing the volume/size by replacing LFTs with IBDCs. Therefore, an IBDC with a high-power density is required for an SST. There are mainly two candidates for the IBDC: a dual active bridge (DAB) converter [8]- [11] and a series resonant converter (SRC) [12]- [15]. The DAB features advanced voltage and power controllability and zero-voltage switching (ZVS) capability. However, the ZVS condition of a DAB depends on the load condition, and the ZVS fails especially under a light-load condition. In addition, the turn-off current of a DAB is the peak current; thus, the turn-off switching loss is large. The trapezoidal current of a DAB contains higher harmonic components, which cause a large amount of EMI. Furthermore, a closed-loop voltage control is required for a DAB [8]- [11], and an input voltage sharing control is also necessary in the AC/DC stage of a DAB-based cascaded SST [8], [9]. In comparison, the SRC features a load-independent ZVS and zero-current switching (ZCS) capability. The quasi-sinusoidal current of an SRC also leads to smaller harmonic components. In addition, the input/output voltage conversion gain can be set to unity without a closed-loop voltage control by operating the SRC at its resonant frequency. This operating mode is, therefore, regarded as a DC transformer (DCX) and is widely used in SST applications [12]- [15]. Although a DCX cannot regulate the output voltage, it is preferable for an input-series outputparallel configuration, as shown in Fig. 1, in terms of an automatic voltage-sharing capability without a closed-loop voltage control [14], [15]. For these reasons, an SRC-DCX is more suitable for the IBDC in a cascaded SST than a DAB.
In practice, however, the resonant components have some tolerance in mass production. In addition, the component values vary depending on the temperature and aging. Therefore, it is difficult to always operate the converter at the resonant frequency without a closed-loop voltage control. As a result, the automatic voltage-sharing capability will be lost. To solve the problem without a closed-loop voltage control, the ratio of magnetizing inductance L m to resonant inductance L r , which is L m /L r , should be increased to planarize the voltage gain within the tolerance range of the resonant frequency. The magnetizing inductance L m is generally designed to satisfy the ZVS condition; therefore, a low resonant inductance design is desired in a DCX application [16]. From another perspective, the SRC in SSTs should work as if it were a real transformer, which means it requires a fast transient response. Small inductance is generally desired for a fast transient response. For these reasons, the resonant inductance of the SRC needs to be as small as possible.
Generally, the input/output current ripples of SRCs are high. Therefore, low-pass filters such as C or LC filters are required to reduce current ripple and harmonics [17]- [19]. When using a C filter, some of the high current ripple flows into a DC-link aluminum electrolytic capacitor. If a high current ripple flows into DC-link capacitors, the lifetime of the capacitors becomes shorter. Therefore, a C filter with a large capacitance or bulky parallel DC-link capacitor configuration is required. When using an LC filter, an additional inductor is required. Both distributed and centralized filters are used for reducing the differential mode noise in a cascaded configuration [18], which means the number of filters increases as the number of cells increases. Thus, these low-pass filters decrease the power density of an SRC-SST.
Several methods have been proposed to solve this problem, including an interleaved converter [20]- [22], current-fed converter [23]- [26], and passive ripple-cancelling circuit [27]- [31]. Although an interleaved converter basically reduces current ripple, it has another current-imbalance problem when the resonant components have tolerance. In [20], an additional phase shift modulation is proposed. However, it is not suitable for the half-bridge topology, and it leads to more complex control. The voltage gains of the interleaved converter can be adjusted with an additional auxiliary circuit [21]; however, this adds weight and volume, which in turn results in decreasing the power density. The converter in [22] has an automatic current-balance characteristic by using the charge balance of flying capacitors. It solves the current-imbalance problem. However, the output current ripple cannot be suppressed. Current-fed converters are proposed in [23]- [26]. However, these converters require additional large filter inductors, which results in a low power density. The transient response of the current-fed converter is slower than that of voltage-fed converters due to the large filter inductance. To reduce the filter inductance, an interleaved technique is required, even with current-fed converters [25], [26]. Passive ripple-cancelling circuits are proposed in [27]- [31]. These circuits require additional magnetic components such as transformers or coupled inductors and capacitors. These auxiliary circuits can be used for cancelling ripple and cannot be used for transferring power. In addition, the circuits can cancel the current ripple of either the input or output currents. Therefore, they are not suitable for bidirectional applications.
To solve the above-mentioned problems, we previously proposed a ripple-cancellation technique for input/output currents [32], [33]. The proposed ripple-cancellation circuit just requires an additional clamping capacitor on each port for cancelling current ripple, which means the magnetic components play two roles, transferring power and cancelling ripple. In addition, the circuit has symmetry because the circuit can be used as both an inverter and rectifier. Thus, this proposed circuit can be easily applied to bidirectional converters. A bidirectional isolated ripple-cancellation converter based on this technique was proposed in [34], and a bidirectional built-in filter converter was proposed in [35]. On the basis of the converters in [34] and [35], converters for three-port and high-voltage applications were proposed in [36] and [37]. The converters in [34]- [37] are classified as being in the DAB family. However, the SRC-DCX is more suitable for SSTs than DAB, as mentioned above. Thus, a ripple-cancellation SRC-DCX converter was proposed in [38]. According to [34]- [38], compared with conventional converters, ripple-cancellation converters do not require an input/output filter and can use a miniaturized EMI filter. In [34], [35], and [38], the operating principles of the ripple-cancellation converter and superiority against EMI are presented. However, a quantitative analysis of ripplecancelling characteristics, the dynamics of the proposed converter, and a loss breakdown are not presented in detail. A detailed parameter design of the converter is not presented either, especially for the clamping capacitors. The power density may decrease when using clamping capacitors with a large capacitance. In addition, a comprehensive comparison with the conventional converters with filter circuits is not presented either.
This paper presents a detailed analysis of the proposed converter in [38] and a comprehensive comparison with the conventional SRC to verify the superiority of the proposed converter. An analysis of the proposed converter is shown in detail including a quantitative analysis of ripple-cancelling characteristics, component stress, and a dynamic model in section II. The tolerance of the resonant components is discussed in section III. Section IV explains the design methodology of the proposed converter. A loss breakdown among the proposed converter and conventional SRC with C/LC filter circuits is given in section V. A comprehensive comparison including voltage gain, harmonic components, power density, transient response, and efficiency are shown in section VI. Section VII is the conclusion.

II. ANALYSIS OF PROPOSED CONVERTER
Circuit diagrams of a conventional half-bridge CLLC (HBCLLC) converter [39] and the proposed ripplecancellation CLLC (RCCLLC) converter are shown in Fig. 2. The diagram of the proposed converter is the same as the bidirectional isolated ripple-cancellation converters proposed in [34] and [35]. However, the passive components work differently. Here, L 1 , L 2 , L 3 , and L 4 are designed to be resonant inductors, and C 1 , C 2 , C 3 , and C 4 are designed to be resonant capacitors. The proposed converter consists of two halfbridge switch pairs, Q 1 -Q 2 and Q 3 -Q 4 , a split four-winding transformer, S 1 , S 2 , S 3 , and S 4 , the magnetizing inductance of the transformer, L m , resonant inductors, L 1 , L 2 , L 3 , and L 4 , resonant capacitors, C 1 , C 2 , C 3 , and C 4 , clamping capacitors, C a and C b , and two DC-link capacitors, C i and C o . In DCX applications, no voltage regulation is required; the proposed converter can operate at a fixed switching frequency with a complementary 50% duty ratio. The switching frequency is set to a frequency slightly lower than the resonant frequency because the switching period equals the resonant conduction period plus deadtime period to achieve high efficiency operation [12]. In powering mode, the switch pair on the primary side, Q 1 -Q 2 , is complementarily operated as an inverter. The switch pair on the secondary side, Q 3 -Q 4 , is operated as a rectifier. In regenerating mode, the pair on the secondary side is complementarily operated as an inverter. The pair on the primary side is operated as a rectifier. Several assumptions are made to simplify the analysis. The semiconductors are ideal. The clamping capacitors, C a and C b , and DC-link capacitors, C i and C o , are large enough to not take part in resonance and are considered to be constant voltage sources. Fig. 3 shows the key waveforms of the proposed converter. There are six operating modes in one switching cycle. In modes 1 and 4, the converter operates resonantly and transfers power, while in modes 2 and 5, which are discontinuous current modes, the converter does not transfer power. Modes 3 and 6 are deadtime durations in which ZVS is achieved. Because the operating modes are similar, only the operating principles of the half-switching cycle during the powering operation are described. Fig. 4 shows the operating modes of the proposed converter during the cycle. Each operation stage is described in detail as follows.

A. OPERATING PRINCIPLE
Mode 1[t 0 −t 1 ] : As shown in Fig. 4(a), Q 1 is turned on with ZVS at t 0 . In this mode, power is transferred from the primary to the secondary side through the transformer. The body diode of the Q 3 is conducted. The voltage across the transformer is clamped by NV o /2. Therefore, the current of L m increases linearly. Resonant inductors L 1 , L 2 , L 3 , and L 4 and resonant capacitors C 1 , C 2 , C 3 , and C 4 participate in the resonant operation. During this mode, the voltages across Q 2 and Q 4 are clamped by v Ca (t) and v Cb (t), respectively. Because of the reverse polarity of the transformer on each side, S 1 -S 2 and S 3 -S 4 , the average voltages across C a and C b are the same as the input and output voltages, V i and V o , respectively. Assuming C a and C b are large enough, the voltage stresses of Q 2 and Q 4 are represented in (1) and (2), respectively.
Mode 2[t 1 -t 2 ]: As shown in Fig. 4(b), this mode starts when the magnetizing current reaches the resonant current i rp (t), which is the sum of the inductor currents i L1 (t) and i L2 (t). Q 1 is still conducted. When the switch current i Q3 (t) is equal to zero, Q 3 is turned off. Thus, Q 3 is turned off with ZCS. In this mode, power is not transferred from the primary to the secondary side. Therefore, resonant current i rp (t) is equal to the magnetizing current. Because of the reverse polarity of the secondary-side transformer, S 3 -S 4 , the average voltage across C b is the same as the output voltage. The output current is mainly provided by C b . Thus, i c3 (t) and i c4 (t) are nearly zero.

Mode 3[t 2 -t 3 ]
: This mode is a deadtime duration. As shown in Fig. 4(c), Q 1 is turned off with a low turn-off current. The current in Q 1 commutates through the body diode of Q 2 ; thus, it turns Q 2 on with ZVS at t 3 . In this interval, Q 4 is conducted to transfer power from the primary to the secondary side. The voltage across the transformer is also clamped by −NV o /2. During this mode, voltages across Q 1 and Q 3 are clamped by v Ca (t) and v Cb (t), respectively. Thus, the voltage stresses of Since the clamping capacitors, C a and C b , are assumed to be large enough, they can be considered as constant voltage sources V i and V o , respectively. As a result, (4) and (5) are transformed to (9) and (10), respectively.
Here, I rp is the RMS value of i rp (t). By applying KCL, i L1 (t) and i L2 (t) are derived in (21) and (22), respectively.
Note that (21) and (22) hold independently of the operating modes. Currents through capacitors should be purely AC waveforms due to the capacitors' charge balance in the steady state. As a result, inductor currents consist of the two AC currents and a DC bias current that is the same as the average input current. By using (11) and (20), the AC component of the i L1 (t) can be represented in (23).
To determine I rp in (24) and (25), the charge balance of C a during one switching cycle can be applied.
Note that the resonant current of the proposed converter is the same as that of the half-bridge SRC in [40]. Thus, the current stress of the semiconductors and voltage stress of the resonant capacitors in the proposed converter are the same as those of the conventional HBCLLC converter. i L3 (t) and i L4 (t) can be derived in (28) and (29) in the same manner.
As shown in (24), (25), (28), and (29), the resonant current is divided into two inductor currents on each side. The inductor currents consist of AC and DC components. Assuming that L 1 = L 2 and L 3 = L 4 for simple calculation, the RMS values of the inductor currents are derived in (30) and (31).
Equations (30) and (31) indicate that the RMS values of the inductor currents of the proposed converter are smaller than those of the conventional converter, which reduces the copper loss. A detailed loss breakdown is given in section V. In accordance with this analysis, a comparison of the component stresses between the conventional HBCLLC converter and the proposed RCCLLC converter is summarized in Table 1.

B. GAIN CHARACTERISTICS
To identify the gain characteristics of the proposed converter, a fundamental harmonic approximation (FHA) analysis is done. The resonant components are assumed to be L 1 = L 2 = L p , C 1 = C 2 = C p , L 3 = L 4 = L s , and C 3 = C 4 = C s to simplify the analysis. The equivalent circuit of the proposed converter is shown in Fig. 5. Here, the voltages v ac1 (t), v ac2 (t), v ac3 (t), and v ac4 (t) are represented in (32)- (35). Assuming that C a and C b are large enough, v ca (t) and v cb (t) can be considered as constant voltage sources V i and V o , respectively. Thus, equations (36) and (37) Because v ac1 (t) equals v ac2 (t), and v ac3 (t) equals v ac4 (t), the resonant inductors are connected in parallel. The configuration of the resonant capacitor is a general split capacitor one. The FHA model of the conventional converter [39] and the proposed converter are derived as shown in Fig. 6. Using these models, the transfer functions of the resonant tanks can be derived. Since the difference between two models is only the coefficient of the resonant inductance, the transfer functions can be summarized into one. Due to their symmetric resonant tank, the transfer function of the resonant tank H r (s) in powering mode is described only. Transfer function H r (s) is represented in (38). where Here, Z in (s) is the input impedance of the resonant tank, Z o (s) is the impedance of the output stage, and m is the coefficient of the resonant inductance. By using (38) and (39), the voltage gains of the converters can be derived in terms of the normalized frequency f n , (40) as shown at the bottom of the page, where Here, k and Q are defined for comparison when utilizing the same resonant inductance. Fig. 7 shows the voltage gains of the proposed and conventional converters when a = 1, b = 1, k = 5, and Q = 0.3. Comparing between these two models, the gain deviation of the proposed converter is smaller than that of the conventional converter because the equivalent resonant inductance of the proposed converter is four times smaller than that of the conventional converter. To design the resonant converter as a DCX, a smaller resonant inductance is desired for planarizing the voltage gain and fast transient response as mentioned. Therefore, the proposed converter is more suitable for a DCX.

C. RIPPLE-CANCELLING CHARACTERISTICS
In contrast to the conventional resonant converter, the input/output capacitors of the proposed converter have voltage and current ripple-cancelling characteristics. Because of  their analogous operations, the ripple-cancelling characteristics on the secondary side during a positive half-cycle is described only. Fig. 8 shows the current directions, voltage polarities, and key waveforms of the current ripple of the conventional converter. Fig. 9 shows those of the proposed converter. The circuit equations of the conventional converter are derived by KVL in (42) 1 Here, v C3 (0) and v C4 (0) are the initial values of the voltages of C 3 and C 4 , respectively. When capacitor C fo is assumed to be large enough and considered as constant voltage source V o , equation (45) holds by differentiating (42).
By (43)-(45), the output current i o (t) and the current ripple i Cfo (t) are represented in (46).
Generally, C 3 and C 4 are designed to be the same; thus, the output current is half of the resonant current, and the output current ripple, whose amplitude is also half of the resonant current, flows into the filter capacitor in the conventional converter as shown in Fig. 8(b). The output current of the proposed converter and the output current ripple are derived in (47) by (16) and (29).
As shown in (47), the output current ripple will be zero when Practically, the resonant components should be designed to be identical for each port. Thus, the current ripple will be cancelled in the proposed converter as shown in Fig. 9(b).
According to the current ripple-cancelling characteristics of both input/output capacitors, the voltage ripple on both capacitors is also cancelled. Although the current ripples of the capacitors are moved to the clamping capacitors as shown in Fig. 9(b), film or ceramic capacitors with a small capacitance can be used as clamping capacitors. Because the output voltage ripple is cancelled, using a small clamping capacitance does not cause any voltage variations in the input/output. Therefore, the propagation noise is suppressed by this feature. In addition, the design of the input/output capacitors needs to consider only the energy transfer during the transient operation of the converter because input/output capacitors are free from large current ripples.

D. EMBEDDED π FILTER
On the basis of the average DC current paths, the proposed converter has embedded π filters at both the input and output. Fig. 10(a) shows the average DC current paths of the proposed converter. In the steady state, the average current through the capacitor is zero. Accordingly, the mid-terminal average current is zero. Thus, the mid-terminal is open in the average switch model. As a result, switch pairs Q 1 -Q 2 and Q 3 -Q 4 can be replaced by rectifier current sources i rect and Ni rect as shown in Fig. 10(b). The rectifier current sources are in parallel to the clamping capacitors. Consequently, the clamping capacitor, resonant inductors, resonant capacitors, and DC-link capacitor compose a π filter to suppress differential mode noise on each side. The resonant inductors work for not only transferring power but also for filtering current ripple in this converter. Thus, an additional filter inductor is no longer necessary.

E. DYNAMIC MODEL
Since voltage regulation is implemented in the part of the AC/DC converter in the SST, the dynamics of the proposed converter with open-loop control is of high interest because its output voltage is a control target of the part of the AC/DC converter. The proposed converter has the characteristics of the SRC and the embedded π filter as discussed in the previous sections. Therefore, the dynamics of the proposed converter is derived by combining two characteristics. The dynamics of the SRC has been accurately modeled by a passive equivalent circuit [41]. The equivalent circuit is derived by converting the total resonant inductor and total parasitic resistance to DC equivalent ones. The DC equivalent resistor R dc is derived on the basis of the energy consumption of the resistor. The energy consumption of the total resistor should be the same as the energy consumption of the DC equivalent resistor. Therefore, the relationship is derived from (48).
The DC equivalent inductor L dc is derived on the basis of the stored energy of the inductor. The total stored energy of the resonant inductor should be the same as the stored energy of the DC equivalent inductor. Therefore, the relationship is derived from (49).
Here, R total is the total parasitic resistor, L total is the total resonant inductor, i rms is the RMS current of the resonant current, i peak is the peak current of the resonant current, and i dc is the half-cycle average value of the resonant current. By using this technique, the characteristics of the proposed converter as an SRC are derived as the DC equivalent circuit shown in Fig. 11(a). Here, V F is the equivalent voltage drop in rectifier diodes, i.e., V F = 2V diode in the considered circuit. Fig. 11(b) shows the embedded π filter when considering parasitic resistors. Here, R Lp and R Ls are equivalent series resistors (ESRs) of each winding on the primary-side transformer and on the secondary-side transformer. R Ci and R Co are ESRs VOLUME 10, 2022  of input and output DC-link capacitors, respectively. Since the ESRs of the resonant capacitors and clamping capacitors are small, they are ignored in the equivalent circuit. i dc in Fig. 11(a) is the same as the i rect in Fig. 11(b) because these two currents indicate the half-cycle average value of the resonant current. Therefore, these two equivalent circuits can be combined, and the developed DC equivalent circuit of the proposed converter is shown in Fig. 11(c). Fig. 12 shows the simulation results for the proposed dynamic model and an actual circuit simulation based on the parameters in Table 2. The load is changed in a step from 400 to 40 . α and β can be calculated by (48) and (49). To decide α and β, the resonant current is assumed to be a sinusoidal current, and the switching frequency is assumed to be the resonant frequency. In this case, α and β are calculated with π and π √ 2, respectively, with reference to (27). The total inductance can be calculated with L 1 //L 2 +N 2 (L 3 //L 4 ) with reference to (18). The total resistance R total can be calculated with R Lp /2 + N 2 R Ls /2 + R on because the resonant inductors on each side are connected in parallel. Here, R on is the on-resistance of the switch. The copper loss derived by the DC bias current through the inductor can be represented by R Lp and N 2 R Ls in the embedded π filter part. The proposed model coincides with the actual circuit simulation well during both steady state and transient period as shown in Fig. 12.

III. TOLERANCE OF RESONANT COMPONENTS
The proposed converter was analyzed assuming that the resonant components on each side were identical to those in section II. However, it is difficult to accurately align the values of the resonant components on each side in mass production. In this section, the tolerance of the resonant components is discussed. Taking the secondary side resonant inductance as an example, the tolerance is discussed. As mentioned in sections II-A and B, the resonant inductors are connected in parallel. Therefore, the equivalent resonant inductance on the secondary side is derived in (50).
Equation (50) indicates that the equivalent resonant inductance will be 0.5 L s when L 3 = L 4 = L s . As the difference between L 3 and L 4 increases, L s_eq also moves away from 0.5 L s ; however, even if the difference between L 3 and L 4 is ±20%, L eq_s will remain within a range of about ±10% for 0.5 L s . Thus, the parallel connection mitigates the impact of the difference between resonant inductances on the equivalent resonant inductance, which means reducing the change in the resonant frequency and voltage gain curve. In addition, the currents through L 3 and L 4 are represented in (28) and (29) in section II. Equations (28) and (29) indicate that when the resonant inductors are different, their current ripples become different. However, even if the difference between L 3 and L 4 is ±20%, the difference in the current ripple is about ±10%, which means one resonant inductor current ripple is 45%, and the other is 55% of the resonant current ripple. Therefore, this difference does not have a big impact on the copper loss. The output current ripple ratio is obtained with (51) in reference to (47). Fig. 13 shows the current ripple ratio i o / i rs in accordance with the inductance ratio L 4 /L 3 . As is shown, even if the difference is ±20%, the output current ripple is about ±5% of the resonant current ripple. Therefore, even if the resonant parameter has tolerance, the ripple-cancelling characteristics are effective.

IV. DESIGN METHODOLOGY OF PROPOSED CONVERTER
In this study, the specifications of the final target for the SST are an input voltage of 6.6 kVac, output voltage of 400 Vdc, and output power of 32 kW with 8 cells. Therefore, the specifications of each cell SRC are an input voltage of 1200 Vdc, output voltage of 400 Vdc, and output power of 4 kW. A prototype of the proposed circuit was fabricated as a scaled down version with an input voltage of 600 Vdc, output voltage of 200 Vdc, and output power of 1 kW. The selected resonant frequency was 100 kHz, and the turns ratio was set to 3:1. This section consists of three parts: 1) the design of the magnetizing inductance, 2) of the resonant tank, and 3) of the clamping capacitor.

A. DESIGN OF MAGNETIZING INDUCTANCE
To achieve ZVS, the magnetizing inductance L m and deadtime t d have to be carefully chosen in order to charge and discharge the output capacitance of MOSFETs, C oss , and the junction capacitance of diodes, C jc . Generally, a small L m easily achieves ZVS. However, a small L m increases the RMS current. Extending the deadtime t d can give a large L m , which would result in a low RMS current. However, this reduces the effective energy transfer and increases the RMS current when td is excessively large. Both cause a high conduction loss.
The primary-side resonant current shown in Fig. 14 can be expressed by (53).
Here, I rp is the RMS value of the primary current i rp (t), and The secondary-side resonant current can be expressed by (55) on the basis of KCL.
Here, I Lm (t) is the magnetizing current shown in Fig. 14 written as From (53)-(56), the average output current I o can be calculated as From (54) and (57), the RMS value of i rp (t) is obtained as The RMS value of the secondary current I rs can be obtained as (59), shown at the bottom the of the next page. Generally, Picture of primary-side resonant current and magnetizing current with deadtime. VOLUME 10, 2022 conduction loss on the secondary side is a large concern due to its high RMS current and the forward voltage drops of the diodes. The relationship between L m and I rs at various deadtimes from (52) and (59) is plotted as shown in Fig. 15.
As is shown, a large L m leads to a low RMS current. However, when it is excessively large, the RMS current increases again. L m and t d values were selected to be 200 µH and 300 ns, respectively, on the basis of Fig. 15.

B. DESIGN OF RESONANT TANK
It is desirable for the DCX to make the leakage inductance as small as possible for a flat voltage gain and faster response. This section discusses designing the value of k to be satisfied so that the voltage gain is flat within the tolerance range of the resonant frequency. Resonant components might generally have ±20% parameter deviations; consequently, the resonant frequency f r may vary from 0.8 f r to 1.2 f r . Thus, the voltage gain of the DCX should be unity from 0.8 f n to 1.2 f n . From (41), the relationship between k and Q is derived in (60).
Equation (60) indicates that a large k leads to a small Q. Both a large k and small Q contribute to planarizing the voltage gain. Fig. 16 shows the voltage gains under a full-load condition with several k values. The value of k should be greater than five to keep the voltage gain variation range within 5% as based on Fig. 16.

C. DESIGN OF CLAMPING CAPACITOR
To avoid the clamping capacitor from participating in the resonant operation, the easiest way is using a capacitor with a large capacitance. However, this can reduce the power density. This section discusses designing the minimum value of the clamping capacitor to be satisfied so that it will not participate in the resonant operation. For the clamping capacitor not to participate, the voltage ripple of the clamping capacitor should be sufficiently smaller than that of the resonant capacitor as shown in (61).
To simplify the calculation, the magnetizing current and deadtime are ignored here. The resonant current of the proposed converter is divided into two resonant capacitors. Thus, the voltage ripple of the resonant capacitor is written as The voltage ripple of the clamping capacitor is written as From (62) and (63), the clamping capacitor should satisfy (64).
Generally, it is necessary for satisfying the condition of being enough large as in (61) to be ten times or more. Fig. 17 shows  the clamping capacitor voltage ripple ratio v ca /V i in accordance with the capacitance ratio C a /C p . As shown in Fig. 17, the calculation result for (63) coincides with the simulation result in the range where the capacitance ratio is more than two. Therefore, the clamping capacitor should be greater than 2C p to avoid it from taking part in the resonant operation.

V. LOSS BREAKDOWN AMONG PROPOSED CONVERTER AND CONVENTIONAL CONVERTER WITH C/LC FILTERS
Taking the operation in powering mode as an example, the loss breakdown of three different structures, the proposed RCCLLC converter, the conventional HBCLLC converter with C filters, and one with LC filters, is investigated in this section. Since the ESRs of the resonant capacitors and filter capacitors are small, the ESR losses are ignored.

A. SWITCHING LOSS AND CONDUCTION LOSS
Although the resonant current of the proposed converter is divided into two resonant inductors, the current through the switch is the sum of them. Therefore, the switch currents of the three structures are considered to be the same. Therefore, the switching loss and conduction loss of each structure are estimated to be the same. Since both the proposed and conventional converters have turn-on ZVS on the primary side and turn-on and turn-off ZCS on the secondary side, switching loss occurs only at the turn-off on the primary side. The turn-off loss is represented by (65), and the conduction losses on the primary side and the secondary side are represented by (66) and (67).
Here, E off is the turn-off switching energy, R on is the onresistance of the switch, and V F is the forward voltage drop of the diode rectifier.

B. TRANSFORMER CORE LOSS
As the polarities of the transformer winding S 1 and S 2 are the reverse, DC magnetic fluxes caused by DC bias currents are cancelled. Therefore, the design of the magnetic core for the HBCLLC converter can be applied to the proposed RCCLLC converter. The magnetic flux density of the HBCLLC converter B HBCLLC and that of the proposed converter B RCCLLC are written as follows.
Here, N S1_HBCLLC , N S2_HBCLLC , N S1_RCCLLC , and N S2_RCCLLC are the number of turns for each transformer winding S 1 and S 2 , respectively. A e is the effective cross-sectional area of the magnetic core. (68) and (69) indicate that the two converters have the same magnetic flux density when the total number of turns in the HBCLLC is half the number of turns in the RCCLLC. In that case, the transformer core loss of each structure is estimated to be the same.

C. TRANSFORMER AND INDUCTOR COPPER LOSS
Since the currents through the transformer windings and the resonant inductors are the same, these copper losses are calculated together in this section. The copper loss of the conventional converter on the primary side is represented in (70).
Here, R Sp_HBCLLC is the ESR of each primary-side transformer winding of the conventional converter. In comparison, the primary-side total copper loss of the proposed converter is represented in (71) in reference to (24) and (25).
Here, I in is the input source current and R Sp_RCCLLC is the ESR of each primary-side transformer winding of the proposed converter. As mentioned in section V-B, the winding resistances of the proposed converter are estimated to be twice as large as those of the conventional converter because the total turn numbers are double. When the magnetizing current and deadtime are ignored for simple calculation, (70) and (71) are calculated in (72) and (73).
Comparing (72) and (73), it can be seen that the primary-side total copper loss of the proposed converter is estimated to be 9.47% smaller than that of the conventional converter. The secondary side is the same. VOLUME 10, 2022

D. FILTER LOSS AND DC-LINK CAPACITOR ESR LOSS
Thanks to the ripple-cancelling characteristics and embedded π filter, the current through the DC-link capacitor of the proposed converter becomes zero. Therefore, the proposed converter has no DC-link capacitor ESR loss. In comparison, in the case of the conventional converter, the current flows thorough the DC-link capacitor when using C filters. Therefore, the structure has DC-link capacitor ESR loss. The current through the input DC-link capacitor is calculated as follows.
Here, C fi is the input filter capacitor, C i_2fsw is the capacitance of the input DC-link capacitor at twice the switching frequency, and R Ci is the ESR of the input DC-link capacitor. The input DC-link capacitor ESR loss is written as follows.
When using LC filters, additional filter inductors are required. Therefore, additional copper loss of the filter inductor occurs in the structure. The filter inductor copper loss on the primary side is written as follows.
Here, R Lfi is the ESR of the input filter inductor. Although copper loss of the additional filter inductor occurs in the structure, the current through the DC-link capacitor becomes zero in the structure. The secondary side is the same.

VI. EXPERIMENTAL RESULTS
Three hardware prototypes, the proposed RCCLLC converter, a conventional HBCLLC converter with C filters, and one with LC filters, were implemented to demonstrate the feasibility of the proposed converter and compare their operation characteristics in experiments. The specifications and circuit parameters are listed in Table 3. According to Table 3, the resonant frequency of the prototype RCCLLC converter was 97.5 kHz in reference to (19), and that of the HBCLLC converter was 93.7 kHz. This difference is due to an error of the resonant components. Since an SRC has the highest efficiency at a frequency slightly lower than the resonant frequency, the normalized switching frequency of the proposed converter was set to 95 kHz, and that of the conventional converter was set to 90 kHz in the experiments for fair comparison. The filter components of the conventional converters were designed on the basis of the embedded filter characteristics shown in Fig. 10(b). Only a powering mode test was conducted in the experiments. 900-V SiC-MOSFETs, C3M0065090D, were used as the primary-side inverter switching devices, and 650-V SiC-Schottky diodes, CVFD20065A, were used as the secondary-side rectifier. The three hardware prototypes are shown in Fig. 18. The power densities of the three structures are summarized in Table 4. Since clamping capacitors are used for ripple-cancelling characteristics in the proposed converter instead of filter capacitors, the number of components is the same in the proposed converter and the conventional converter with C filters. Thus, the cross-sectional areas of the prototypes are decided by the presence or absence of the filter inductors, and the heights of the prototypes depend on the transformer core size as shown in Fig. 18. As shown in (68) and (69), if the magnetic flux densities of the two converters are designed to be the same, the cross-sectional area of the core or the total number of turns of the HBCLLC converter can be halved compared with those of the proposed converter. If the cross-sectional area of the core is halved, the power density will be improved, but the copper loss in the winding will be increased. Therefore, the same cores are used in their transformers in this research. As a result, the power densities of the proposed converter and the conventional converter with C filters are the same, and that of the conventional converter with LC filters is the lowest among the three structures because it requires additional filter inductors.

A. SOFT-SWITCHING OPERATIONS
Primary-side ZVS and secondary-side ZCS soft-switching operations are shown in Fig. 19 and 20, respectively. The proposed converter achieved primary-side ZVS and secondary-side ZCS under 10% load (100 W) and fullload (1 kW) conditions. Therefore, it had load-independent soft-switching characteristics like those of conventional converters.     indicates that the voltage gain of the proposed converter is more constant than those of the conventional converters if the resonant inductors are the same.

C. TRANSIENT RESPONSE
To verify the proposed dynamic model, the load step response of the prototype proposed converter is compared with the  proposed model. The circuit parameters of the prototype are given in Table 3, and the parameters of parasitic resistances are given in Table 2. In the experiment, the input voltage was set to 300 V. The load was changed in a step from 400 to 40 . The forward voltage drop of the diode was 1.35 V, i.e., V F = 2.7 V. The resonant current can be assumed to be a piecewise sinusoidal current because f sw is lower than f r . Referring to (48) and (49), α and β can be calculated as α = πf r f sw = 3.22 and β = π f r 2f sw = 2.25, respectively. From the above, the DC equivalent parameters can be calculated as L dc = 330 µH and R dc = 3.86 .  comprises the characteristics of an SRC and embedded π filter. From this result, the proposed dynamic model can be used for the controller design of future SSTs. Furthermore, the load-step responses of the proposed converter and conventional converter with LC filters are compared in Fig. 23. The circuit parameters of the two converters are given in Table 3. Note that the resonant inductor of the conventional converter is designed to be four times smaller than that of the proposed converter. The experimental conditions are the same as the above. As shown in Fig. 23, the response speeds of both were almost the same. Therefore, it is verified that the transient response of the proposed converter is faster than that of the conventional converter with LC filters if the resonant inductors are the same.

D. CURRENT RIPPLE COMPARISON
The key waveforms of the resonant currents and ripplecancelling characteristics are shown in Fig. 24 under a fullload (1 kW) condition. The currents after passing through filters, which are I o + i co for each structure, were measured as output currents to compare how well each filter mitigates current ripples. The output current ripple of the conventional HBCLLC converter with C filters was 3.73 A, whereas the conventional HBCLLC converter with LC filters and the proposed converter had almost no output current ripple even though the resonant current amplitudes of the three structures are almost the same. The output current spectra up to the 20th harmonic component are compared in Fig. 25. The output current spectrum of the proposed converter was suppressed by 19.3 dB compared with that of the conventional converter with C filters and was larger by 0.8 dB compared with that of the conventional converter with LC filters at a frequency of 2 f sw . In addition, the  proposed converter is as effective as the LC filters in reducing the current ripple in the higher harmonic components.
From the results, the filter capacitor needs more capacitance in the conventional converter with C filters to suppress the output current ripple. As a result, the power density will be decreased. In addition, although the conventional converter with LC filters suppressed the output current the most, the structure sacrifices power density, and the proposed converter already sufficiently suppresses output current ripple. Thus, this result shows that the proposed converter suppresses EMI most effectively without sacrificing power density.

E. EFFICIENCY COMPARISON
The measured efficiencies of the three structures are shown in Fig. 26. Among the three structures, the efficiencies were almost the same. However, the proposed converter had a slightly higher efficiency compared with the other two structures. Fig. 27 shows the loss breakdown of the three structures under a 1-kW full-load condition. As discussed in section V, the conduction loss is estimated to be the same. Since the normalized frequencies of the two converters are different, the switching loss and the transformer core loss were slightly different. The switching loss of the conventional converter  was 0.07 W less than that of the proposed converter, and the transformer core loss of the conventional converter is 0.38 W more than that of the proposed converter. Since these differences account for a small proportion of the total losses, they do not have a significant impact on the efficiency comparison. In comparison, the transformer and resonant inductor copper loss of the proposed converter was estimated to be smaller than that of the conventional converter structures by 9.47%. In addition, the ESR loss of the DC-link capacitor and copper loss of the filter inductor additionally occurred for the conventional converters with C and LC filters, respectively. For these reasons, the proposed converter had the highest efficiency among the three structures. Furthermore, since these losses increase as the power rating increases, it is expected that the efficiency of the proposed converter will be further improved compared with the conventional converter with C/LC filters at full-scale.

VII. CONCLUSION
This paper comprehensively discussed the characteristics and design methodology of a proposed converter and compared the converter with a conventional half-bridge CLLC converter with C/LC filters. The equivalent resonant inductor of the proposed converter is four times as small as that of the conventional converters. Therefore, a more constant voltage gain and faster transient response are possibly achieved when the resonant inductors have the same values. In addition, the proposed converter has ripple-cancelling characteristics and an embedded π filter. Consequently, it is superior to the conventional converters in its ability to reduce EMI. Experimental results showed that the proposed converter significantly suppressed the second harmonics of the output current by 19.3 dB compared with that of the conventional converter with C filters while maintaining the same power density, and it improved the power density compared with the conventional converter with LC filters while maintaining almost the same ripple mitigation. Thus, it enables the power density to be increased. It also inherits the advantages of the conventional SRC, such as load-independent soft-switching characteristics. Furthermore, a loss breakdown showed that the proposed converter reduced the copper loss of the transformer windings by 9.47% and eliminated the losses of filter inductors and DC-link capacitors. As a result, the proposed converter had the highest efficiency of 95.4% under a fullload condition among three structures.
These results indicate that the efficiency and power density of the proposed converter are expected to be further improved compared with the conventional converters when they are implemented at full-scale. These features allow a conventional converter to be quickly replaced with the proposed converter for high-power-density DCX-SST.