Multiphase Traction Inverters: State-of-the-Art Review and Future Trends

Multiphase inverters (MPIs) continue to increase in popularity owing to their compelling features that include enhanced fault-tolerance capability, improved per-phase power handling, and reduced dc-bus capacitor sizing. This article presents a comprehensive review on MPIs and their application in transportation electrification. More specifically, voltage source inverter (VSI) and nine-switch inverter (NSI) are the two MPI topologies reviewed herein, due to their popularity and potential for employment as traction inverters. The state-of-the-art review covers modeling and control techniques, dc-capacitor sizing, modulation strategies, inverter losses, and cost. Promising future trends of MPIs in terms of topologies, switching devices and integrated design are also investigated.


I. INTRODUCTION
Recent years have seen an uptake of electrification in all sectors of transportation: road, sea, and air [1]- [3]. In 2020, we witnessed many original equipment manufacturers (OEMs) releasing electric vehicles extending beyond the standard passenger vehicle to include sports cars [4]. This uptake is only expected to grow into the future; it is projected that more than 50% of the global sales of passenger vehicles will be electric by 2040 [5]. This is driven by the need for clean, reliable, inexpensive and sustainable transportation system as global warming concerns continue to rise [6].
The driving power of all electrified powertrains is one or more electric machines (EMs) operating either solely, or in conjunction with an internal combustion engine (ICE) [6]. Driving and controlling the EM is achieved by a traction inverter which converts the dc power drawn from the battery to a variable frequency ac power in motoring mode. Vice versa, in generation mode the inverter acts as a rectifier to transfer the kinetic energy from the vehicle back to the battery. Extensive efforts are being invested in optimizing the efficiency, power density, and cost of traction inverters. Such efforts are in line with the next-generation framework of electrified transportation that includes increased voltage and The associate editor coordinating the review of this manuscript and approving it for publication was Ton Duc Do . power ratings [7] and employment of wide bandgap (WBG) devices [8].
At the heart of traction inverters are power semiconductor devices, whose ratings might be limited in the face of the aforementioned trends. When voltage is a limiting factor, multilevel inverters (MLIs) constitute a viable solution [9]. MLIs are able to utilize switching devices with lower voltage ratings for the same or higher DC-link voltages when compared to two-level inverters. Thereby, their application in powertrains rated at and beyond 800 V is gaining a a significant attention [10]. On the other hand, when current is a limiting factor for the semiconductor devices, discrete device paralleling is the industry-accepted solution; multiple devices are connected in parallel to withstand the output current of the inverter. Tesla's Model 3 (2018), for example, employs four SiC discrete MOSFET devices per switch [11]. However, device paralleling poses design challenges pertaining to static and dynamic current sharing among the paralleled devices [12]- [15]. Mismatches between the paralleled devices lead to current unbalance, which in turn causes hot spots [14].
Alternatively, multiphase drives (MPDs), beyond three phases, thrive in delivering high-power, owing to their improved per-phase current handling [16]. With more phases to share the required output power, device paralleling issues are alleviated, or eliminated altogether [17]. Besides improved current handling, MPDs offer improved fault tolerance capability, lower torque pulsations, better noise characteristics, and modularity [16], [18].
Whether to use a multilevel inverter or a multiphase drive is a subtle question, and rather application-oriented. Increasing the powertrain voltage rating is attractive for electric vehicles (EVs) as it enables fast charging and reduces cabling footprint. On the other hand, it compounds insulation requirements. Improper insulation leads to partial discharge, which in turn causes machine failures [19]. This poses a serious threat for more electric aircrafts (MEA), for example, where reliability is of utmost importance. In such applications, meeting high power demand can be achieved by increasing the current supply at a relatively low voltage, around 400 V [20]. Heavy-duty vehicles resemble another example of high-power electrified powertrain. In such cases, MPDs are more suitable, thanks to their reduced per-phase current requirements. From another perspective, electrified aircrafts can also exploit MPDs to leverage reliability as multiphase drives have superior fault-tolerance capabilities. Fig. 1 summarizes the pros and cons of MPIs.
Both technologies, MLI and MPI, have been widely investigated in literature. Application of MLIs in transportation electrification was recently reviewed in [9]. MPDs for traction applications was reviewed [16], with a focus on sixphase drives. A little attention, though, has been paid to multiphase inverters (MPIs). This arises from the notion that conventional three-phase inverters are extendable to MPIs by simply adding additional switching legs to the existing ones [21]. Another reason is the modularity of six-phase machines with two isolated neutrals, which can be treated as two three-phase sets, commonly known as dual three-phase machines [22]. In principle, for n-phase machine with n multiples of three, the system can be decomposed into n/3 threephase systems [23]. Thus, as far as hardware implementation is concerned, these machines can be driven by multiple threephase inverters. While such reasoning is valid, the resulting MPI is usually oversized with switches rated at twice the rated current and two dc-bus capacitors, in the case of six-phase drives. Proper considerations invested in MPI design can yield improved inverter design. Along with addressing the aforementioned device paralleling issues, input parasitic can be made smaller, thanks to improved current handling in MPIs. Therefore, a higher power density can be achieved. To this end, this paper presents an in-depth review of MPIs for traction applications. More specifically, two MPI topologies are reviewed: voltage source inverter (VSI) and nine-switch inverter (NSI). The selection of those topologies is based on their potential for the applications listed in Fig. 1.
This paper is organized as follows. Modeling techniques for MPIs are discussed in Section II. Sections III and IV review multiphase VSI and NSI, respectively. Section V investigates the future trends for MPIs and the challenges hindering their adoption. Finally, Section VI concludes the paper.

II. MODELING OF MULTIPHASE INVERTERS
The spatial displacement between the phases, δ can be symmetric or asymmetric. For symmetric systems, each two consecutive phases are δ = 2π/n apart. Asymmetric distribution is exclusive to n-phase system where n is a multiple of three. In this case, the system is composed of n/3 multiples of three-phase systems with a displacement of δ = π/n between each three-phase set. Fig. 2 depicts the general phase distribution for symmetric and asymmetric MPIs.
Modeling of MPIs is an n-dimensional problem. There are two main methods to model n-phase inverters, namely vector space decomposition (VSD) and multiple dq. The two modeling approaches are reviewed in this section for multiphase inverters, in addition to the general structure of the current control loop based on such approaches.

A. VECTOR SPACE DECOMPOSITION (VSD)
The VSD technique is applicable to any n-phase system and any spatial displacement configuration. It decomposes the n-dimensional system into multiple orthogonal 2D planes or subspaces [24]. For example, the vectors in six-phase inverter-six-dimensional-are mapped into three two-dimensional subspaces, namely α-β, x-y, and 0 1 -0 2 . Clarke's transformation is extended to n-phase to yield a single transformation matrix for the multiphase space. The VSD transformation is equally applicable for symmetric and asymmetric MPIs. The power-invariant VSD transformation, in the complex vector form, for symmetric n-phase MPI is given in (1), as shown at the bottom of the page, where f α−β = f α +jf β and f can be any n-phase variable, e.g. voltage or current. Similarly, f X , X ∈ {A, B, . . . , n} is the X -phase variable in the stationary ABC . . . n frame.
The vector mapping is selected in such a way that the fundamental component is mapped into the α-β plane, whereas low order harmonics and zero-sequence components are mapped into the x-y and 0 1 -0 2 planes, respectively. Applying the VSD transformation to MPIs with n > 6 yields multiple x k -y k planes, k ∈ [1, 2, ..]. A general formulation for k in terms of n cannot be established. Five-and Six-phase MPIs have a single x-y plane, while seven-and nine-phase MPIs have two x-y planes [25], [26]. Additionally, applying VSD transformation to MPIs with odd number of phases, n, produces a single zero-sequence component (0 2 = 0), whereas two zero sequence components are produced in inverters with n even phases [27]. A special case, however, is asymmetric MPIs with 3j, j ∈ [1, 2, . . .] isolated neutrals. In such a configuration, all the vectors in 0 1 -0 2 are mapped at the origin, thus, nullifying the zero-sequence subspace [28]. Table 1 summarizes the harmonic mapping of the VSD transformation in the 2D orthogonal subspaces for five-, six-, seven-, and nine-phase MPIs.

B. MULTIPLE D-Q
Known in the literature as double d-q for six-phase inverters [16], the notion is extended herein to multiple d-q for MPIs with n multiples of three. Alternative to the VSD model-ing, which treats the n-dimensional space as one, the multiple d-q decomposes the system into multiples of three-phase systems [29]. While multiple d-q is applicable to symmetric and asymmetric spatial distributions, it is only famous for the latter in the literature.
Each three-phase set is transformed using Clarke's and Park's transformation. The stationary frames, α k -β k obtained from Clarke's transformation are transformed into the rotational frame using Park's transformation with a phase shift of kδ, k ∈ [1, 2, . . . , (n − 3)/3]. In this case, the same Clarke's transformation is used for all α k -β k frames. Thus, the transformations can be defined as: f dk−qk = e j(θ+kδ) f αk−βk , where θ ∈ [0, 2π] is the angular position. The resulting d-q frame is considered to be the sum of all d i -q i components, i.e. f d,q = f d1,q1 + f d2,q2 + · · · + f dk,qk .
C. VECTOR-ORIENTED CONTROL Fig. 3 depicts the general structure for the current control of MPIs using VSD and multiple d-q modeling techniques. In VSD (Fig. 3a), the n-phase currents are transformed into the stationary frame using T VSD in (1). Only the α-β frame is transformed to the synchronous d-q frame using Park's transformation, whereas current components in the x i -y i , i = 1, 2, . . . , k are controlled in the stationary frame.
Since the latter components carry the undesired harmonics, they are controlled to zero. The employed controllers can be proportional-integral (PI), proportional-resonant (PR), a combination of both [30], or model predictive controller (MPC) [31]. The output of the current controllers, i.e. reference voltages, are mapped back to phasor quantities using inverse transformations. The reference phase voltages are 4582 VOLUME 10, 2022 then used to generate the switching pulses. Note that an additional zero-sequence controller(s) is required when the n-phase inverter is connected to a single neutral point [32]. Current control in multiple d-q (Fig. 3b) is straightforward. Currents are transformed into multiple d-q frames using Clarke's and Park's transformations given in (2)   The number of required controllers in both modeling techniques is usually the same, regardless of spatial distribution (Fig. 2). For example, for a six-phase inverter with two isolated neutrals, four PI controllers are required in the VSD to control d-, q-, x-, and y-currents. In multiple d-q, the same controllers regulate d 1 -, q 1 -, d 2 -, and q 2 -currents. A similar performance can be achieved using both modeling techniques when the system is balanced [29]. However, multiple d-q is unable to correct for system asymmetries such as magnitude unbalance or inverter dead-time compensation. This is because the contribution of each d-q subspace to such asymmetries is usually undetermined. In this case, current control in VSD is superior as xy-currents can be exploited to correct for system asymmetries [30]. Furthermore, from drives perspective, integration of existing three-phase controls, such as flux-weakening, is seamless in VSD since the MPD is treated as a single system in the synchronous dq-frame [33], [34]. For such attributes, in addition to generality, VSD modeling is favored over multiple d-q. Table 2 summarizes the comparison between VSD and multiple d-q modeling.
After establishing the modeling techniques and the general vector control structure of MPIs, the most relevant MPI topologies are reviewed next.

III. MULTIPHASE VOLTAGE SOURCE INVERTER
Owing to its simplicity, high efficiency and low cost, voltage source inverter (VSI) is the most commonly used inverter topology in transportation electrification applications [35]. This holds true irrespective of the number of phases, n or the type of the load machine [21]. Nevertheless, multiphase VSIs have distinctive attributes that distinguish them from their conventional three-phase counterpart, such as dc-bus capacitor sizing and modulation techniques. The remainder of this section reviews such features.
A. TOPOLOGY Fig. 4 depicts the two-level (2L) multiphase VSI topology with n number of phases. For traction applications, Si IGBT and SiC MOSFET are the two most commonly used devices, with a breakdown voltage range of 600 V -1700 V [36], [37]. The dc-link capacitor is an indispensable component in VSI  as it reduces voltage fluctuations and current ripples [38]. The VSI is known for its high efficiency and low cost, however, it suffers some drawbacks. Firstly, the VSI exhibits a buck behavior where the output voltage level is lower than the dc-link voltage. Secondly, for high power applications, multiple power semiconductor devices are usually paralleled per switch, which poses design challenges as will be discussed next. Thirdly, the dc-bus capacitor is bulky and has a limited operating temperature range. In fact, it is the bottleneck in the face of achieving higher power densities as it occupies up to two thirds of the total volume of the inverter [16], [39]. While the first drawback is inherent in the VSI topology, multiphase VSIs alleviate the foregoing challenges as discussed next.

B. PER-PHASE REQUIREMENTS
One of the most notable features of MPIs is the reduced perphase current. The phase current of MPIs can be defined with respect to their three-phase counterpart as: The reduction in per-phase current in MPIs with respect to three-phase VSI is depicted in Fig. 5. The higher the number of phases the lower the per-phase current requirement is. However, this trend exhibits a diminishing return where at a certain point the reduction in per-phase current is no longer appreciated in the face of increased complexity. On the other hand, n-phase MPIs have, in large part, the same cost, owing to the same volt-ampere (VA) rating. The inverter VA rating reflects the power rating of the semiconductor switches, which in turn drives the cost in large part [40], [41]. The VA rating is given based on the per-unit voltage stress, E and the per-unit current stress, I , multiplied by the total number of switches, k. Note that E is the rated blocking voltage of the switches and is equal to V dc for 2L MPIs. Since there are two switches per leg in an n-phase VSI (i.e. k = 2n), the VA rating can be defined as: Substituting (5) in (6) yields 6EI , irrespective of n.
The significance of the reduction in per-phase requirements is twofold. Firstly, it enables the use of smaller  and lighter cables. The considerable reduction in cable size outweighs the increase in number of cables rendering a lower cost overall. This is demonstrated in Table 3, where AC cable sizing and pricing is calculated based on a 100 kW, 0.8 PF, and 230 V system for MPIs with n ≥ 3. Compared to the conventional three-phase VSI, a six-phase VSI yields a 21% reduction in cabling cost.
Secondly, the reduction in per-phase current mitigates the current limitation of the employed power semiconductor devices, especially SiC MOSFET. As of this writing, the maximum current rating of commercially available, automotive-grade discrete SiC MOSFETs is around a 100 A (see Table 7 in [37]). This limitation renders paralleling of multiple discrete devices in three-phase inverters inevitable. Tesla's Model 3 (2018), for example, employs four discrete SiC MOSFET devices per switch [11], [44]. Device paralleling makes the design of gate drivers more challenging to ensure proper dynamic and static current sharing among the paralleled devices [13]- [15]. Mismatches among the paralleled devices lead to current unbalance, which in turn causes localized over-temperature [14]. According to [15], R ON , pinch-off voltage (which determines at what gate voltage the device enters forward conduction mode), reverse breakdown voltage of the gate, transconductance, and device placement on the circuit are all factors that should be carefully monitored/designed to ensure proper operation of the paralleled devices. Normalized dc-link capacitor requirements for multiphase VSI with different phase number, n in terms of capacitance and RMS current using SPWM [39].

C. DC CAPACITOR REQUIREMENT REDUCTION
Multiphase VSIs offer reduced capacitor requirements in terms of capacitance and physical volume [39]. The capacitance, C dc is determined based on the allowable dc-voltage ripple (typically 5%) [45]. It was shown in [39] that the required C dc decreases with increasing phase number. A 50% capacitance reduction can be achieved in six-phase VSI. Additionally, the dc-voltage ripple is inversely proportional with C dc and switching frequency. This means that the same voltage ripple can be achieved with a lower C dc and higher switching frequency using SiC devices. The volume of the dc-bus capacitor, on the other hand, is dictated by the dc-link RMS current [23], [45]- [48], which depends on a couple of factors including modulation technique, modulation index, and power factor (PF). Similarly, the increased number of phases can decrease the dc-link RMS current, but the reduction is not as appealing. Yet, since the dc-bus capacitor can take up to two thirds of the total volume of the traction inverter [16], even a small reduction is appreciated nonetheless. A 10% reduction in the dc-link RMS current for n ≥ 6 was demonstrated in [39]. Fig. 6 illustrates the reduction in the C dc and dc-link RMS current for multiphase VSI with different n, with respect to three-phase VSI.

D. MODULATION
The basic PWM modulation techniques of three-phase systems are extendable to multiphase inverters. The majority of available techniques, irrespective of inverter topology, can be classified into two groups: carrier-based PWM (CBPWM) and space vector PWM (SVPWM) [49], which are discussed in this subsection. Fig. 8 depicts the classification of the most common modulation techniques for multiphase VSI.

1) CBPWM
CBPWM is the most favorable technique for multiphase inverters. This is due to the high number of permissible states in SVPWM that incurs a heavy computational burden. Furthermore, a comparison between CBPWM and SVPWM in 2L seven-phase VSI in [50], in terms of voltage and current THD, concluded that both techniques exhibit a similar performance. Hence, CBPWM is deemed a simpler yet effective technique for multiphase systems. Similar to three- phase inverters, the carrier is either a periodic triangular or sawtooth signal that control the gating signals when compared to n number of modulating sinusoidal signals, for multiphase VSI with n-phases. The CBPWM with a single carrier is commonly known as sinusoidal PWM (SPWM). Unlike three-phase VSIs, the additional legs in multiphase inverters provide an additional degree of freedom to address PWM-associated issues. For example, CBPWM techniques that reduce the common-mode voltage (CMV) in five-phase VSI were suggested in [51] and [52].
Extension beyond the traditional SPWM to interleaved multi-carrier techniques for multiphase inverters have been suggested for n multiples of three. In interleaved multi-carrier PWM, the n phases are divided into p groups of m phases, n = p·m. A multiple of p carriers, shifted by δ degrees, can be used to modulate m = 3 signals to generate the gate pulses for n switches, as shown in Fig. 7a. This strategy was implemented and reported in [53] on a 15-phase inverter. Implementation of such interleaving technique in [54] resulted in a 60% volume reduction in the dc-bus capacitor for a 55 kW sixphase inverter. However, this strategy is only limited to a segmented MPD 1 and reduces the n-dimensional control to 3-dimensional. In other words, some degrees of freedom are lost. Alternatively, the same p carriers can be used to modulate the n phases, as shown in Fig. 7b. Furthermore, phaseshifted PWM (PS-PWM) with n number of carriers, with δ phase shift between two consecutive carriers, was proposed in [55] for five-and six-phase 2L VSI in order to reduce the CMV. However, the high number of carriers increases the computational time dramatically.
Despite its simple implementation, CBPWM suffers low dc-link voltage utilization. The maximum level of dc-link In linear modulation region, the maximum output voltage is 0.5V dc (i.e. M max = 1), regardless of the number of phases [50]. CBPWM techniques in conjunction with zero-sequence injection (ZSI) were proposed for multiphase inverters in order to improve the dc-link utilization [56], increase the torque density [57], and reduce output distortion [58]. Analogous to third-harmonic injection in threephase VSI, n th harmonic injection for multiphase VSI with n odd phases was suggested in [56]. The M max for n odd number of phases is defined as [59]: For example, 5 th harmonic injection in CBPWM for fivephase 2L VSI results in 5.15% increase in output fundamental voltage, making it equal to that of SVPWM. A special case is n = 6, where (8) is only applicable when the load has asymmetric windings with a single neutral point [60]. Alternatively, multiple ZSIs can be applied to achieve a 15.4% dc-link voltage utilization, similar to SVPWM, when n is a multiple of three and the neutral points are isolated [61]. For example, six-phase VSI with dual ZSIs was demonstrated in [62]. Table 4 summarizes the maximum attainable M max in multiphase inverters with single and multiple ZSI for symmetric and asymmetric loads.

2) SVPWM
In spite of its complexity, SVPWM is yet attractive in multiphase traction inverters owing to its improved dc-bus voltage utilization, lower harmonic components, and improved fault tolerance owing to the redundant switching states for the same voltage vectors. This redundancy also provides the designer with an additional degree of freedom to optimize the performance based on a desired criterion. Numerous SVPWM techniques have been proposed in the literature for MPIs. The different techniques vary in the applied vectors and/or switching sequence. Consequently, different maximum modulation indices are derived. Nonetheless, many of the proposed techniques are based on the VSD approach discussed in Section II-A.
The α-β and x-y subspaces are commonly referred to as torque-producing subspace and harmonic-producing subspace, respectively. Put otherwise, the vectors in α-β subspace contain the fundamental components of the machine that produce a rotating magnetomotive force, while the vectors in x-y subspace only produce losses. Hence, modulation techniques usually focus on minimizing the x-y subspace contribution. While completely eliminating its effect is impossible, using the volt-second principle alternating vectors in x-y subspace can be chosen to produce a zero average of those components. Note that for multiphase inverters with n > 6 there exist more than one x-y subspaces (see Table 1).
VSD-based SVPWM for n = 5 decomposes the 5D space into two orthogonal subspaces, α-β and x-y. In general, for any n odd number of phases, voltage and current vectors are mapped into (n − 1)/2 orthogonal subspaces. Fig. 9 depicts the voltage vectors in 2L five-phase VSI, where the vectors form two concentric decagons. In VSI, there exist 2 5 = 32 voltage vectors, of which 30 are active [63]. Those vectors are categorized in three groups: large, medium, and small vectors. SVPWM techniques for 2L five-phase VSI  are normally classified, based on voltage vectors selection, as near-two vectors (NTV) and near-four vectors (NFV) [64]. While NTV techniques enjoy a superior maximum modulation index, NFV techniques are preferred for their 3 rd harmonic suppression capability.
VSD-based SVPWM for n = 6 can be classified as 12-sector based [24], [58], [65], [66] and 24-sector based techniques [67]- [69]. The latter is digitally easier to implement and yields reduced current harmonic distortion. However, two transitions belonging to two or more inverter legs occur at the same time during a sampling period [67]. As a result, asymmetric PWM waveforms are expected. On the other hand, the digital implementation of 12-sector modulation techniques is challenging since inverter legs can switch more than once in a switching period. In both schemes, the vectors are categorized in four groups: large, medium-large, medium, and small vectors, as shown in Fig. 10. The switching sequence and the applied zero vector yields continuous or discontinuous (DPWM) modulation [65], [69], [70]. In continuous modulation, all switching legs change their on/off state within one switching period at least once, whereas one (or more) leg(s) is clamped to +V dc or −V dc for at least one sector in DPWM. Discontinuous SVPWM techniques can reduce the implementation complexity at the cost of higher distortions [70], [71].
Numerous VSD-based SVPWM techniques for MPIs are invested in the reduction of CMV, induced by the high-frequency modulated inverters. The CMV excites a common-mode current, which is detrimental for many applications including motor drives and PV systems [81], [82]. The excited common-mode current contributes to motor aging rate by causing a bearing damage, insulation breakdown and electromagnetic interference (EMI) [83]. For n-phase VSI, the CMV varies in the range of ±0.5V dc , regardless of n. However, the number of levels in CMV increases with n. Figs. 11 demonstrates the CMV in 2L VSI with n ∈ {3, 5, 6, 7} when conventional SVPWM is employed. Hence, the higher the phase count the higher the degrees of freedom are to be exploited to reduce the CMV. CMV reduction based on SVPWM techniques for five-phase VSI was investigated in [72]- [76], [83]. The conventional SVPWM technique for five-phase VSIs employs large, medium and zero vectors.  The latter are responsible for the highest level of CVM (i.e. ±0.5V dc ). Hence, the suggested techniques in [72]- [76], [83] offer alternative switching techniques and patterns that eliminate the need for zero vectors, thus reducing the CMV. However, the reduction of CMV comes at the expense of performance deterioration in either voltage THD, current THD, switching loss, modulation range, or a combination of them.
Utilization of only medium vectors or only large vectors were suggested in [74]. Such techniques yield a constant CMV (i.e. CMV= 0). On the other hand, the RMS value of the CMV was still high. A competitive technique using only a combination of large vectors was suggested in [72] and employed in [83] for motor drives applications. This technique results in a CMV of ±0.1V dc while maintaining an adequate current THD. Its switching loss can also be improved when combined with the method suggested in [75] at high M . A MPC controller was proposed in [77] to improve the current performance while simultaneously reducing the CMV to ±0.1V dc and maintaining a full modulation range. This, however, is achieved at the expense of increased switching frequency.
Similarly, CMV reduction by SVPWM for n = 6 [70], [78], [79] and n = 7 [80] have been proposed. In [70], [79], and [80], zero vectors are avoided to reduce, and even eliminate, the variations in CMV at the expense of reduced modulation range. In [78], a phase shifting strategy for the PWM signals of a six-phase VSI supplying a dual three-phase asymmetric machine was proposed. The shifting strategy leads to two CMVs (from each three-phase set) that are 180 • out of phase. As a result, the total CMV, which is the sum of both, is zero. Table 5 summarizes the VSD-based SVPWM techniques for for CMV reduction in multiphase VSIs.
Besides VSD, other SVPWM techniques have been investigated for 2L multiphase VSIs such as group-based and vector classification. When n is a multiple of 3, the n-dimensional space can be treated as n/3 independent three-phase systems, given that the load has n/3 isolated neutrals. Such an approach is known as a group-based SVPWM. In [23] and [39], group-based SVPWM techniques were applied to 2L nine-phase VSI. An improved performance, in terms of voltage and current harmonics, was reported when compared to VSD-based SVPWM techniques. Additionally, it was demonstrated in [39] that group-based SVPWM can reduce dc-link capacitor requirements. More specifically, it was found that C dc in a nine-phase VSI with group-based SVPWM has to handle only one third of the dc-link RMS current when compared to a three-phase VSI modulated via SPWM. Hence, the modulation technique can play a key role in achieving a higher power density in multiphase inverters.
Vector classification (VC)-SVPWM was investigated in 2L six-phase VSI in [84]- [86]. The VC-SVPWM is based on the double d-q modeling theory for multiphase systems. He et al. [86] compared VC-SVPWM to 12-sector VSD-based SVPWM techniques. They concluded that VC-SVPWM achieves a higher dc-bus voltage utilization with a simpler implementation, at the expense of higher output harmonics.

IV. NINE-SWITCH INVERTER
Nine-switch inverter (NSI) is a special VSI topology. Originally conceived in the late 2000's to independently drive two three-phase machines with reduced switch count [87], NSI was later adopted for six-phase machines [88]- [93]. This section reviews the NSI topology and compares it to the six-phase VSI in terms of cost, control, and efficiency.

A. TOPOLOGY
The NSI topology is depicted in Fig. 12, where a six-phase inverter is realized by three legs only, each comprising three switches. Instead of the twelve switches needed for six-phase machines in the traditional 2L VSI topology (Fig. 4), NSI utilizes only nine switches. The middle switches of the NSI, S m are controlled via an exclusive OR (XOR) logic gate to prevent a leg short-circuit, as detailed in the next subsection. The NSI topology is also extendable to any (3n + 3)-switch inverter, where n is the number of three-phase sets [87]. For example, a 12-switch inverter can be developed for nine-phase applications with four switches per leg, in contrast to the 18 switches in nine-phase VSI.
While NSI employs reduced switch count, the current rating of its switches is relatively larger than their counterparts in six-phase VSI. Fig. 13 depicts the relationship between input leg current and output phase currents of the NSI for leg A, when connected to an asymmetric load (i.e. δ = 30 • ). The input leg current is the vector summation of the two output phase currents as illustrated in Fig. 14. Its magnitude for an FIGURE 13. Current waveforms of leg A, i legA and associated phase currents, i A1 and i A2 of the NSI in Fig. 12 for asymmetric six-phase load (switching frequency: 30 kHz). arbitrary δ, defined in Fig. 2, can be generally defined as: where I A and I A1 are the magnitude of leg and phase currents, respectively, as depicted in Fig. 12.
A fair comparison of inverter cost can be evaluated using the volt-ampere (VA) rating of the inverter, as discussed in Section III. Table 6 compares the inverter VA ratings of the NSI and VSI for the different load configurations. The values in Table 6 assumes three-phase VSI for base values. Since the discussion is limited to 2L inverters, the switches in both, VSI and NSI, are rated at E, irrespective of number of phases. The per-unit current rating, I of the switches in VSI for n phases is given in (5), whereas for NSI it is defined as: From the VA rating comparison, it is evident that NSI has a higher cost compared to six-phase VSI. The total VA rating for VSI is always 6 p.u., as discussed in the previous section. Considering six-phase asymmetric machine as a load, the cost ratio of NSI to VSI is three to two. Power semiconductors dictate around 40% and 70% of the total cost of traction inverters in the case of Si IGBT and SiC MOSFET, respectively [94], [95]. Hence, the NSI topology could be more expensive than VSI. It also follows that the reduced switch count in NSI does not necessarily mean reduced cost. At the expense of increased cost, NSI has the potential for higher power density owing to its reduced switch count and associated gate drivers. Furthermore, because the commutation time of the inverter legs is relatively larger, to supply two phase currents, the stress on the dc-bus capacitor is alleviated. In other words, there exists a current path from the switching VOLUME 10, 2022 pole to the load for a longer time within one switching cycle, when compared to VSI. Therefore, less commutation spikes are experienced by the dc-capacitor in NSI. Fig. 15 compares the normalized maximum stress on the dc-link capacitor in VSI and NSI topologies. Judging by the maximum current stress, NSI can achieve dc-capacitor size reduction by approximately 16% when compared to its six-phase VSI counterpart, or 26% with respect to the conventional three-phase VSI.
One of the main drawbacks of the NSI, however, is the low dc-link voltage utilization by the established modulation techniques [16]. The NSI requires 20% or 33% higher input voltage with respect to its VSI counterpart in order to produce the same output power when the winding of the load machine is asymmetric or symmetric, respectively [88]. A NSI topology with a boosting feature has been recently proposed in [96] to overcome this issue. With the help of input inductor and diodes the boosting NSI yields a higher dc-link voltage utilization.

B. MODULATION
Similar to the VSI topology, the modulation techniques of the NSI can generally be categorized into CBPWM and SVPWM techniques. Additionally, the operation of the NSI can be divided into common-frequency (CF) and differentfrequency (DF) modes [97]. In CF mode, both three-phase sets (upper and lower sets in Fig. 12) operate at the same frequency, whereas in DF mode each of the two sets is operated at different frequency. Again, when the NSI is utilized to drive a six-phase machine, it is desired to have all sets operating at the same frequency, thus only CF mode is considered for multiphase drives applications. The CBPWM and SVPWM techniques of the CF mode of the NSI are reviewed in this subsection.

1) CBPWM
Similar to the VSI, the reference voltages of the NSI are compared with a carrier waveform to produce the gating signals of the switches in CBPWM [88]- [90], [92]. However, there are three distinct differences in CBPWM for the NSI. Firstly, each three-phase set can be controlled independently, and as such, has its own modulation index. Secondly, to guarantee that each of the two three-phase sets supply the same power, the modulating signals of the two sets must not overlap. Consequently, a vertical offset in the positive and negative directions is added to the upper and lower three-phase sets, respectively. While the modulation index and the offset values can be different for each three-phase set, they are chosen to be the same when supplying a single six-phase machine [88]. Thirdly, as mentioned earlier, the gate signals of the middle switches are generated by XOR-ing the gate signals of the upper and lower switches to prevent a short-circuit. Fig. 16 depicts the CBPWM technique for the NSI.
As mentioned in the previous subsection, the modulation index of the NSI in CBPWM is influenced by the winding configuration of the six-phase machine. The maximum modulation index for the NSI topology, as a function of the spatial displacement between the two three-phase sets, δ is defined as [92]:  Using (11), the M max is 0.667 and 0.794 for symmetric (δ = π/3) and asymmetric (δ = π/6) machines, respectively. Therefore, the NSI topology is deemed more competitive when utilized in asymmetric six-phase drives. Sinusoidal modulating signals with proper offsets are used in [87]. Although the method is simple, it suffers from uneven thermal distribution among the three switches of the same leg and high switching loss. Additionally, shifting the modulating signals vertically leads to unsymmetrical switching profiles of the positive and negative half cycles which in return increases the voltage THD. Modifying the modulating signals by ZSI is investigated in [90]. The addition of the third order harmonic increases M max by 15.4%, similar to SVPWM technique [99]. However, the method in [90] could not reduce the switching loss.
In order to reduce the switching loss of NSI, DPWM was in [97], where one modulating signal is shifted vertically and the other one remains symmetric along the time axis, which is the modulating signal of higher magnitude. The method in [97] reduces the THD and the switching loss of the top and bottom switches. This method is extended in [98] to include the middle switch as well, achieving a minimum switching loss at the expense of complexity. Table 7 summarizes the comparison between those different modulation techniques.

2) SVPWM
Based on the surveyed literature, SVPWM techniques are not as common when compared to CBPWM techniques, although they enjoy the potential of improved dc-link voltage utilization and reduced switching commutation [89], [99]. This is mainly attributed to the simplicity of the CBPWM. Conversely, the SVPWM scheme for NSI is not as involved as its six-phase VSI counterpart. For the NSI, the SVPWM scheme is found upon the hexagon of the conventional 2L three-phase VSI. However, each voltage vector of the hexagon can be generated by two redundant switching states in the NSI [91]. Hence, there are a total of 14 switching states in the SVPWM of the NSI. Nevertheless, Li et al. [91] argue that not all switching states are necessary to generate the desired output. In [91], a six-mode SVPWM switching sequence was proposed, which resulted in improved efficiency at the expense of slightly higher output voltage harmonics. Authors in [100] and [101] developed an SVM that provides a decoupled control for the NSI similarly as it is two 2-level 6-switch VSIs.
The decoupled control in [100] and [101] eliminates the need for XOR gate to generate the PWM signals for the middle switches. In [101], the selection of voltage vectors to reduce the switching loss is considered which was not in [100].

C. INVERTER LOSSES
Based on the foregoing relative VA ratings of VSI and NSI, the efficiency of both multi-phase inverter topologies can be evaluated by comparing the power losses incurred by the switches. For this analysis, the considered switch is SiC MOSFET (1200V/115A) by Cree (C3M0016120D). Also, the modulators used for both topologies is SPWM.
The device switching loss is determined by the rated voltage and current stress and switching frequency, while the conduction loss is determined by the average current and onstate resistance, R DS(ON) , from the datasheet. All operating conditions including junction temperature, gate resistance and switching frequency, along with modulation index, are assumed the same. Normalized power loss with respect to the switching loss is adopted to yield a generalized comparison. Put otherwise, the rated switching loss of the SiC MOSFET is set to 1 p.u. It follows that the total per-leg switching loss for six-phase VSI is 2 p.u. The switching loss of the upper and lower switches (S u and S l ) in NSI is similar to that of the VSI, i.e. 1 p.u. However, the switching frequency for the middle switch (S m ) is twice as that of S u /S l . Thus, the total per-leg switching loss of NSI is 4 p.u.
The conduction loss of the SiC MOSFET can be determined by the average current and R DS(ON) from the datasheet. For a duty cycle D = 0.6, the conduction loss is found to be 0.6 p.u. per switch, or 1.2 p.u. per-leg in six-phase VSI. In NSI, the average current is higher than that of the VSI and can be determined by using (10). For n = 6, I = 1.73 and 1.93 for symmetric and asymmetric loads, respectively. Therefore, the conduction loss ratio between S u and S l to that of the VSI is I 2 . The difference in duty cycle for S u and S l due to the modulation offset in Fig. 16 balance out when considering per-leg losses. It follows that the conduction loss for (S u + S l ) is (0.6 p.u. × 2I 2 ) or 3.6 p.u. and 4.5 p.u. for symmetric and asymmetric loads, respectively. Lastly, S m is only on for a fraction of D equal to the modulation offset value, which is considered 0.2 herein. It follows that the conduction loss of S m is (0.6 p.u. × 0.2 × I 2 ). Thus, the  total per-leg conduction loss in NSI is 4 p.u. and 4.9 p.u. for symmetric and asymmetric loads, respectively. Table 8 summarizes the total inverter loss of NSI and VSI based on the respective VA rating of each topology. Based on this analysis, NSI is inferior to VSI in terms of inverter efficiency, and it is at its worst when supplying an asymmetric load/machine due to high I rating. VSI enjoys approximately 25% and 40% higher efficiency when compared to NSI with symmetric and asymmetric loads, respectively. The same analysis was verified numerically using the thermal model of the SiC MOSFET in PLECS by Plexim. Fig. 17 depicts the normalized losses of VSI and NSI, which are in line with those tabulated in Table 8.

V. FUTURE TRENDS
To further advance the viability and commercial feasibility of MPIs, some recent research trends have been noticed in literature. Such trends focus on improving efficiency, power density, and reliability of the MPIs. This section reviews such trends and highlights the challenges that must be addressed prior to their adoption.

A. TOPOLOGIES 1) MULTIPHASE CURRENT SOURCE INVERTER
By principle of duality, the current source inverter (CSI), shown in Fig. 18, constitute an alternative family of inverter topologies [125]. The CSI offers inherent advantages that are unavailable in VSI, such as a voltage boosting capability which enables an extended range of operation [102]- [104]. Additionally, the bulky and volatile dc-bus capacitor in the VSI is replaced with a choke input inductor, which can improve the power density of the inverter and reduce maintenance cost. Unlike the dc-bus capacitor, the input inductor is not temperature-limited and its size can be reduced by increasing the switching frequency [126]. This in turn gives way for wider operating temperatures and higher power density. Last but not least, the CSI output is PWM currents and not voltages as in VSI. Therefore, the high dv/dt issue associated with VSI is non-existent in CSI [116]. The CSI requires switches with reverse blocking (RB) capability, which has conventionally been realized using Si controlled rectifiers (SCRs) or Si IGBT with a diode in series.
On the other hand, CSI suffers a relatively low efficiency and increased control complexity. Consequently, it has traditionally been considered inferior to VSI. However, with the emergence of WBG devices, as will be discussed in the next subsection, the employment of CSI drives for automotive and MEA applications has been revisited [113]- [116]. WBG devices with RB or bidiretional (BD) capabilities, such as SiC MOSFET and Gallium Nitride high electron mobility transistors (GaN HEMT), yield superior efficiency performance and reduce the size of the input inductor, thus improving the power density. An efficiency of 97.2% was reported in [113] for a three-phase CSI with RB SiC MOSFETs. Further efficiency improvement using BD GaN HEMT devices over RB SiC MOSFET was demonstrated in [114] and [115]. Extension to multiphase CSI has been reported in literature, albeit limited to five phases. In [120]- [124], five-phase CSI-fed drive operation, modulation, and fault tolerance techniques were investigated.
Nevertheless, the bottleneck for CSI in battery-powered applications is the need for a prestage converter to be installed between the battery and the CSI to provide a controlled dccurrent [108], as shown in Fig. 18. The prestage is normally set to operate in continuous conduction mode, thus incurring high conduction loss [116]. The future of CSI traction inverter is promising, yet its commercialization is contingent upon overcoming its inherent drawbacks. For example, inclusion of a seventh switch (in addition to the six switches in three-phase systems), in different topologies, was proposed in [105], [106], [109] to reduce CMV. In [107], an LC resonant circuit across the input inductor was proposed to enable soft-switching, and therefore, improve the inverter efficiency.  A summary of recent research related to CSI from various perspectives is listed in Table 10.

2) MULTIPHASE MULTILEVEL INVERTER (MPMLI)
As mentioned in Section I MLIs have been proposed for higher efficiency, reduced harmonic distortion, lower electromagnetic compatibility (EMC) requirements, and improved fault tolerance [9]. With the trend in the automotive industry to upgrade powertrains from 400 V to 800 V and beyond [7], [127], MLI is expected to compete with the dominant 2L VSI, let alone supersede it.
Currently, the high complexity and cost associated with the high part count, make MPMLIs feasible only for MV and HV applications. However, as the market share of 800 V powertrains is expected to grow [134], [135], MPMLIs will become more feasible.

B. WBG DEVICES
A paradigm shift from conventional Si IGBT to WBG devices has been noticed over the past decade, thanks to their superior material properties [136]- [138]. Normally, the term WBG is synonym to SiC MOSFET and GaN HEMT semiconductor switches as they dominate the market share of WBG devices. However, other devices such SiC junction field effect transistor (JFET) [139] and vertical GaN [138] are under development.
In terms of technology, GaN semiconductors are considered superior to SiC as they enjoy higher breakdown field, higher switching frequency, and lower R DS(ON) [138], [140]. In contrast, device packaging, gate driver design, and EMC are deemed more challenging for GaN HEMT due to gate and parasitics ringing arising from ultra-fast switching [37]. Yet the main shortcoming of GaN HEMT is its low voltage rating (≤ 650 V). Hence, GaN devices are not applicable in traction inverters, but rather limited to on-board chargers and dcdc converters. Fig. 19 shows the power-frequency envelope of the most famous Si, SiC and GaN power semiconductor devices, highlighting the suitability for traction inverters and on-board chargers in the automotive industry.
SiC MOSFETs enjoy a multitude of features that can be exploited to produce traction inverters with a significantly higher power density [8]. Currently, the cost premium associated with SiC is challenging its wide adoption. Despite the compelling advantages of SiC switching devices over Si counterparts, they suffer reliability issues due to the thinner gate oxide layer (typically 50 nm for SiC versus 100 nm for Si) [141]- [143]. The thinner oxide layer can introduce degradation to the gate and body diode. Since SiC switching devices experience higher stress of electric field, it has been concluded that applying positive gate voltage for a long time causes a change in the threshold voltage (i.e. the minimum voltage required to turn on the device) and vice-versa for applying a negative gate voltage. This can be explained by moving the trapped electrons or holes when a gate voltage is applied causing a shift to the threshold voltage [144]. Although this phenomenon has been reduced in the second generation of the SiC MOSFETs, still 0.25 V variation is expected. This change can be limited when applying positive and negative gate voltages [142]. The gate leakage current is another concern for SiC switching devices. MOSFETs should be capable of withstanding a short-circuit current for small periods, where these currents are usually tenfold the rated value. When MOSFET experiences short-circuit current, the entire dc-link voltage is applied across the MOSFET terminals. This introduces a high electric field that causes a leakage current from the gate to the source of the MOSFET, depending on the thickness of the gate oxide layer (which is relatively thin in SiC compared to the Si devices) and the applied electric field. This leakage current causes degradation to the gate oxide layer [145].

C. MULTIPHASE INTEGRATED MOTOR DRIVES
The integrated motor drive (IMD) is a structural integration of the electric motor and the driving power electronics in a single unit. As a result of the physical integration, cost cutting is possible by the elimination of shielded cables and separate inverter housing [146]- [148]. The elimination of such components leads to 20%-40% volume reduction [149]. Furthermore, enhanced EMC is achieved, thanks to the direct connection between the two components. Researchers have been interested in combining the merits of IMDs with the merits of multiphase drives, such as higher torque density, lower torque ripple and improved fault tolerance, to yield a highly competitive motor drive for traction applications [53], [150]- [152]. A five-phase IMD with a disk-shaped, aircooled inverter was proposed in [151]. The authors reported a reduced volume when compared to its three-phase counterpart, thanks to the reduction in the dc-bus capacitor. Another disk-shaped, nine-phase inverter in an IMD structure was reported in [150]. A high power density of 35 kW/L was achieved by exploiting the reduced per-phase power handling of the MPI. In [152], a six-phase IMD drive for 48 V belt starter-generators (BSGs) was suggested for mild hybrid vehicles. The six phases were divided into three direct bonded copper (DBC) modules with air-cooling.
On the contrary, thermal management and mechanical design of IMD is very challenging [147]. Such challenges are compounded in multiphase IMD due to increased electronic components, such as sensors and gate drivers [146]. A potential solution for thermal management is the employment of WBG devices that can intrinsically operate at higher temperatures when compared to Si-based counterparts. The employment of GaN HEMT in IMD is currently a hot topic of research as reported in [115], [147], [148], and [114].

VI. CONCLUSION
This paper reviewed the state-of-the-art of multiphase (beyond three) inverters and their application in transportation electrification. Two main topologies were reviewed: voltage source inverter and nine-switch inverter. While the former is extendable to any number of phases the latter is only limited to multiples of three phases. The benefits reaped from multiphase inverters in terms of improved per-phase current handling, reduced cabling cost, dc-capacitor sizing, control flexibility were reviewed in detail and benchmarked against the conventional three-phase inverter. Comparing six-phase to three-phase inverters for example, the former employs lighter AC cables whose total cost is lower than that of the later by around 20%. Also, the volume of the dc-bus capacitor can be reduced by up to 10% or 25% when utilizing a voltage source inverter or a nine-switch inverter, respectively. Furthermore, while multiphase voltage source inverters employ a higher number of switches when compared to three-phase counterparts, both systems have the same volt-ampere rating, thus incurring similar cost in terms of power semiconductors. Such benefits make multiphase inverters suitable for high-power traction and aerospace applications.
It was found in this paper that voltage source inverter is more competitive than nine-switch inverter in terms of efficiency, fault tolerance, dc-bus voltage utilization, and cost. Although the latter employs a fewer number of switches (nine versus twelve for six-phase systems), it exhibits a higher volt-ampere rating due to the reduced number of legs, which in turn increases the current stress on the switches.
Despite the foregoing merits of multiphase inverters, they require increased number of sensors and gate driver circuitry. Additionally, design for electromagnetic compatibility can be more complex. This is due to the higher switch count, which means more sources of electromagnetic noise.