A Non-Isolated High Step-Up DC-DC Converter Using Voltage Lift Technique: Analysis, Design, and Implementation

This paper presents a new structure for non-isolated and non-inverting DC-DC converters with high voltage gain harnessing the fundamentals of the voltage lift technique. The proposed topology is a suitable structure for low voltage applications. The operation principles, the steady-state relations, and different switching strategies to further improve the voltage gain performance of the proposed converter are described. A hybrid utilization of complementary switching approach and simultaneous switching of two switches is proposed to achieve the highest voltage gain in different duty cycles. Furthermore, a theoretical analysis of power losses is provided. The suggested DC-DC converter architecture features high voltage gain, high efficiency, and low stress on semiconductor devices. In order to demonstrate these advantages, the structure is compared with some recently-presented high step-up converters in terms of efficiency, voltage gain, and voltage stress. Moreover, A 200W laboratory prototype is developed with experiments carried out to validate the given theories and feasibility of the proposed converter topology.


I. INTRODUCTION
High step-up DC-DC converters have increasingly attracted attention in recent years, primarily due to their several advantages, making them suitable alternatives to be employed in many critical applications of power electronic converters, such as renewable energy interface systems, DC distribution networks, energy storage systems, electric vehicles, and uninterruptible power supplies (UPS) [1]- [3]. Besides high voltage gain and high efficiency, the boost converters feature a low ripple input current, especially in photovoltaic (PV) and fuel cell (FC) applications, which in turn, results in achieving maximum power point tracking (MPPT) in PVs, prolong lifetime of the FCs [4], and improved dynamic performance of the system [5], [6].
The associate editor coordinating the review of this manuscript and approving it for publication was Zhong Wu .
Isolated-type DC-DC converters and coupled inductor type converters utilizing high-frequency transformers can provide high voltage gain since they can accommodate any desired transformer turns ratio [7]. However, besides the increasing volume and cost because of using magnetic elements, one drawback is the voltage spikes across the semiconductor devices due to the leakage inductance. This issue mostly requires employing snubber circuits [8], which increases the cost, complexity, and power loss [9]. Compared to the isolated structures, non-isolated DC-DC converters offer simplicity, compact size, and low cost [10]. However, the classical non-isolated boost converters cannot achieve a high voltage gain at extremely-high duty cycles due to the parasitic elements and the related losses [11]. Therefore, different architectures and techniques were introduced in the literature in response [12], such as switched-inductor (SI) [13] and switched-capacitor (SC) cells, switched-capacitor-inductor networks [14], coupled [15] and non-coupled inductors [16].
Non-coupled inductor boost converters include the cascaded converters [17] and voltage multipliers [18]. While this type of converters can provide a high voltage gain, their efficiency is limited due to the excessive number of elements. In the topologies based on the coupled inductors, energy flows through both electrical and magnetic paths, thereby generally improves the converter's performance. Nevertheless, similar to isolated structures, the leakage inductance of the coupled inductors can produce voltage spikes. Converters based on the SC technique [19]- [21] comprise switches and capacitors with minimum inductors used. Although a high voltage gain is achieved by a combination of these elements, considerable complexity, capacitors current stress issue, and poor energy efficiency poses a limitation to their wide applications. Therefore, these structures are typically used in low power applications, such as energy harvesting and in-chip design of integrated circuits (IC) [21]. The voltage lift (VL) technique is another approach to increase the performance and the voltage gain simultaneously [22]. The VL circuit can increase the output voltage by adding a charge path using diodes and capacitors. Generally, the VL technique can improve the power density, efficiency, and output voltage ripple of the classical boost converters. Additionally, it results in cost-effective and straightforward designs. Several DC-DC converters based on this technique are researched in [23], [24].
According to Fig. 1, the fuel cell requires a high step-up dcdc converter to interface it to dc-link of the inverter [2]. In this paper, a new architecture that brings together improved voltage gain, enhanced efficiency, and reduced voltage stresses is proposed for fuel cell-powered electric vehicles (EVs), validated, and compared with the state-of-the-art models. This paper is organized as follows: The operation principles, key waveforms, and the main relations of steady-state operation in continuous conduction mode (CCM) and an analysis of various switching methods are provided in Section II. Driven by the performed analyses, passive elements design, calculating voltage and current stresses of semiconductor devices, and efficiency analysis are investigated in Section III. The proposed architecture is compared with the state-of-the-art converter topologies in Section IV. In section V, the accuracy of the theoretical concepts is validated by experiments on a 200W laboratory prototype.

II. CONFIGURATION, OPERATION PRINCIPLES, AND STEADY-STATE ANALYSIS OF THE PROPOSED CONVERTER
The operation of the VL technique is based on energy transmission between inductors and capacitors, which are the storage elements of the converter. The schematic of the proposed converter is illustrated in Fig. 2, which includes two switches (S 1 and S 2 ), two non-coupled inductors (L 1 and L 2 ), three capacitors (C 1 , C 2 , and C o ), and three diodes (D 1 , D 2 , and D o ). In the following, operation modes, steady-state relations, and different switching states are analyzed.

A. OPERATION PRINCIPLES AND STEADY-STATE ANALYSIS
In order to simplify the analyses, several hypotheses are considered as follows: • All elements are considered ideal. • The converter operates in CCM and steady-state conditions.
• Capacitors are large enough to assume that the corresponding voltages are constant.
• A complementary switching is considered as the switching strategy. Other possible strategies are discussed in section II-B. The CCM operation of the converter consists of two modes, as discussed in the following.

Mode I (S 1 : ON & S 2 : OFF):
This mode lasts for t on (t on = DT s ), where T s is the switching period, and D is the duty cycle of S 1 . During this mode, D 1 and D 2 are reversebiased, and D o is forward-biased. L 1 is connected to the input source V in , and therefore, the inductor current (i L1 ) increases. L 2 , C 1 , and C 2 are connected in series along with the source to the load; as a result, their stored energy gradually decreases. The current paths of this mode are shown in Fig. 2(c), and the waveforms are shown in Fig. 2. The relations for the inductor voltages (v L1 and v L2 ) and the capacitor currents (i C1 , i C2 , and i Co ) during this interval are as follows: where I o = V Co /R is the load current.

Mode II (S 1 : OFF & S 2 : ON) :
In this time interval, which is equal to t off (t off = (1-D)T ), D 1 and D 2 are forward-biased, D o is reversed-biased, and the stored energy in L 1 is delivered to C 1 , C 2 , and L 2 . Therefore, the stored energy of C 1 , C 2 , and L 2 increases. Meanwhile, C o discharge current provides the load current. The current paths of this mode are shown in Fig. 2 (d), and the waveforms are shown in Fig. 3. The relations for the inductors voltages and the capacitors currents during this mode of operation are as follows: In order to find the average values of the capacitor voltages, the inductor voltage-second balance is applied to the derived relations of the two operation modes, which yields: The average value of the input current (I in ) and L 1 current (I L1 ) can be calculated considering the input and output power balance.
In steady-state condition, the average value of capacitor C 2 current is zero, therefore: The average value of L 2 current (I L2 ) is calculated based on the current passes through D o .
Using (12), the converter voltage gain for CCM operation (M ) is obtained as (16).

B. INVESTIGATION OF DIFFERENT SWITCHING STRATEGIES
Different features of DC-DC converters, such as voltage gain, efficiency, and voltage and current stresses of the elements, are dependent on the switching strategy. In the following, four possible switching strategies of the proposed converter, as shown in Fig. 4, are elaborated in detail.

1) COMPLEMENTARY SWITCHING FIG. 4(a))
Operation principles and relations were described. The converter voltage gain is calculated by (16). At the beginning of mode IV, V in + V C2 is greater than V C1 , hence D 2 is reverse-biased. However, C 1 is being charged, and its voltage increases, while C 2 is discharging, and its voltage decreases. Whenever V C1 = V in + V C2 , diode D 2 turns ON and starts conducting. This mode lasts for (1 − D − D 2 )T . The current paths and waveforms during this mode are shown in Fig. 5(c) and Fig. 6, respectively.
The average values of the capacitor voltages, inductor currents, and the voltage gain for this switching approach are obtained using a similar procedure as described before, which yields the following relations: The relation for I L1 is the same for all switching methods and is calculated by (14).
3) PHASE-SHIFTED WITH D < 0.5 (FIG. 4(c)) In this switching strategy, the command signal of S 2 is shifted for T s /2 seconds, and both commands have a similar duty cycle equals to D, where D is lower than 0.5 (Fig. 4(c)). Therefore, the converter includes three modes of operation: mode I, mode II, and mode V. Utilizing the same approach used for Parts II-A and II-B, the converter's main equations can be obtained as: This approach is the same as strategy 3, with a duty cycle higher than 0.5. The converter includes three modes of operation: mode I, mode II, and mode III. The main equations of the converter using this switching method are as follows: Using (16), (19), (23), and (27), the voltage gain for different switching strategies are plotted in Fig. 7. As illustrated in Fig. 7, the complementary switching approach provides the highest gain for D < 0.62, while the voltage gain with simultaneous switching for D > 0.62 is higher than other switching methods.

III. DESIGN CONSIDERATIONS OF THE CONVERTER ELEMENTS AND EFFICIENCY ANALYSIS
Proper operation of a converter is driven by the appropriate design of its components. Some important considerations regarding the passive components and the semiconductor devices must be taken into account. A procedure to design the elements of the proposed converter architecture in CCM operation are presented here and then validated by the experimental results in Section V. The switching strategy is assumed to be the complementary switching.

A. INDUCTOR DESIGN
Critical inductance is the minimum value of the inductance required to guarantee the CCM operation. By applying the current-balance law to C 1 and C 2 in CCM, and considering I LV 1 + I LV 2 = 0, the critical inductances of L 1 and L 2 are obtained as follows: where L crit1 , L crit2 , and f s are the critical inductances of L 1 and L 2 , and the switching frequency, respectively. Inductor's inductance value is determined according to the desired current ripple value, which depends on the inductor voltage (V L ), current ripple ( i L ), switching frequency (f s ), and duty cycle (D). Considering (1), (5), and (10), the inductances of L 1 and L 2 are found as (31) and (32), respectively.

B. CALCULATION OF THE CAPACITANCE
With the capacitors considered ideal, the capacitor's voltage ripple ( V C ) can be calculated. The size of the capacitor depends on its current (i C ), desired voltage ripple ( V C ), switching frequency (f s ), and duty cycle (D). Therefore, according to (1) and (8), the capacitance values of C 1 , C 2 , and C o are obtained as follows:

C. VOLTAGE STRESS ACROSS THE SWITCHES AND DIODES
Voltage stress is calculated by considering the OFF state of the switches and diodes. The voltage stress across S 1 and S 2 (V DS(S1) and V DS(S2) ) are presented in (36)

D. CURRENT STRESS OF THE SEMICONDUCTOR DEVICES
Similarly, the current stress of S 1 and S 2 (I CS(S1) and I CS(S2) ) can be found by (41)

E. CONVERTER LOSSES AND EFFICIENCY
The converter losses generally include two parts: conduction losses and switching losses. The non-idealities considered for conduction losses are the conduction resistance of the inductors (r L ), switch on-state resistance (r S ), and diodes forward voltage (V f ). Therefore conduction losses include three parts: inductor, switch, and diode conduction losses (P COND(L) , P COND(SW ) , and P COND(D) , respectively). Using the values calculated in the previous session, theoretical values of the converter losses are calculated in the following: The diodes' reverse recovery phenomenon and switches' current and linear voltage variation during switching transients are considered the source of switching losses. MOS-FET switching losses (P SW (S) ) is evaluated based on the dissipated amount of energy (E SW ) in the switches during switching transitions [8], [25] and given by (49).
The theoretically calculated converter's power losses and efficiency are shown in Fig. 8. The value of the parasitic elements and converter specifications used for efficiency calculations are the same as the prototype specifications used for model validation in section V.

IV. COMPARISONS WITH OTHER CONVERTER TOPOLOGIES
A comparison between the proposed converter and some other non-isolated structures are represented in Fig. 9 and Fig. 10. Several performance criteria are considered for this comparison, including the voltage gain, number of elements, and voltage and current stresses across the semiconductor devices. As shown in Fig. 9(a), the voltage gain of the proposed converter is higher than that achieved in [24], [26], and [27]. Compared to the topologies introduced in [13] and [16], the presented structure reveals a higher voltage gain for D < 0.58, while having a better voltage gain for D < 0.5 than the solution presented in [28]. It should be noted that, although the solution in [16] offers a higher voltage gain at higher duty cycles, it consists of three inductors in the structure, which limits the efficiency and increase the cost and volume. The variation of the normalized voltage stress of the switches and diodes versus the voltage gain are presented in Fig. 9(b) and (c), respectively, demonstrating that the proposed structure features an acceptable switch and VOLUME 10, 2022 diode voltage stresses. Moreover, Fig. 10 shows the proposed converter's efficiency for different output powers compared to other topologies, which validates its promising efficiency performance.

V. EXPERIMENTAL VERIFICATIONS
In order to validate the given theories and validate the feasibility of the proposed converter, a 200W laboratory prototype (Fig. 11) is developed using the parameters represented in TABLE 2. and TABLE 3. For the given values of V in = 24V, R = 100 , and D = 0.5, the critical inductance values for L 1 and L 2 are determined as 7µH and 20µH, respectively. As the critical values are far lower than the actual values of L 1 and L 2 , CCM operation is guaranteed.
Furthermore, to generate the required output voltage of 144V using the complementary switching strategy, the duty cycle should be D = 0.5 according to (16). But here, the duty cycle of S 1 is adjusted to D = 0.52 to compensate for the nonideal conditions as described in TABLE 3. In conclusion, the experimental results are shown in Fig. 12.

FIGURE 10.
Theoretical efficiency comparison of the proposed converter with high step-up non-isolated topologies presented in [2], [24], and [27]. The input and output voltages and currents are shown in Fig. 12(a) and (b), respectively. The voltage across the capacitors C 1 and C 2 are shown in Fig. 12(c). As can be seen, the average voltages across the capacitors C 1 and C 2 are V C1 = 48V and V C2 = 24V, which confirms (10) and (11), respectively. Furthermore, the average voltage across C o is observed at 144V, which is in accordance with that presented in (16). The voltage across the diodes D 1 , D 2 , and D o are presented in Fig. 12(f), (g), and (h), respectively, which confirms (38)-(40). The minor differences between the theoretical and experimental results are due to the effect of parasitic elements. Moreover, according to Fig. 12(i) and (j), the voltage stresses of the switches are 48V and 96V, which confirms (36) and (37), respectively. Also, the current stress   of the switches follows (41) and (42). Furthermore, the experimental efficiency results of the proposed converter are presented in Fig. 13.

VI. CONCLUSION
In the current study, a high voltage gain converter based on the voltage-lift technique was proposed and analyzed in the CCM operating condition. The voltage and current relations were extracted for different switching strategies. It was shown that, the complementary switching approach provides the highest gain for D < 0.62, while the voltage gain with simultaneous switching for D > 0.62 shows the highest value. Therefore the hybrid utilization of these strategies were proposed to achieve the highest voltage gain for different duty ratio. Furthermore, the design considerations of the proposed converter were investigated, including passive elements design, calculating the critical inductances, and assessing the voltage and current stresses. Compared to the similar state-of-the-art topologies, the proposed structure features several advantages, such as higher voltage gain and lower electrical stresses on the semiconductor devices. The highest measured efficiency was achieved at 200W output power and the converter's performance was verified by experiments on a laboratory prototype. The proposed topology represented several advantages as mentioned in the following: high voltage gain, low voltage stress on other elements, high efficiency with lower number of elements. However the topology has some constraints which the main is high voltage stress on sw 2 . Regarding these advantages and disadvantages, the proposed topology is a suitable structure for low voltage low power applications. According to [29], it has proposed a high step-up scalable voltage multiple cell based DC/DC converters, so one of the suggestions about our topology is construct n-stage boost converter. With this technique we can achieve high level output voltage with minimum elements.